1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/videodev2.h>
30#include <linux/i2c.h>
31#include <linux/delay.h>
32#include <media/v4l2-common.h>
33#include <media/v4l2-device.h>
34#include "au8522.h"
35#include "au8522_priv.h"
36
37MODULE_AUTHOR("Devin Heitmueller");
38MODULE_LICENSE("GPL");
39
40static int au8522_analog_debug;
41
42
43module_param_named(analog_debug, au8522_analog_debug, int, 0644);
44
45MODULE_PARM_DESC(analog_debug,
46 "Analog debugging messages [0=Off (default) 1=On]");
47
48struct au8522_register_config {
49 u16 reg_name;
50 u8 reg_val[8];
51};
52
53
54
55
56
57
58static const struct au8522_register_config filter_coef[] = {
59 {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
60 {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
61 {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
62 {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
63 {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
64 {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
65 {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
66 {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
67 {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
68 {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
69 {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
70 {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
71 {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
72 {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
73 {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
74 {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
75 {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
76 {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
77 {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
78 {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
79 {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
80 {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
81 {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
82 {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
83 {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
84 {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
85 {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
86 {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
87 {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
88 {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
89
90};
91#define NUM_FILTER_COEF (sizeof(filter_coef)\
92 / sizeof(struct au8522_register_config))
93
94
95
96
97
98
99
100static const struct au8522_register_config lpfilter_coef[] = {
101 {0x060b, {0x21, 0x0b} },
102 {0x060c, {0xad, 0xad} },
103 {0x060d, {0x70, 0xf0} },
104 {0x060e, {0xea, 0xe9} },
105 {0x060f, {0xdd, 0xdd} },
106 {0x0610, {0x08, 0x64} },
107 {0x0611, {0x60, 0x60} },
108 {0x0612, {0xf8, 0xb2} },
109 {0x0613, {0x01, 0x02} },
110 {0x0614, {0xe4, 0xb4} },
111 {0x0615, {0x19, 0x02} },
112 {0x0616, {0xae, 0x2e} },
113 {0x0617, {0xee, 0xc5} },
114 {0x0618, {0x56, 0x56} },
115 {0x0619, {0x30, 0x58} },
116 {0x061a, {0xf9, 0xf8} },
117 {0x061b, {0x24, 0x64} },
118 {0x061c, {0x07, 0x07} },
119 {0x061d, {0x30, 0x30} },
120 {0x061e, {0xa9, 0xed} },
121 {0x061f, {0x09, 0x0b} },
122 {0x0620, {0x42, 0xc2} },
123 {0x0621, {0x1d, 0x2a} },
124 {0x0622, {0xd6, 0x56} },
125 {0x0623, {0x95, 0x8b} },
126 {0x0624, {0x2b, 0x2b} },
127 {0x0625, {0x30, 0x24} },
128 {0x0626, {0x3e, 0x3e} },
129 {0x0627, {0x62, 0xe2} },
130 {0x0628, {0xe9, 0xf5} },
131 {0x0629, {0x99, 0x19} },
132 {0x062a, {0xd4, 0x11} },
133 {0x062b, {0x03, 0x04} },
134 {0x062c, {0xb5, 0x85} },
135 {0x062d, {0x1e, 0x20} },
136 {0x062e, {0x2a, 0xea} },
137 {0x062f, {0xd7, 0xd2} },
138 {0x0630, {0x15, 0x15} },
139 {0x0631, {0xa3, 0xa9} },
140 {0x0632, {0x1f, 0x1f} },
141 {0x0633, {0xf9, 0xd1} },
142 {0x0634, {0xc0, 0xc3} },
143 {0x0635, {0x4d, 0x8d} },
144 {0x0636, {0x21, 0x31} },
145 {0x0637, {0x83, 0x83} },
146 {0x0638, {0x08, 0x8c} },
147 {0x0639, {0x19, 0x19} },
148 {0x063a, {0x45, 0xa5} },
149 {0x063b, {0xef, 0xec} },
150 {0x063c, {0x8a, 0x8a} },
151 {0x063d, {0xf4, 0xf6} },
152 {0x063e, {0x8f, 0x8f} },
153 {0x063f, {0x44, 0x0c} },
154 {0x0640, {0xef, 0xf0} },
155 {0x0641, {0x66, 0x66} },
156 {0x0642, {0xcc, 0xd2} },
157 {0x0643, {0x41, 0x41} },
158 {0x0644, {0x63, 0x93} },
159 {0x0645, {0x8e, 0x8e} },
160 {0x0646, {0xa2, 0x42} },
161 {0x0647, {0x7b, 0x7b} },
162 {0x0648, {0x04, 0x04} },
163 {0x0649, {0x00, 0x00} },
164 {0x064a, {0x40, 0x40} },
165 {0x064b, {0x8c, 0x98} },
166 {0x064c, {0x00, 0x00} },
167 {0x064d, {0x63, 0xc3} },
168 {0x064e, {0x04, 0x04} },
169 {0x064f, {0x20, 0x20} },
170 {0x0650, {0x00, 0x00} },
171 {0x0651, {0x40, 0x40} },
172 {0x0652, {0x01, 0x01} },
173};
174#define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
175 / sizeof(struct au8522_register_config))
176
177static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
178{
179 return container_of(sd, struct au8522_state, sd);
180}
181
182static void setup_vbi(struct au8522_state *state, int aud_input)
183{
184 int i;
185
186
187 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, 0x00);
188 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_L_REG018H, 0x00);
189 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H, 0x00);
190 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH, 0x00);
191 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH, 0x00);
192 au8522_writereg(state, AU8522_TVDEC_VBI_USER_THRESH1_REG01CH, 0x00);
193 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH, 0x00);
194 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH, 0x00);
195 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H, 0x00);
196 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H,
197 0x00);
198 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H,
199 0x00);
200 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H,
201 0x00);
202
203
204 for (i = 0x30; i < 0x60; i++)
205 au8522_writereg(state, i, 0x40);
206
207
208
209 au8522_writereg(state, 0x44, 0x60);
210
211
212
213 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H,
214 AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON);
215
216}
217
218static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
219{
220 int i;
221 int filter_coef_type;
222
223
224 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
225 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
226 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
227 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
228 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
229 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
230 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
231
232
233 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
234
235 if (is_svideo)
236 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
237 else
238 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
239
240 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
241 AU8522_TVDEC_PGA_REG012H_CVBS);
242 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
243 AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
244 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
245 AU8522_TVDED_DBG_MODE_REG060H_CVBS);
246
247 if (state->std == V4L2_STD_PAL_M) {
248 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
249 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
250 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
251 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO);
252 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
253 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M);
254 } else {
255
256 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
257 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
258 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
259 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
260 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
261 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
262 }
263 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
264 AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
265 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
266 AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
267 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
268 AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
269 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
270 AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
271 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
272 AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
273 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
274 AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
275 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
276 AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
277 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
278 AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
279 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
280 AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
281 if (is_svideo) {
282 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
283 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
284 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
285 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
286 } else {
287 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
288 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
289 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
290 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
291 }
292 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
293 AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
294 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
295 AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
296 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
297 AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
298 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
299 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
300 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
301 AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
302 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
303 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
304 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
305 AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
306 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
307 AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
308 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
309 AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
310 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
311 AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
312 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
313 AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
314 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
315 AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
316 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
317 AU8522_TOREGAAGC_REG0E5H_CVBS);
318 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
319
320 setup_vbi(state, 0);
321
322 if (is_svideo) {
323
324
325
326 filter_coef_type = 5;
327 } else {
328 filter_coef_type = 5;
329 }
330
331
332 for (i = 0; i < NUM_FILTER_COEF; i++) {
333 au8522_writereg(state, filter_coef[i].reg_name,
334 filter_coef[i].reg_val[filter_coef_type]);
335 }
336
337
338
339 au8522_writereg(state, AU8522_REG42EH, 0x87);
340 au8522_writereg(state, AU8522_REG42FH, 0xa2);
341 au8522_writereg(state, AU8522_REG430H, 0xbf);
342 au8522_writereg(state, AU8522_REG431H, 0xcb);
343 au8522_writereg(state, AU8522_REG432H, 0xa1);
344 au8522_writereg(state, AU8522_REG433H, 0x41);
345 au8522_writereg(state, AU8522_REG434H, 0x88);
346 au8522_writereg(state, AU8522_REG435H, 0xc2);
347 au8522_writereg(state, AU8522_REG436H, 0x3c);
348}
349
350static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
351{
352
353 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
354 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
355
356
357 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
358
359
360 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
361
362 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
363
364 setup_decoder_defaults(state, false);
365
366 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
367 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
368}
369
370static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
371 u8 input_mode)
372{
373
374 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
375 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
376
377
378
379 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
380
381
382 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
383
384
385 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
386
387
388 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
389
390 setup_decoder_defaults(state, false);
391
392 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
393 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
394}
395
396static void au8522_setup_svideo_mode(struct au8522_state *state,
397 u8 input_mode)
398{
399 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
400 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
401
402
403 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
404
405
406 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
407
408
409 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
410
411 setup_decoder_defaults(state, true);
412
413 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
414 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
415}
416
417
418
419static void disable_audio_input(struct au8522_state *state)
420{
421 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
422 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
423 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
424
425 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
426 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
427
428 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
429 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
430}
431
432
433static void set_audio_input(struct au8522_state *state)
434{
435 int aud_input = state->aud_input;
436 int i;
437
438
439
440
441 if (aud_input == AU8522_AUDIO_NONE) {
442 disable_audio_input(state);
443 return;
444 }
445
446 if (aud_input != AU8522_AUDIO_SIF) {
447
448 printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
449 aud_input);
450 return;
451 }
452
453
454 for (i = 0; i < NUM_LPFILTER_COEF; i++) {
455 au8522_writereg(state, lpfilter_coef[i].reg_name,
456 lpfilter_coef[i].reg_val[0]);
457 }
458
459
460 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
461 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
462 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
463 au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80);
464 au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84);
465 msleep(150);
466 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x00);
467 msleep(10);
468 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
469 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
470 msleep(50);
471 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
472 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
473 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
474 msleep(80);
475 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
476 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
477 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
478 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
479 msleep(70);
480 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
481 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
482 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
483}
484
485
486
487static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
488{
489 struct au8522_state *state =
490 container_of(ctrl->handler, struct au8522_state, hdl);
491
492 switch (ctrl->id) {
493 case V4L2_CID_BRIGHTNESS:
494 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
495 ctrl->val - 128);
496 break;
497 case V4L2_CID_CONTRAST:
498 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
499 ctrl->val);
500 break;
501 case V4L2_CID_SATURATION:
502 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
503 ctrl->val);
504 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
505 ctrl->val);
506 break;
507 case V4L2_CID_HUE:
508 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
509 ctrl->val >> 8);
510 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
511 ctrl->val & 0xFF);
512 break;
513 default:
514 return -EINVAL;
515 }
516
517 return 0;
518}
519
520
521
522#ifdef CONFIG_VIDEO_ADV_DEBUG
523static int au8522_g_register(struct v4l2_subdev *sd,
524 struct v4l2_dbg_register *reg)
525{
526 struct au8522_state *state = to_state(sd);
527
528 reg->val = au8522_readreg(state, reg->reg & 0xffff);
529 return 0;
530}
531
532static int au8522_s_register(struct v4l2_subdev *sd,
533 const struct v4l2_dbg_register *reg)
534{
535 struct au8522_state *state = to_state(sd);
536
537 au8522_writereg(state, reg->reg, reg->val & 0xff);
538 return 0;
539}
540#endif
541
542static void au8522_video_set(struct au8522_state *state)
543{
544 u8 input_mode;
545
546 au8522_writereg(state, 0xa4, 1 << 5);
547
548 switch (state->vid_input) {
549 case AU8522_COMPOSITE_CH1:
550 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1;
551 au8522_setup_cvbs_mode(state, input_mode);
552 break;
553 case AU8522_COMPOSITE_CH2:
554 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2;
555 au8522_setup_cvbs_mode(state, input_mode);
556 break;
557 case AU8522_COMPOSITE_CH3:
558 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3;
559 au8522_setup_cvbs_mode(state, input_mode);
560 break;
561 case AU8522_COMPOSITE_CH4:
562 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4;
563 au8522_setup_cvbs_mode(state, input_mode);
564 break;
565 case AU8522_SVIDEO_CH13:
566 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13;
567 au8522_setup_svideo_mode(state, input_mode);
568 break;
569 case AU8522_SVIDEO_CH24:
570 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24;
571 au8522_setup_svideo_mode(state, input_mode);
572 break;
573 default:
574 case AU8522_COMPOSITE_CH4_SIF:
575 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF;
576 au8522_setup_cvbs_tuner_mode(state, input_mode);
577 break;
578 }
579}
580
581static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
582{
583 struct au8522_state *state = to_state(sd);
584
585 if (enable) {
586
587
588
589
590
591 state->current_frequency = 0;
592
593 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
594 0x01);
595 msleep(10);
596
597 au8522_video_set(state);
598 set_audio_input(state);
599
600 state->operational_mode = AU8522_ANALOG_MODE;
601 } else {
602
603
604 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
605 1 << 5);
606 state->operational_mode = AU8522_SUSPEND_MODE;
607 }
608 return 0;
609}
610
611static int au8522_s_video_routing(struct v4l2_subdev *sd,
612 u32 input, u32 output, u32 config)
613{
614 struct au8522_state *state = to_state(sd);
615
616 switch(input) {
617 case AU8522_COMPOSITE_CH1:
618 case AU8522_SVIDEO_CH13:
619 case AU8522_COMPOSITE_CH4_SIF:
620 state->vid_input = input;
621 break;
622 default:
623 printk(KERN_ERR "au8522 mode not currently supported\n");
624 return -EINVAL;
625 }
626
627 if (state->operational_mode == AU8522_ANALOG_MODE)
628 au8522_video_set(state);
629
630 return 0;
631}
632
633static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
634{
635 struct au8522_state *state = to_state(sd);
636
637 if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0)
638 return -EINVAL;
639
640 state->std = std;
641
642 if (state->operational_mode == AU8522_ANALOG_MODE)
643 au8522_video_set(state);
644
645 return 0;
646}
647
648static int au8522_s_audio_routing(struct v4l2_subdev *sd,
649 u32 input, u32 output, u32 config)
650{
651 struct au8522_state *state = to_state(sd);
652
653 state->aud_input = input;
654
655 if (state->operational_mode == AU8522_ANALOG_MODE)
656 set_audio_input(state);
657
658 return 0;
659}
660
661static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
662{
663 int val = 0;
664 struct au8522_state *state = to_state(sd);
665 u8 lock_status;
666
667
668 lock_status = au8522_readreg(state, 0x00);
669 if (lock_status == 0xa2)
670 vt->signal = 0xffff;
671 else
672 vt->signal = 0x00;
673
674 vt->capability |=
675 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
676 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
677
678 val = V4L2_TUNER_SUB_MONO;
679 vt->rxsubchans = val;
680 vt->audmode = V4L2_TUNER_MODE_STEREO;
681 return 0;
682}
683
684
685
686static const struct v4l2_subdev_core_ops au8522_core_ops = {
687 .log_status = v4l2_ctrl_subdev_log_status,
688#ifdef CONFIG_VIDEO_ADV_DEBUG
689 .g_register = au8522_g_register,
690 .s_register = au8522_s_register,
691#endif
692};
693
694static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
695 .g_tuner = au8522_g_tuner,
696};
697
698static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
699 .s_routing = au8522_s_audio_routing,
700};
701
702static const struct v4l2_subdev_video_ops au8522_video_ops = {
703 .s_routing = au8522_s_video_routing,
704 .s_stream = au8522_s_stream,
705 .s_std = au8522_s_std,
706};
707
708static const struct v4l2_subdev_ops au8522_ops = {
709 .core = &au8522_core_ops,
710 .tuner = &au8522_tuner_ops,
711 .audio = &au8522_audio_ops,
712 .video = &au8522_video_ops,
713};
714
715static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
716 .s_ctrl = au8522_s_ctrl,
717};
718
719
720
721static int au8522_probe(struct i2c_client *client,
722 const struct i2c_device_id *did)
723{
724 struct au8522_state *state;
725 struct v4l2_ctrl_handler *hdl;
726 struct v4l2_subdev *sd;
727 int instance;
728#ifdef CONFIG_MEDIA_CONTROLLER
729 int ret;
730#endif
731
732
733 if (!i2c_check_functionality(client->adapter,
734 I2C_FUNC_SMBUS_BYTE_DATA)) {
735 return -EIO;
736 }
737
738
739 instance = au8522_get_state(&state, client->adapter, client->addr);
740 switch (instance) {
741 case 0:
742 printk(KERN_ERR "au8522_decoder allocation failed\n");
743 return -EIO;
744 case 1:
745
746 printk(KERN_INFO "au8522_decoder creating new instance...\n");
747 break;
748 default:
749
750 printk(KERN_INFO "au8522_decoder attach existing instance.\n");
751 break;
752 }
753
754 state->config.demod_address = 0x8e >> 1;
755 state->i2c = client->adapter;
756
757 sd = &state->sd;
758 v4l2_i2c_subdev_init(sd, client, &au8522_ops);
759#if defined(CONFIG_MEDIA_CONTROLLER)
760
761 state->pads[DEMOD_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
762 state->pads[DEMOD_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
763 state->pads[DEMOD_PAD_VBI_OUT].flags = MEDIA_PAD_FL_SOURCE;
764 state->pads[DEMOD_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE;
765 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
766
767 ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads),
768 state->pads);
769 if (ret < 0) {
770 v4l_info(client, "failed to initialize media entity!\n");
771 return ret;
772 }
773#endif
774
775 hdl = &state->hdl;
776 v4l2_ctrl_handler_init(hdl, 4);
777 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
778 V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
779 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
780 V4L2_CID_CONTRAST, 0, 255, 1,
781 AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
782 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
783 V4L2_CID_SATURATION, 0, 255, 1, 128);
784 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
785 V4L2_CID_HUE, -32768, 32767, 1, 0);
786 sd->ctrl_handler = hdl;
787 if (hdl->error) {
788 int err = hdl->error;
789
790 v4l2_ctrl_handler_free(hdl);
791 au8522_release_state(state);
792 return err;
793 }
794
795 state->c = client;
796 state->std = V4L2_STD_NTSC_M;
797 state->vid_input = AU8522_COMPOSITE_CH1;
798 state->aud_input = AU8522_AUDIO_NONE;
799 state->id = 8522;
800 state->rev = 0;
801
802
803 au8522_writereg(state, 0x106, 1);
804
805 return 0;
806}
807
808static int au8522_remove(struct i2c_client *client)
809{
810 struct v4l2_subdev *sd = i2c_get_clientdata(client);
811 v4l2_device_unregister_subdev(sd);
812 v4l2_ctrl_handler_free(sd->ctrl_handler);
813 au8522_release_state(to_state(sd));
814 return 0;
815}
816
817static const struct i2c_device_id au8522_id[] = {
818 {"au8522", 0},
819 {}
820};
821
822MODULE_DEVICE_TABLE(i2c, au8522_id);
823
824static struct i2c_driver au8522_driver = {
825 .driver = {
826 .name = "au8522",
827 },
828 .probe = au8522_probe,
829 .remove = au8522_remove,
830 .id_table = au8522_id,
831};
832
833module_i2c_driver(au8522_driver);
834
