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113
114#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
115
116#define DRV_NAME "nmclan_cs"
117#define DRV_VERSION "0.16"
118
119
120
121
122
123
124#define MULTI_TX 0
125#define RESET_ON_TIMEOUT 1
126#define TX_INTERRUPTABLE 1
127#define RESET_XILINX 0
128
129
130
131
132
133#include <linux/module.h>
134#include <linux/kernel.h>
135#include <linux/ptrace.h>
136#include <linux/slab.h>
137#include <linux/string.h>
138#include <linux/timer.h>
139#include <linux/interrupt.h>
140#include <linux/in.h>
141#include <linux/delay.h>
142#include <linux/ethtool.h>
143#include <linux/netdevice.h>
144#include <linux/etherdevice.h>
145#include <linux/skbuff.h>
146#include <linux/if_arp.h>
147#include <linux/ioport.h>
148#include <linux/bitops.h>
149
150#include <pcmcia/cisreg.h>
151#include <pcmcia/cistpl.h>
152#include <pcmcia/ds.h>
153
154#include <linux/uaccess.h>
155#include <asm/io.h>
156
157
158
159
160
161#define MACE_LADRF_LEN 8
162
163
164
165#define MACE_MAX_IR_ITERATIONS 10
166#define MACE_MAX_RX_ITERATIONS 12
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182#define AM2150_MAX_TX_FRAMES 4
183#define AM2150_MAX_RX_FRAMES 12
184
185
186#define AM2150_RCV 0x00
187#define AM2150_XMT 0x04
188#define AM2150_XMT_SKIP 0x09
189#define AM2150_RCV_NEXT 0x0A
190#define AM2150_RCV_FRAME_COUNT 0x0B
191#define AM2150_MACE_BANK 0x0C
192#define AM2150_MACE_BASE 0x10
193
194
195#define MACE_RCVFIFO 0
196#define MACE_XMTFIFO 1
197#define MACE_XMTFC 2
198#define MACE_XMTFS 3
199#define MACE_XMTRC 4
200#define MACE_RCVFC 5
201#define MACE_RCVFS 6
202#define MACE_FIFOFC 7
203#define MACE_IR 8
204#define MACE_IMR 9
205#define MACE_PR 10
206#define MACE_BIUCC 11
207#define MACE_FIFOCC 12
208#define MACE_MACCC 13
209#define MACE_PLSCC 14
210#define MACE_PHYCC 15
211#define MACE_CHIPIDL 16
212#define MACE_CHIPIDH 17
213#define MACE_IAC 18
214
215#define MACE_LADRF 20
216#define MACE_PADR 21
217
218
219#define MACE_MPC 24
220
221#define MACE_RNTPC 26
222#define MACE_RCVCC 27
223
224#define MACE_UTR 29
225#define MACE_RTR1 30
226#define MACE_RTR2 31
227
228
229#define MACE_XMTRC_EXDEF 0x80
230#define MACE_XMTRC_XMTRC 0x0F
231
232#define MACE_XMTFS_XMTSV 0x80
233#define MACE_XMTFS_UFLO 0x40
234#define MACE_XMTFS_LCOL 0x20
235#define MACE_XMTFS_MORE 0x10
236#define MACE_XMTFS_ONE 0x08
237#define MACE_XMTFS_DEFER 0x04
238#define MACE_XMTFS_LCAR 0x02
239#define MACE_XMTFS_RTRY 0x01
240
241#define MACE_RCVFS_RCVSTS 0xF000
242#define MACE_RCVFS_OFLO 0x8000
243#define MACE_RCVFS_CLSN 0x4000
244#define MACE_RCVFS_FRAM 0x2000
245#define MACE_RCVFS_FCS 0x1000
246
247#define MACE_FIFOFC_RCVFC 0xF0
248#define MACE_FIFOFC_XMTFC 0x0F
249
250#define MACE_IR_JAB 0x80
251#define MACE_IR_BABL 0x40
252#define MACE_IR_CERR 0x20
253#define MACE_IR_RCVCCO 0x10
254#define MACE_IR_RNTPCO 0x08
255#define MACE_IR_MPCO 0x04
256#define MACE_IR_RCVINT 0x02
257#define MACE_IR_XMTINT 0x01
258
259#define MACE_MACCC_PROM 0x80
260#define MACE_MACCC_DXMT2PD 0x40
261#define MACE_MACCC_EMBA 0x20
262#define MACE_MACCC_RESERVED 0x10
263#define MACE_MACCC_DRCVPA 0x08
264#define MACE_MACCC_DRCVBC 0x04
265#define MACE_MACCC_ENXMT 0x02
266#define MACE_MACCC_ENRCV 0x01
267
268#define MACE_PHYCC_LNKFL 0x80
269#define MACE_PHYCC_DLNKTST 0x40
270#define MACE_PHYCC_REVPOL 0x20
271#define MACE_PHYCC_DAPC 0x10
272#define MACE_PHYCC_LRT 0x08
273#define MACE_PHYCC_ASEL 0x04
274#define MACE_PHYCC_RWAKE 0x02
275#define MACE_PHYCC_AWAKE 0x01
276
277#define MACE_IAC_ADDRCHG 0x80
278#define MACE_IAC_PHYADDR 0x04
279#define MACE_IAC_LOGADDR 0x02
280
281#define MACE_UTR_RTRE 0x80
282#define MACE_UTR_RTRD 0x40
283#define MACE_UTR_RPA 0x20
284#define MACE_UTR_FCOLL 0x10
285#define MACE_UTR_RCVFCSE 0x08
286#define MACE_UTR_LOOP_INCL_MENDEC 0x06
287#define MACE_UTR_LOOP_NO_MENDEC 0x04
288#define MACE_UTR_LOOP_EXTERNAL 0x02
289#define MACE_UTR_LOOP_NONE 0x00
290#define MACE_UTR_RESERVED 0x01
291
292
293#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
294
295#define MACE_IMR_DEFAULT \
296 (0xFF - \
297 ( \
298 MACE_IR_CERR | \
299 MACE_IR_RCVCCO | \
300 MACE_IR_RNTPCO | \
301 MACE_IR_MPCO | \
302 MACE_IR_RCVINT | \
303 MACE_IR_XMTINT \
304 ) \
305 )
306#undef MACE_IMR_DEFAULT
307#define MACE_IMR_DEFAULT 0x00
308
309#define TX_TIMEOUT ((400*HZ)/1000)
310
311
312
313
314
315typedef struct _mace_statistics {
316
317 int xmtsv;
318 int uflo;
319 int lcol;
320 int more;
321 int one;
322 int defer;
323 int lcar;
324 int rtry;
325
326
327 int exdef;
328 int xmtrc;
329
330
331 int oflo;
332 int clsn;
333 int fram;
334 int fcs;
335
336
337 int rfs_rntpc;
338
339
340 int rfs_rcvcc;
341
342
343 int jab;
344 int babl;
345 int cerr;
346 int rcvcco;
347 int rntpco;
348 int mpco;
349
350
351 int mpc;
352
353
354 int rntpc;
355
356
357 int rcvcc;
358} mace_statistics;
359
360typedef struct _mace_private {
361 struct pcmcia_device *p_dev;
362 struct net_device_stats linux_stats;
363 mace_statistics mace_stats;
364
365
366 int multicast_ladrf[MACE_LADRF_LEN];
367 int multicast_num_addrs;
368
369 char tx_free_frames;
370 char tx_irq_disabled;
371
372 spinlock_t bank_lock;
373} mace_private;
374
375
376
377
378
379static const char *if_names[]={
380 "Auto", "10baseT", "BNC",
381};
382
383
384
385
386
387
388
389MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
390MODULE_LICENSE("GPL");
391
392#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
393
394
395INT_MODULE_PARM(if_port, 0);
396
397
398
399
400
401
402static int nmclan_config(struct pcmcia_device *link);
403static void nmclan_release(struct pcmcia_device *link);
404
405static void nmclan_reset(struct net_device *dev);
406static int mace_config(struct net_device *dev, struct ifmap *map);
407static int mace_open(struct net_device *dev);
408static int mace_close(struct net_device *dev);
409static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
410 struct net_device *dev);
411static void mace_tx_timeout(struct net_device *dev);
412static irqreturn_t mace_interrupt(int irq, void *dev_id);
413static struct net_device_stats *mace_get_stats(struct net_device *dev);
414static int mace_rx(struct net_device *dev, unsigned char RxCnt);
415static void restore_multicast_list(struct net_device *dev);
416static void set_multicast_list(struct net_device *dev);
417static const struct ethtool_ops netdev_ethtool_ops;
418
419
420static void nmclan_detach(struct pcmcia_device *p_dev);
421
422static const struct net_device_ops mace_netdev_ops = {
423 .ndo_open = mace_open,
424 .ndo_stop = mace_close,
425 .ndo_start_xmit = mace_start_xmit,
426 .ndo_tx_timeout = mace_tx_timeout,
427 .ndo_set_config = mace_config,
428 .ndo_get_stats = mace_get_stats,
429 .ndo_set_rx_mode = set_multicast_list,
430 .ndo_set_mac_address = eth_mac_addr,
431 .ndo_validate_addr = eth_validate_addr,
432};
433
434static int nmclan_probe(struct pcmcia_device *link)
435{
436 mace_private *lp;
437 struct net_device *dev;
438
439 dev_dbg(&link->dev, "nmclan_attach()\n");
440
441
442 dev = alloc_etherdev(sizeof(mace_private));
443 if (!dev)
444 return -ENOMEM;
445 lp = netdev_priv(dev);
446 lp->p_dev = link;
447 link->priv = dev;
448
449 spin_lock_init(&lp->bank_lock);
450 link->resource[0]->end = 32;
451 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
452 link->config_flags |= CONF_ENABLE_IRQ;
453 link->config_index = 1;
454 link->config_regs = PRESENT_OPTION;
455
456 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
457
458 dev->netdev_ops = &mace_netdev_ops;
459 dev->ethtool_ops = &netdev_ethtool_ops;
460 dev->watchdog_timeo = TX_TIMEOUT;
461
462 return nmclan_config(link);
463}
464
465static void nmclan_detach(struct pcmcia_device *link)
466{
467 struct net_device *dev = link->priv;
468
469 dev_dbg(&link->dev, "nmclan_detach\n");
470
471 unregister_netdev(dev);
472
473 nmclan_release(link);
474
475 free_netdev(dev);
476}
477
478
479
480
481
482
483
484
485static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
486{
487 int data = 0xFF;
488 unsigned long flags;
489
490 switch (reg >> 4) {
491 case 0:
492 data = inb(ioaddr + AM2150_MACE_BASE + reg);
493 break;
494 case 1:
495 spin_lock_irqsave(&lp->bank_lock, flags);
496 MACEBANK(1);
497 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
498 MACEBANK(0);
499 spin_unlock_irqrestore(&lp->bank_lock, flags);
500 break;
501 }
502 return data & 0xFF;
503}
504
505
506
507
508
509
510
511
512static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
513 int data)
514{
515 unsigned long flags;
516
517 switch (reg >> 4) {
518 case 0:
519 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
520 break;
521 case 1:
522 spin_lock_irqsave(&lp->bank_lock, flags);
523 MACEBANK(1);
524 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
525 MACEBANK(0);
526 spin_unlock_irqrestore(&lp->bank_lock, flags);
527 break;
528 }
529}
530
531
532
533
534
535static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
536{
537 int i;
538 int ct = 0;
539
540
541 mace_write(lp, ioaddr, MACE_BIUCC, 1);
542 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
543 ;
544 if(++ct > 500)
545 {
546 pr_err("reset failed, card removed?\n");
547 return -1;
548 }
549 udelay(1);
550 }
551 mace_write(lp, ioaddr, MACE_BIUCC, 0);
552
553
554 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
555
556 mace_write(lp,ioaddr, MACE_RCVFC, 0);
557 mace_write(lp, ioaddr, MACE_IMR, 0xFF);
558
559
560
561
562
563
564
565
566
567
568
569
570
571 switch (if_port) {
572 case 1:
573 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
574 break;
575 case 2:
576 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
577 break;
578 default:
579 mace_write(lp, ioaddr, MACE_PHYCC, 4);
580
581
582
583 break;
584 }
585
586 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
587
588 ct = 0;
589 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
590 {
591 if(++ ct > 500)
592 {
593 pr_err("ADDRCHG timeout, card removed?\n");
594 return -1;
595 }
596 }
597
598 for (i = 0; i < ETH_ALEN; i++)
599 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
600
601
602
603
604 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
605 return 0;
606}
607
608static int nmclan_config(struct pcmcia_device *link)
609{
610 struct net_device *dev = link->priv;
611 mace_private *lp = netdev_priv(dev);
612 u8 *buf;
613 size_t len;
614 int i, ret;
615 unsigned int ioaddr;
616
617 dev_dbg(&link->dev, "nmclan_config\n");
618
619 link->io_lines = 5;
620 ret = pcmcia_request_io(link);
621 if (ret)
622 goto failed;
623 ret = pcmcia_request_irq(link, mace_interrupt);
624 if (ret)
625 goto failed;
626 ret = pcmcia_enable_device(link);
627 if (ret)
628 goto failed;
629
630 dev->irq = link->irq;
631 dev->base_addr = link->resource[0]->start;
632
633 ioaddr = dev->base_addr;
634
635
636 len = pcmcia_get_tuple(link, 0x80, &buf);
637 if (!buf || len < ETH_ALEN) {
638 kfree(buf);
639 goto failed;
640 }
641 memcpy(dev->dev_addr, buf, ETH_ALEN);
642 kfree(buf);
643
644
645 {
646 char sig[2];
647
648 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
649 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
650 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
651 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
652 sig[0], sig[1]);
653 } else {
654 pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
655 sig[0], sig[1]);
656 return -ENODEV;
657 }
658 }
659
660 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
661 goto failed;
662
663
664 if (if_port <= 2)
665 dev->if_port = if_port;
666 else
667 pr_notice("invalid if_port requested\n");
668
669 SET_NETDEV_DEV(dev, &link->dev);
670
671 i = register_netdev(dev);
672 if (i != 0) {
673 pr_notice("register_netdev() failed\n");
674 goto failed;
675 }
676
677 netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
678 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
679 return 0;
680
681failed:
682 nmclan_release(link);
683 return -ENODEV;
684}
685
686static void nmclan_release(struct pcmcia_device *link)
687{
688 dev_dbg(&link->dev, "nmclan_release\n");
689 pcmcia_disable_device(link);
690}
691
692static int nmclan_suspend(struct pcmcia_device *link)
693{
694 struct net_device *dev = link->priv;
695
696 if (link->open)
697 netif_device_detach(dev);
698
699 return 0;
700}
701
702static int nmclan_resume(struct pcmcia_device *link)
703{
704 struct net_device *dev = link->priv;
705
706 if (link->open) {
707 nmclan_reset(dev);
708 netif_device_attach(dev);
709 }
710
711 return 0;
712}
713
714
715
716
717
718
719static void nmclan_reset(struct net_device *dev)
720{
721 mace_private *lp = netdev_priv(dev);
722
723#if RESET_XILINX
724 struct pcmcia_device *link = &lp->link;
725 u8 OrigCorValue;
726
727
728 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
729
730
731 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
732 OrigCorValue);
733 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
734
735
736
737 pcmcia_write_config_byte(link, CISREG_COR,
738 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
739
740 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
741
742#endif
743
744
745 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
746
747
748 mace_init(lp, dev->base_addr, dev->dev_addr);
749 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
750
751
752 restore_multicast_list(dev);
753}
754
755
756
757
758
759
760
761static int mace_config(struct net_device *dev, struct ifmap *map)
762{
763 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
764 if (map->port <= 2) {
765 dev->if_port = map->port;
766 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
767 } else
768 return -EINVAL;
769 }
770 return 0;
771}
772
773
774
775
776
777static int mace_open(struct net_device *dev)
778{
779 unsigned int ioaddr = dev->base_addr;
780 mace_private *lp = netdev_priv(dev);
781 struct pcmcia_device *link = lp->p_dev;
782
783 if (!pcmcia_dev_present(link))
784 return -ENODEV;
785
786 link->open++;
787
788 MACEBANK(0);
789
790 netif_start_queue(dev);
791 nmclan_reset(dev);
792
793 return 0;
794}
795
796
797
798
799
800static int mace_close(struct net_device *dev)
801{
802 unsigned int ioaddr = dev->base_addr;
803 mace_private *lp = netdev_priv(dev);
804 struct pcmcia_device *link = lp->p_dev;
805
806 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
807
808
809 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
810
811 link->open--;
812 netif_stop_queue(dev);
813
814 return 0;
815}
816
817static void netdev_get_drvinfo(struct net_device *dev,
818 struct ethtool_drvinfo *info)
819{
820 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
821 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
822 snprintf(info->bus_info, sizeof(info->bus_info),
823 "PCMCIA 0x%lx", dev->base_addr);
824}
825
826static const struct ethtool_ops netdev_ethtool_ops = {
827 .get_drvinfo = netdev_get_drvinfo,
828};
829
830
831
832
833
834
835
836
837
838
839
840
841static void mace_tx_timeout(struct net_device *dev)
842{
843 mace_private *lp = netdev_priv(dev);
844 struct pcmcia_device *link = lp->p_dev;
845
846 netdev_notice(dev, "transmit timed out -- ");
847#if RESET_ON_TIMEOUT
848 pr_cont("resetting card\n");
849 pcmcia_reset_card(link->socket);
850#else
851 pr_cont("NOT resetting card\n");
852#endif
853 netif_trans_update(dev);
854 netif_wake_queue(dev);
855}
856
857static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
858 struct net_device *dev)
859{
860 mace_private *lp = netdev_priv(dev);
861 unsigned int ioaddr = dev->base_addr;
862
863 netif_stop_queue(dev);
864
865 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
866 dev->name, (long)skb->len);
867
868#if (!TX_INTERRUPTABLE)
869
870 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
871 ioaddr + AM2150_MACE_BASE + MACE_IMR);
872 lp->tx_irq_disabled=1;
873#endif
874
875 {
876
877
878
879
880
881
882 lp->linux_stats.tx_bytes += skb->len;
883 lp->tx_free_frames--;
884
885
886
887 outw(skb->len, ioaddr + AM2150_XMT);
888
889 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
890 if (skb->len & 1) {
891
892 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
893 }
894
895#if MULTI_TX
896 if (lp->tx_free_frames > 0)
897 netif_start_queue(dev);
898#endif
899 }
900
901#if (!TX_INTERRUPTABLE)
902
903 lp->tx_irq_disabled=0;
904 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
905#endif
906
907 dev_kfree_skb(skb);
908
909 return NETDEV_TX_OK;
910}
911
912
913
914
915
916static irqreturn_t mace_interrupt(int irq, void *dev_id)
917{
918 struct net_device *dev = (struct net_device *) dev_id;
919 mace_private *lp = netdev_priv(dev);
920 unsigned int ioaddr;
921 int status;
922 int IntrCnt = MACE_MAX_IR_ITERATIONS;
923
924 if (dev == NULL) {
925 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
926 irq);
927 return IRQ_NONE;
928 }
929
930 ioaddr = dev->base_addr;
931
932 if (lp->tx_irq_disabled) {
933 const char *msg;
934 if (lp->tx_irq_disabled)
935 msg = "Interrupt with tx_irq_disabled";
936 else
937 msg = "Re-entering the interrupt handler";
938 netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
939 msg,
940 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
941 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
942
943 return IRQ_NONE;
944 }
945
946 if (!netif_device_present(dev)) {
947 netdev_dbg(dev, "interrupt from dead card\n");
948 return IRQ_NONE;
949 }
950
951 do {
952
953 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
954 if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS)
955 return IRQ_NONE;
956
957 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
958
959 if (status & MACE_IR_RCVINT) {
960 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
961 }
962
963 if (status & MACE_IR_XMTINT) {
964 unsigned char fifofc;
965 unsigned char xmtrc;
966 unsigned char xmtfs;
967
968 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
969 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
970 lp->linux_stats.tx_errors++;
971 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
972 }
973
974
975 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
976 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
977 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
978
979 if (
980 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
981 MACE_XMTFS_XMTSV
982 ) {
983 lp->mace_stats.xmtsv++;
984
985 if (xmtfs & ~MACE_XMTFS_XMTSV) {
986 if (xmtfs & MACE_XMTFS_UFLO) {
987
988
989 lp->mace_stats.uflo++;
990 }
991 if (xmtfs & MACE_XMTFS_LCOL) {
992
993 lp->mace_stats.lcol++;
994 }
995 if (xmtfs & MACE_XMTFS_MORE) {
996
997 lp->mace_stats.more++;
998 }
999 if (xmtfs & MACE_XMTFS_ONE) {
1000
1001 lp->mace_stats.one++;
1002 }
1003 if (xmtfs & MACE_XMTFS_DEFER) {
1004
1005 lp->mace_stats.defer++;
1006 }
1007 if (xmtfs & MACE_XMTFS_LCAR) {
1008
1009 lp->mace_stats.lcar++;
1010 }
1011 if (xmtfs & MACE_XMTFS_RTRY) {
1012
1013 lp->mace_stats.rtry++;
1014 }
1015 }
1016
1017 }
1018
1019 lp->linux_stats.tx_packets++;
1020 lp->tx_free_frames++;
1021 netif_wake_queue(dev);
1022 }
1023
1024 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1025 if (status & MACE_IR_JAB) {
1026
1027 lp->mace_stats.jab++;
1028 }
1029 if (status & MACE_IR_BABL) {
1030
1031 lp->mace_stats.babl++;
1032 }
1033 if (status & MACE_IR_CERR) {
1034
1035
1036
1037 lp->mace_stats.cerr++;
1038 }
1039 if (status & MACE_IR_RCVCCO) {
1040
1041 lp->mace_stats.rcvcco++;
1042 }
1043 if (status & MACE_IR_RNTPCO) {
1044
1045 lp->mace_stats.rntpco++;
1046 }
1047 if (status & MACE_IR_MPCO) {
1048
1049 lp->mace_stats.mpco++;
1050 }
1051 }
1052
1053 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1054
1055 return IRQ_HANDLED;
1056}
1057
1058
1059
1060
1061
1062static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1063{
1064 mace_private *lp = netdev_priv(dev);
1065 unsigned int ioaddr = dev->base_addr;
1066 unsigned char rx_framecnt;
1067 unsigned short rx_status;
1068
1069 while (
1070 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1071 (rx_framecnt <= 12) &&
1072 (RxCnt--)
1073 ) {
1074 rx_status = inw(ioaddr + AM2150_RCV);
1075
1076 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1077 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1078
1079 if (rx_status & MACE_RCVFS_RCVSTS) {
1080 lp->linux_stats.rx_errors++;
1081 if (rx_status & MACE_RCVFS_OFLO) {
1082 lp->mace_stats.oflo++;
1083 }
1084 if (rx_status & MACE_RCVFS_CLSN) {
1085 lp->mace_stats.clsn++;
1086 }
1087 if (rx_status & MACE_RCVFS_FRAM) {
1088 lp->mace_stats.fram++;
1089 }
1090 if (rx_status & MACE_RCVFS_FCS) {
1091 lp->mace_stats.fcs++;
1092 }
1093 } else {
1094 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1095
1096 struct sk_buff *skb;
1097
1098 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1099
1100 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1101
1102
1103 pr_debug(" receiving packet size 0x%X rx_status"
1104 " 0x%X.\n", pkt_len, rx_status);
1105
1106 skb = netdev_alloc_skb(dev, pkt_len + 2);
1107
1108 if (skb != NULL) {
1109 skb_reserve(skb, 2);
1110 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1111 if (pkt_len & 1)
1112 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1113 skb->protocol = eth_type_trans(skb, dev);
1114
1115 netif_rx(skb);
1116
1117 lp->linux_stats.rx_packets++;
1118 lp->linux_stats.rx_bytes += pkt_len;
1119 outb(0xFF, ioaddr + AM2150_RCV_NEXT);
1120 continue;
1121 } else {
1122 pr_debug("%s: couldn't allocate a sk_buff of size"
1123 " %d.\n", dev->name, pkt_len);
1124 lp->linux_stats.rx_dropped++;
1125 }
1126 }
1127 outb(0xFF, ioaddr + AM2150_RCV_NEXT);
1128 }
1129
1130 return 0;
1131}
1132
1133
1134
1135
1136static void pr_linux_stats(struct net_device_stats *pstats)
1137{
1138 pr_debug("pr_linux_stats\n");
1139 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1140 (long)pstats->rx_packets, (long)pstats->tx_packets);
1141 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1142 (long)pstats->rx_errors, (long)pstats->tx_errors);
1143 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1144 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1145 pr_debug(" multicast=%-7ld collisions=%ld\n",
1146 (long)pstats->multicast, (long)pstats->collisions);
1147
1148 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1149 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1150 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1151 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1152 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1153 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1154
1155 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1156 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1157 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1158 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1159 pr_debug(" tx_window_errors=%ld\n",
1160 (long)pstats->tx_window_errors);
1161}
1162
1163
1164
1165
1166static void pr_mace_stats(mace_statistics *pstats)
1167{
1168 pr_debug("pr_mace_stats\n");
1169
1170 pr_debug(" xmtsv=%-7d uflo=%d\n",
1171 pstats->xmtsv, pstats->uflo);
1172 pr_debug(" lcol=%-7d more=%d\n",
1173 pstats->lcol, pstats->more);
1174 pr_debug(" one=%-7d defer=%d\n",
1175 pstats->one, pstats->defer);
1176 pr_debug(" lcar=%-7d rtry=%d\n",
1177 pstats->lcar, pstats->rtry);
1178
1179
1180 pr_debug(" exdef=%-7d xmtrc=%d\n",
1181 pstats->exdef, pstats->xmtrc);
1182
1183
1184 pr_debug(" oflo=%-7d clsn=%d\n",
1185 pstats->oflo, pstats->clsn);
1186 pr_debug(" fram=%-7d fcs=%d\n",
1187 pstats->fram, pstats->fcs);
1188
1189
1190
1191 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1192 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1193
1194
1195 pr_debug(" jab=%-7d babl=%d\n",
1196 pstats->jab, pstats->babl);
1197 pr_debug(" cerr=%-7d rcvcco=%d\n",
1198 pstats->cerr, pstats->rcvcco);
1199 pr_debug(" rntpco=%-7d mpco=%d\n",
1200 pstats->rntpco, pstats->mpco);
1201
1202
1203 pr_debug(" mpc=%d\n", pstats->mpc);
1204
1205
1206 pr_debug(" rntpc=%d\n", pstats->rntpc);
1207
1208
1209 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1210
1211}
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226static void update_stats(unsigned int ioaddr, struct net_device *dev)
1227{
1228 mace_private *lp = netdev_priv(dev);
1229
1230 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1231 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1232 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1233
1234
1235
1236
1237
1238
1239
1240 lp->linux_stats.collisions =
1241 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1242
1243
1244
1245
1246
1247
1248 lp->linux_stats.rx_length_errors =
1249 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1250
1251 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1252 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1253 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1254 lp->linux_stats.rx_missed_errors =
1255 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1256
1257
1258 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1259 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1260
1261 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1262 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1263
1264}
1265
1266
1267
1268
1269
1270static struct net_device_stats *mace_get_stats(struct net_device *dev)
1271{
1272 mace_private *lp = netdev_priv(dev);
1273
1274 update_stats(dev->base_addr, dev);
1275
1276 pr_debug("%s: updating the statistics.\n", dev->name);
1277 pr_linux_stats(&lp->linux_stats);
1278 pr_mace_stats(&lp->mace_stats);
1279
1280 return &lp->linux_stats;
1281}
1282
1283
1284
1285
1286
1287
1288#ifdef BROKEN_MULTICAST
1289
1290static void updateCRC(int *CRC, int bit)
1291{
1292 static const int poly[]={
1293 1,1,1,0, 1,1,0,1,
1294 1,0,1,1, 1,0,0,0,
1295 1,0,0,0, 0,0,1,1,
1296 0,0,1,0, 0,0,0,0
1297 };
1298
1299
1300 int j;
1301
1302
1303 for (j = 32; j > 0; j--)
1304 CRC[j] = CRC[j-1];
1305 CRC[0] = 0;
1306
1307
1308 if (bit ^ CRC[32])
1309 for (j = 0; j < 32; j++)
1310 CRC[j] ^= poly[j];
1311}
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322static void BuildLAF(int *ladrf, int *adr)
1323{
1324 int CRC[33]={1};
1325
1326 int i, byte;
1327 int hashcode;
1328
1329 CRC[32]=0;
1330
1331 for (byte = 0; byte < 6; byte++)
1332 for (i = 0; i < 8; i++)
1333 updateCRC(CRC, (adr[byte] >> i) & 1);
1334
1335 hashcode = 0;
1336 for (i = 0; i < 6; i++)
1337 hashcode = (hashcode << 1) + CRC[i];
1338
1339 byte = hashcode >> 3;
1340 ladrf[byte] |= (1 << (hashcode & 7));
1341
1342#ifdef PCMCIA_DEBUG
1343 if (0)
1344 printk(KERN_DEBUG " adr =%pM\n", adr);
1345 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1346 for (i = 0; i < 8; i++)
1347 pr_cont(" %02X", ladrf[i]);
1348 pr_cont("\n");
1349#endif
1350}
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361static void restore_multicast_list(struct net_device *dev)
1362{
1363 mace_private *lp = netdev_priv(dev);
1364 int num_addrs = lp->multicast_num_addrs;
1365 int *ladrf = lp->multicast_ladrf;
1366 unsigned int ioaddr = dev->base_addr;
1367 int i;
1368
1369 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1370 dev->name, num_addrs);
1371
1372 if (num_addrs > 0) {
1373
1374 pr_debug("Attempt to restore multicast list detected.\n");
1375
1376 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1377
1378 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1379 ;
1380
1381 for (i = 0; i < MACE_LADRF_LEN; i++)
1382 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1383
1384 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1385 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1386
1387 } else if (num_addrs < 0) {
1388
1389
1390 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1391 mace_write(lp, ioaddr, MACE_MACCC,
1392 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1393 );
1394
1395 } else {
1396
1397
1398 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1399 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1400
1401 }
1402}
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418static void set_multicast_list(struct net_device *dev)
1419{
1420 mace_private *lp = netdev_priv(dev);
1421 int adr[ETH_ALEN] = {0};
1422 struct netdev_hw_addr *ha;
1423
1424#ifdef PCMCIA_DEBUG
1425 {
1426 static int old;
1427 if (netdev_mc_count(dev) != old) {
1428 old = netdev_mc_count(dev);
1429 pr_debug("%s: setting Rx mode to %d addresses.\n",
1430 dev->name, old);
1431 }
1432 }
1433#endif
1434
1435
1436 lp->multicast_num_addrs = netdev_mc_count(dev);
1437
1438
1439 if (num_addrs > 0) {
1440
1441 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1442 netdev_for_each_mc_addr(ha, dev) {
1443 memcpy(adr, ha->addr, ETH_ALEN);
1444 BuildLAF(lp->multicast_ladrf, adr);
1445 }
1446 }
1447
1448 restore_multicast_list(dev);
1449
1450}
1451
1452#endif
1453
1454static void restore_multicast_list(struct net_device *dev)
1455{
1456 unsigned int ioaddr = dev->base_addr;
1457 mace_private *lp = netdev_priv(dev);
1458
1459 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1460 lp->multicast_num_addrs);
1461
1462 if (dev->flags & IFF_PROMISC) {
1463
1464 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1465 mace_write(lp, ioaddr, MACE_MACCC,
1466 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1467 );
1468 } else {
1469
1470 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1471 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1472 }
1473}
1474
1475static void set_multicast_list(struct net_device *dev)
1476{
1477 mace_private *lp = netdev_priv(dev);
1478
1479#ifdef PCMCIA_DEBUG
1480 {
1481 static int old;
1482 if (netdev_mc_count(dev) != old) {
1483 old = netdev_mc_count(dev);
1484 pr_debug("%s: setting Rx mode to %d addresses.\n",
1485 dev->name, old);
1486 }
1487 }
1488#endif
1489
1490 lp->multicast_num_addrs = netdev_mc_count(dev);
1491 restore_multicast_list(dev);
1492
1493}
1494
1495static const struct pcmcia_device_id nmclan_ids[] = {
1496 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1497 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1498 PCMCIA_DEVICE_NULL,
1499};
1500MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1501
1502static struct pcmcia_driver nmclan_cs_driver = {
1503 .owner = THIS_MODULE,
1504 .name = "nmclan_cs",
1505 .probe = nmclan_probe,
1506 .remove = nmclan_detach,
1507 .id_table = nmclan_ids,
1508 .suspend = nmclan_suspend,
1509 .resume = nmclan_resume,
1510};
1511module_pcmcia_driver(nmclan_cs_driver);
1512