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9#ifndef NICVF_QUEUES_H
10#define NICVF_QUEUES_H
11
12#include <linux/netdevice.h>
13#include "q_struct.h"
14
15#define MAX_QUEUE_SET 128
16#define MAX_RCV_QUEUES_PER_QS 8
17#define MAX_RCV_BUF_DESC_RINGS_PER_QS 2
18#define MAX_SND_QUEUES_PER_QS 8
19#define MAX_CMP_QUEUES_PER_QS 8
20
21
22#define NICVF_INTR_ID_CQ 0
23#define NICVF_INTR_ID_SQ 8
24#define NICVF_INTR_ID_RBDR 16
25#define NICVF_INTR_ID_MISC 18
26#define NICVF_INTR_ID_QS_ERR 19
27
28#define for_each_cq_irq(irq) \
29 for (irq = NICVF_INTR_ID_CQ; irq < NICVF_INTR_ID_SQ; irq++)
30#define for_each_sq_irq(irq) \
31 for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_RBDR; irq++)
32#define for_each_rbdr_irq(irq) \
33 for (irq = NICVF_INTR_ID_RBDR; irq < NICVF_INTR_ID_MISC; irq++)
34
35#define RBDR_SIZE0 0ULL
36#define RBDR_SIZE1 1ULL
37#define RBDR_SIZE2 2ULL
38#define RBDR_SIZE3 3ULL
39#define RBDR_SIZE4 4ULL
40#define RBDR_SIZE5 5ULL
41#define RBDR_SIZE6 6ULL
42
43#define SND_QUEUE_SIZE0 0ULL
44#define SND_QUEUE_SIZE1 1ULL
45#define SND_QUEUE_SIZE2 2ULL
46#define SND_QUEUE_SIZE3 3ULL
47#define SND_QUEUE_SIZE4 4ULL
48#define SND_QUEUE_SIZE5 5ULL
49#define SND_QUEUE_SIZE6 6ULL
50
51#define CMP_QUEUE_SIZE0 0ULL
52#define CMP_QUEUE_SIZE1 1ULL
53#define CMP_QUEUE_SIZE2 2ULL
54#define CMP_QUEUE_SIZE3 3ULL
55#define CMP_QUEUE_SIZE4 4ULL
56#define CMP_QUEUE_SIZE5 5ULL
57#define CMP_QUEUE_SIZE6 6ULL
58
59
60#define DEFAULT_RBDR_CNT 1
61
62#define SND_QSIZE SND_QUEUE_SIZE0
63#define SND_QUEUE_LEN (1ULL << (SND_QSIZE + 10))
64#define MIN_SND_QUEUE_LEN (1ULL << (SND_QUEUE_SIZE0 + 10))
65#define MAX_SND_QUEUE_LEN (1ULL << (SND_QUEUE_SIZE6 + 10))
66#define SND_QUEUE_THRESH 2ULL
67#define MIN_SQ_DESC_PER_PKT_XMIT 2
68
69#define MAX_CQE_PER_PKT_XMIT 1
70
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72
73
74#define CMP_QSIZE CMP_QUEUE_SIZE0
75#define CMP_QUEUE_LEN (1ULL << (CMP_QSIZE + 10))
76#define MIN_CMP_QUEUE_LEN (1ULL << (CMP_QUEUE_SIZE0 + 10))
77#define MAX_CMP_QUEUE_LEN (1ULL << (CMP_QUEUE_SIZE6 + 10))
78#define CMP_QUEUE_CQE_THRESH (NAPI_POLL_WEIGHT / 2)
79#define CMP_QUEUE_TIMER_THRESH 80
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83
84#define CMP_QUEUE_PIPELINE_RSVD 544
85
86#define RBDR_SIZE RBDR_SIZE0
87#define RCV_BUF_COUNT (1ULL << (RBDR_SIZE + 13))
88#define MAX_RCV_BUF_COUNT (1ULL << (RBDR_SIZE6 + 13))
89#define RBDR_THRESH (RCV_BUF_COUNT / 2)
90#define DMA_BUFFER_LEN 1536
91#define RCV_FRAG_LEN (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \
92 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
93
94#define MAX_CQES_FOR_TX ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \
95 MAX_CQE_PER_PKT_XMIT)
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103
104#define RQ_PASS_CQ_LVL 192ULL
105#define RQ_DROP_CQ_LVL 184ULL
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113
114#define RQ_PASS_RBDR_LVL 8ULL
115#define RQ_DROP_RBDR_LVL 0ULL
116
117
118#define SND_QUEUE_DESC_SIZE 16
119#define CMP_QUEUE_DESC_SIZE 512
120
121
122#define NICVF_RCV_BUF_ALIGN 7
123#define NICVF_RCV_BUF_ALIGN_BYTES (1ULL << NICVF_RCV_BUF_ALIGN)
124#define NICVF_CQ_BASE_ALIGN_BYTES 512
125#define NICVF_SQ_BASE_ALIGN_BYTES 128
126
127#define NICVF_ALIGNED_ADDR(ADDR, ALIGN_BYTES) ALIGN(ADDR, ALIGN_BYTES)
128
129
130#define NICVF_SQ_EN BIT_ULL(19)
131
132
133#define NICVF_CQ_RESET BIT_ULL(41)
134#define NICVF_SQ_RESET BIT_ULL(17)
135#define NICVF_RBDR_RESET BIT_ULL(43)
136
137enum CQ_RX_ERRLVL_E {
138 CQ_ERRLVL_MAC,
139 CQ_ERRLVL_L2,
140 CQ_ERRLVL_L3,
141 CQ_ERRLVL_L4,
142};
143
144enum CQ_RX_ERROP_E {
145 CQ_RX_ERROP_RE_NONE = 0x0,
146 CQ_RX_ERROP_RE_PARTIAL = 0x1,
147 CQ_RX_ERROP_RE_JABBER = 0x2,
148 CQ_RX_ERROP_RE_FCS = 0x7,
149 CQ_RX_ERROP_RE_TERMINATE = 0x9,
150 CQ_RX_ERROP_RE_RX_CTL = 0xb,
151 CQ_RX_ERROP_PREL2_ERR = 0x1f,
152 CQ_RX_ERROP_L2_FRAGMENT = 0x20,
153 CQ_RX_ERROP_L2_OVERRUN = 0x21,
154 CQ_RX_ERROP_L2_PFCS = 0x22,
155 CQ_RX_ERROP_L2_PUNY = 0x23,
156 CQ_RX_ERROP_L2_MAL = 0x24,
157 CQ_RX_ERROP_L2_OVERSIZE = 0x25,
158 CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
159 CQ_RX_ERROP_L2_LENMISM = 0x27,
160 CQ_RX_ERROP_L2_PCLP = 0x28,
161 CQ_RX_ERROP_IP_NOT = 0x41,
162 CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
163 CQ_RX_ERROP_IP_MAL = 0x43,
164 CQ_RX_ERROP_IP_MALD = 0x44,
165 CQ_RX_ERROP_IP_HOP = 0x45,
166 CQ_RX_ERROP_L3_ICRC = 0x46,
167 CQ_RX_ERROP_L3_PCLP = 0x47,
168 CQ_RX_ERROP_L4_MAL = 0x61,
169 CQ_RX_ERROP_L4_CHK = 0x62,
170 CQ_RX_ERROP_UDP_LEN = 0x63,
171 CQ_RX_ERROP_L4_PORT = 0x64,
172 CQ_RX_ERROP_TCP_FLAG = 0x65,
173 CQ_RX_ERROP_TCP_OFFSET = 0x66,
174 CQ_RX_ERROP_L4_PCLP = 0x67,
175 CQ_RX_ERROP_RBDR_TRUNC = 0x70,
176};
177
178enum CQ_TX_ERROP_E {
179 CQ_TX_ERROP_GOOD = 0x0,
180 CQ_TX_ERROP_DESC_FAULT = 0x10,
181 CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
182 CQ_TX_ERROP_SUBDC_ERR = 0x12,
183 CQ_TX_ERROP_MAX_SIZE_VIOL = 0x13,
184 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
185 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
186 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
187 CQ_TX_ERROP_LOCK_VIOL = 0x83,
188 CQ_TX_ERROP_DATA_FAULT = 0x84,
189 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
190 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
191 CQ_TX_ERROP_MEM_FAULT = 0x87,
192 CQ_TX_ERROP_CK_OVERLAP = 0x88,
193 CQ_TX_ERROP_CK_OFLOW = 0x89,
194 CQ_TX_ERROP_ENUM_LAST = 0x8a,
195};
196
197enum RQ_SQ_STATS {
198 RQ_SQ_STATS_OCTS,
199 RQ_SQ_STATS_PKTS,
200};
201
202struct rx_tx_queue_stats {
203 u64 bytes;
204 u64 pkts;
205} ____cacheline_aligned_in_smp;
206
207struct q_desc_mem {
208 dma_addr_t dma;
209 u64 size;
210 u16 q_len;
211 dma_addr_t phys_base;
212 void *base;
213 void *unalign_base;
214};
215
216struct rbdr {
217 bool enable;
218 u32 dma_size;
219 u32 frag_len;
220 u32 thresh;
221 void *desc;
222 u32 head;
223 u32 tail;
224 struct q_desc_mem dmem;
225} ____cacheline_aligned_in_smp;
226
227struct rcv_queue {
228 bool enable;
229 struct rbdr *rbdr_start;
230 struct rbdr *rbdr_cont;
231 bool en_tcp_reassembly;
232 u8 cq_qs;
233 u8 cq_idx;
234 u8 cont_rbdr_qs;
235 u8 cont_qs_rbdr_idx;
236 u8 start_rbdr_qs;
237 u8 start_qs_rbdr_idx;
238 u8 caching;
239 struct rx_tx_queue_stats stats;
240} ____cacheline_aligned_in_smp;
241
242struct cmp_queue {
243 bool enable;
244 u16 thresh;
245 spinlock_t lock;
246 void *desc;
247 struct q_desc_mem dmem;
248 int irq;
249} ____cacheline_aligned_in_smp;
250
251struct snd_queue {
252 bool enable;
253 u8 cq_qs;
254 u8 cq_idx;
255 u16 thresh;
256 atomic_t free_cnt;
257 u32 head;
258 u32 tail;
259 u64 *skbuff;
260 void *desc;
261
262#define TSO_HEADER_SIZE 128
263
264 char *tso_hdrs;
265 dma_addr_t tso_hdrs_phys;
266
267 cpumask_t affinity_mask;
268 struct q_desc_mem dmem;
269 struct rx_tx_queue_stats stats;
270} ____cacheline_aligned_in_smp;
271
272struct queue_set {
273 bool enable;
274 bool be_en;
275 u8 vnic_id;
276 u8 rq_cnt;
277 u8 cq_cnt;
278 u64 cq_len;
279 u8 sq_cnt;
280 u64 sq_len;
281 u8 rbdr_cnt;
282 u64 rbdr_len;
283 struct rcv_queue rq[MAX_RCV_QUEUES_PER_QS];
284 struct cmp_queue cq[MAX_CMP_QUEUES_PER_QS];
285 struct snd_queue sq[MAX_SND_QUEUES_PER_QS];
286 struct rbdr rbdr[MAX_RCV_BUF_DESC_RINGS_PER_QS];
287} ____cacheline_aligned_in_smp;
288
289#define GET_RBDR_DESC(RING, idx)\
290 (&(((struct rbdr_entry_t *)((RING)->desc))[idx]))
291#define GET_SQ_DESC(RING, idx)\
292 (&(((struct sq_hdr_subdesc *)((RING)->desc))[idx]))
293#define GET_CQ_DESC(RING, idx)\
294 (&(((union cq_desc_t *)((RING)->desc))[idx]))
295
296
297#define CQ_WR_FULL BIT(26)
298#define CQ_WR_DISABLE BIT(25)
299#define CQ_WR_FAULT BIT(24)
300#define CQ_CQE_COUNT (0xFFFF << 0)
301
302#define CQ_ERR_MASK (CQ_WR_FULL | CQ_WR_DISABLE | CQ_WR_FAULT)
303
304void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq,
305 int hdr_sqe, u8 subdesc_cnt);
306void nicvf_config_vlan_stripping(struct nicvf *nic,
307 netdev_features_t features);
308int nicvf_set_qset_resources(struct nicvf *nic);
309int nicvf_config_data_transfer(struct nicvf *nic, bool enable);
310void nicvf_qset_config(struct nicvf *nic, bool enable);
311void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
312 int qidx, bool enable);
313
314void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx);
315void nicvf_sq_disable(struct nicvf *nic, int qidx);
316void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt);
317void nicvf_sq_free_used_descs(struct net_device *netdev,
318 struct snd_queue *sq, int qidx);
319int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq,
320 struct sk_buff *skb, u8 sq_num);
321
322struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic, struct cqe_rx_t *cqe_rx);
323void nicvf_rbdr_task(unsigned long data);
324void nicvf_rbdr_work(struct work_struct *work);
325
326void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx);
327void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx);
328void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx);
329int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx);
330
331
332void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val);
333u64 nicvf_reg_read(struct nicvf *nic, u64 offset);
334void nicvf_qset_reg_write(struct nicvf *nic, u64 offset, u64 val);
335u64 nicvf_qset_reg_read(struct nicvf *nic, u64 offset);
336void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
337 u64 qidx, u64 val);
338u64 nicvf_queue_reg_read(struct nicvf *nic,
339 u64 offset, u64 qidx);
340
341
342void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx);
343void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx);
344int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx);
345int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx);
346#endif
347