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29#include "ixgbe.h"
30#include "ixgbe_type.h"
31#include "ixgbe_dcb.h"
32#include "ixgbe_dcb_82599.h"
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43
44s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
45 u16 *refill,
46 u16 *max,
47 u8 *bwg_id,
48 u8 *prio_type,
49 u8 *prio_tc)
50{
51 u32 reg = 0;
52 u32 credit_refill = 0;
53 u32 credit_max = 0;
54 u8 i = 0;
55
56
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58
59
60 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
61 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
62
63
64 reg = 0;
65 for (i = 0; i < MAX_USER_PRIORITY; i++)
66 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
67 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
68
69
70 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
71 credit_refill = refill[i];
72 credit_max = max[i];
73 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
74
75 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
76
77 if (prio_type[i] == prio_link)
78 reg |= IXGBE_RTRPT4C_LSP;
79
80 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
81 }
82
83
84
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86
87 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
88 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
89
90 return 0;
91}
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102
103s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
104 u16 *refill,
105 u16 *max,
106 u8 *bwg_id,
107 u8 *prio_type)
108{
109 u32 reg, max_credits;
110 u8 i;
111
112
113 for (i = 0; i < 128; i++) {
114 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
115 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
116 }
117
118
119 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
120 max_credits = max[i];
121 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
122 reg |= refill[i];
123 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
124
125 if (prio_type[i] == prio_group)
126 reg |= IXGBE_RTTDT2C_GSP;
127
128 if (prio_type[i] == prio_link)
129 reg |= IXGBE_RTTDT2C_LSP;
130
131 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
132 }
133
134
135
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137
138 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
139 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
140
141 return 0;
142}
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154s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
155 u16 *refill,
156 u16 *max,
157 u8 *bwg_id,
158 u8 *prio_type,
159 u8 *prio_tc)
160{
161 u32 reg;
162 u8 i;
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167
168 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
169 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
170 IXGBE_RTTPCS_ARBDIS;
171 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
172
173
174 reg = 0;
175 for (i = 0; i < MAX_USER_PRIORITY; i++)
176 reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
177 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
178
179
180 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
181 reg = refill[i];
182 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
183 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
184
185 if (prio_type[i] == prio_group)
186 reg |= IXGBE_RTTPT2C_GSP;
187
188 if (prio_type[i] == prio_link)
189 reg |= IXGBE_RTTPT2C_LSP;
190
191 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
192 }
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197
198 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
199 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
200 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
201
202 return 0;
203}
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212
213s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
214{
215 u32 i, j, fcrtl, reg;
216 u8 max_tc = 0;
217
218
219 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
220
221
222 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
223 reg |= IXGBE_MFLCN_DPF;
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229
230 reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
231
232 if (hw->mac.type >= ixgbe_mac_X540)
233 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
234
235 if (pfc_en)
236 reg |= IXGBE_MFLCN_RPFCE;
237
238 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
239
240 for (i = 0; i < MAX_USER_PRIORITY; i++) {
241 if (prio_tc[i] > max_tc)
242 max_tc = prio_tc[i];
243 }
244
245
246
247 for (i = 0; i <= max_tc; i++) {
248 int enabled = 0;
249
250 for (j = 0; j < MAX_USER_PRIORITY; j++) {
251 if ((prio_tc[j] == i) && (pfc_en & BIT(j))) {
252 enabled = 1;
253 break;
254 }
255 }
256
257 if (enabled) {
258 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
259 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
260 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
261 } else {
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268 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
269 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
270 }
271
272 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
273 }
274
275 for (; i < MAX_TRAFFIC_CLASS; i++) {
276 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
277 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
278 }
279
280
281 reg = hw->fc.pause_time * 0x00010001;
282 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
283 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
284
285
286 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
287
288 return 0;
289}
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298static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
299{
300 u32 reg = 0;
301 u8 i = 0;
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309 for (i = 0; i < 32; i++) {
310 reg = 0x01010101 * (i / 4);
311 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
312 }
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321 for (i = 0; i < 32; i++) {
322 if (i < 8)
323 reg = 0x00000000;
324 else if (i < 16)
325 reg = 0x01010101;
326 else if (i < 20)
327 reg = 0x02020202;
328 else if (i < 24)
329 reg = 0x03030303;
330 else if (i < 26)
331 reg = 0x04040404;
332 else if (i < 28)
333 reg = 0x05050505;
334 else if (i < 30)
335 reg = 0x06060606;
336 else
337 reg = 0x07070707;
338 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
339 }
340
341 return 0;
342}
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355s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
356 u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
357{
358 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
359 prio_type, prio_tc);
360 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
361 bwg_id, prio_type);
362 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
363 bwg_id, prio_type, prio_tc);
364 ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
365 ixgbe_dcb_config_tc_stats_82599(hw);
366
367 return 0;
368}
369
370