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13#include <linux/kernel.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/platform_device.h>
17#include <linux/skbuff.h>
18#include <linux/inetdevice.h>
19#include <linux/mbus.h>
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/cpumask.h>
23#include <linux/of.h>
24#include <linux/of_irq.h>
25#include <linux/of_mdio.h>
26#include <linux/of_net.h>
27#include <linux/of_address.h>
28#include <linux/phy.h>
29#include <linux/clk.h>
30#include <linux/hrtimer.h>
31#include <linux/ktime.h>
32#include <uapi/linux/ppp_defs.h>
33#include <net/ip.h>
34#include <net/ipv6.h>
35
36
37#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
38#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
39#define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
40#define MVPP2_RX_FIFO_INIT_REG 0x64
41
42
43#define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
44#define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
45#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
46#define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
47#define MVPP2_POOL_BUF_SIZE_OFFSET 5
48#define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
49#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
50#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
51#define MVPP2_RXQ_POOL_SHORT_OFFS 20
52#define MVPP2_RXQ_POOL_SHORT_MASK 0x700000
53#define MVPP2_RXQ_POOL_LONG_OFFS 24
54#define MVPP2_RXQ_POOL_LONG_MASK 0x7000000
55#define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
56#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
57#define MVPP2_RXQ_DISABLE_MASK BIT(31)
58
59
60#define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
61#define MVPP2_PRS_PORT_LU_MAX 0xf
62#define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
63#define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
64#define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
65#define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
66#define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
67#define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
68#define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
69#define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
70#define MVPP2_PRS_TCAM_IDX_REG 0x1100
71#define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
72#define MVPP2_PRS_TCAM_INV_MASK BIT(31)
73#define MVPP2_PRS_SRAM_IDX_REG 0x1200
74#define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
75#define MVPP2_PRS_TCAM_CTRL_REG 0x1230
76#define MVPP2_PRS_TCAM_EN_MASK BIT(0)
77
78
79#define MVPP2_CLS_MODE_REG 0x1800
80#define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
81#define MVPP2_CLS_PORT_WAY_REG 0x1810
82#define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
83#define MVPP2_CLS_LKP_INDEX_REG 0x1814
84#define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
85#define MVPP2_CLS_LKP_TBL_REG 0x1818
86#define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
87#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
88#define MVPP2_CLS_FLOW_INDEX_REG 0x1820
89#define MVPP2_CLS_FLOW_TBL0_REG 0x1824
90#define MVPP2_CLS_FLOW_TBL1_REG 0x1828
91#define MVPP2_CLS_FLOW_TBL2_REG 0x182c
92#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
93#define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
94#define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
95#define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
96#define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
97#define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
98
99
100#define MVPP2_RXQ_NUM_REG 0x2040
101#define MVPP2_RXQ_DESC_ADDR_REG 0x2044
102#define MVPP2_RXQ_DESC_SIZE_REG 0x2048
103#define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
104#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
105#define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
106#define MVPP2_RXQ_NUM_NEW_OFFSET 16
107#define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
108#define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
109#define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
110#define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
111#define MVPP2_RXQ_THRESH_REG 0x204c
112#define MVPP2_OCCUPIED_THRESH_OFFSET 0
113#define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
114#define MVPP2_RXQ_INDEX_REG 0x2050
115#define MVPP2_TXQ_NUM_REG 0x2080
116#define MVPP2_TXQ_DESC_ADDR_REG 0x2084
117#define MVPP2_TXQ_DESC_SIZE_REG 0x2088
118#define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
119#define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
120#define MVPP2_TXQ_THRESH_REG 0x2094
121#define MVPP2_TRANSMITTED_THRESH_OFFSET 16
122#define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
123#define MVPP2_TXQ_INDEX_REG 0x2098
124#define MVPP2_TXQ_PREF_BUF_REG 0x209c
125#define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
126#define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
127#define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
128#define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
129#define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
130#define MVPP2_TXQ_PENDING_REG 0x20a0
131#define MVPP2_TXQ_PENDING_MASK 0x3fff
132#define MVPP2_TXQ_INT_STATUS_REG 0x20a4
133#define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
134#define MVPP2_TRANSMITTED_COUNT_OFFSET 16
135#define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
136#define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
137#define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
138#define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
139#define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
140#define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
141#define MVPP2_TXQ_RSVD_CLR_OFFSET 16
142#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
143#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
144#define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
145#define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
146#define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
147#define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
148
149
150#define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
151#define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
152#define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
153#define MVPP2_BASE_ADDR_ENABLE 0x4060
154
155
156#define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
157#define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
158#define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
159#define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
160#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
161#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
162#define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
163#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
164#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
165#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
166#define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
167#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
168#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
169#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
170#define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
171#define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
172#define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
173#define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
174#define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
175#define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
176#define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
177
178
179#define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
180#define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
181#define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
182#define MVPP2_BM_POOL_SIZE_MASK 0xfff0
183#define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
184#define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
185#define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
186#define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
187#define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
188#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
189#define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
190#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
191#define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
192#define MVPP2_BM_START_MASK BIT(0)
193#define MVPP2_BM_STOP_MASK BIT(1)
194#define MVPP2_BM_STATE_MASK BIT(4)
195#define MVPP2_BM_LOW_THRESH_OFFS 8
196#define MVPP2_BM_LOW_THRESH_MASK 0x7f00
197#define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
198 MVPP2_BM_LOW_THRESH_OFFS)
199#define MVPP2_BM_HIGH_THRESH_OFFS 16
200#define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
201#define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
202 MVPP2_BM_HIGH_THRESH_OFFS)
203#define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
204#define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
205#define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
206#define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
207#define MVPP2_BM_BPPE_FULL_MASK BIT(3)
208#define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
209#define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
210#define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
211#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
212#define MVPP2_BM_VIRT_ALLOC_REG 0x6440
213#define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
214#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
215#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
216#define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
217#define MVPP2_BM_VIRT_RLS_REG 0x64c0
218#define MVPP2_BM_MC_RLS_REG 0x64c4
219#define MVPP2_BM_MC_ID_MASK 0xfff
220#define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
221
222
223#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
224#define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
225#define MVPP2_TXP_SCHED_ENQ_MASK 0xff
226#define MVPP2_TXP_SCHED_DISQ_OFFSET 8
227#define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
228#define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
229#define MVPP2_TXP_SCHED_MTU_REG 0x801c
230#define MVPP2_TXP_MTU_MAX 0x7FFFF
231#define MVPP2_TXP_SCHED_REFILL_REG 0x8020
232#define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
233#define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
234#define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
235#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
236#define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
237#define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
238#define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
239#define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
240#define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
241#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
242#define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
243#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
244#define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
245
246
247#define MVPP2_TX_SNOOP_REG 0x8800
248#define MVPP2_TX_PORT_FLUSH_REG 0x8810
249#define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
250
251
252#define MVPP2_SRC_ADDR_MIDDLE 0x24
253#define MVPP2_SRC_ADDR_HIGH 0x28
254#define MVPP2_PHY_AN_CFG0_REG 0x34
255#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
256#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
257#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
258
259
260#define MVPP2_GMAC_CTRL_0_REG 0x0
261#define MVPP2_GMAC_PORT_EN_MASK BIT(0)
262#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
263#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
264#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
265#define MVPP2_GMAC_CTRL_1_REG 0x4
266#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
267#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
268#define MVPP2_GMAC_PCS_LB_EN_BIT 6
269#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
270#define MVPP2_GMAC_SA_LOW_OFFS 7
271#define MVPP2_GMAC_CTRL_2_REG 0x8
272#define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
273#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
274#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
275#define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
276#define MVPP2_GMAC_AUTONEG_CONFIG 0xc
277#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
278#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
279#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
280#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
281#define MVPP2_GMAC_AN_SPEED_EN BIT(7)
282#define MVPP2_GMAC_FC_ADV_EN BIT(9)
283#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
284#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
285#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
286#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
287#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
288#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
289 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
290
291#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
292
293
294#define MVPP2_QUEUE_NEXT_DESC(q, index) \
295 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
296
297
298
299
300#define MVPP2_TXDONE_COAL_PKTS_THRESH 15
301#define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
302#define MVPP2_RX_COAL_PKTS 32
303#define MVPP2_RX_COAL_USEC 100
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311
312
313#define MVPP2_MH_SIZE 2
314#define MVPP2_ETH_TYPE_LEN 2
315#define MVPP2_PPPOE_HDR_SIZE 8
316#define MVPP2_VLAN_TAG_LEN 4
317
318
319#define MVPP2_IP_LBDT_TYPE 0xfffa
320
321#define MVPP2_TX_CSUM_MAX_SIZE 9800
322
323
324#define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
325#define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
326
327#define MVPP2_TX_MTU_MAX 0x7ffff
328
329
330#define MVPP2_MAX_TCONT 16
331
332
333#define MVPP2_MAX_PORTS 4
334
335
336#define MVPP2_MAX_TXQ 8
337
338
339#define MVPP2_MAX_RXQ 8
340
341
342#define MVPP2_DEFAULT_RXQ 4
343
344
345#define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
346
347
348#define MVPP2_MAX_RXD 128
349
350
351#define MVPP2_MAX_TXD 1024
352
353
354#define MVPP2_CPU_DESC_CHUNK 64
355
356
357#define MVPP2_AGGR_TXQ_SIZE 256
358
359
360#define MVPP2_DESC_ALIGNED_SIZE 32
361
362
363#define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
364
365
366#define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
367#define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
368#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
369
370
371#define MVPP2_SKB_SHINFO_SIZE \
372 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
373
374#define MVPP2_RX_PKT_SIZE(mtu) \
375 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
376 ETH_HLEN + ETH_FCS_LEN, cache_line_size())
377
378#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
379#define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
380#define MVPP2_RX_MAX_PKT_SIZE(total_size) \
381 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
382
383#define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
384
385
386#define MVPP2_MAX_L3_ADDR_SIZE 16
387
388
389#define MVPP2_F_LOOPBACK BIT(0)
390
391
392enum mvpp2_tag_type {
393 MVPP2_TAG_TYPE_NONE = 0,
394 MVPP2_TAG_TYPE_MH = 1,
395 MVPP2_TAG_TYPE_DSA = 2,
396 MVPP2_TAG_TYPE_EDSA = 3,
397 MVPP2_TAG_TYPE_VLAN = 4,
398 MVPP2_TAG_TYPE_LAST = 5
399};
400
401
402#define MVPP2_PRS_TCAM_SRAM_SIZE 256
403#define MVPP2_PRS_TCAM_WORDS 6
404#define MVPP2_PRS_SRAM_WORDS 4
405#define MVPP2_PRS_FLOW_ID_SIZE 64
406#define MVPP2_PRS_FLOW_ID_MASK 0x3f
407#define MVPP2_PRS_TCAM_ENTRY_INVALID 1
408#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
409#define MVPP2_PRS_IPV4_HEAD 0x40
410#define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
411#define MVPP2_PRS_IPV4_MC 0xe0
412#define MVPP2_PRS_IPV4_MC_MASK 0xf0
413#define MVPP2_PRS_IPV4_BC_MASK 0xff
414#define MVPP2_PRS_IPV4_IHL 0x5
415#define MVPP2_PRS_IPV4_IHL_MASK 0xf
416#define MVPP2_PRS_IPV6_MC 0xff
417#define MVPP2_PRS_IPV6_MC_MASK 0xff
418#define MVPP2_PRS_IPV6_HOP_MASK 0xff
419#define MVPP2_PRS_TCAM_PROTO_MASK 0xff
420#define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
421#define MVPP2_PRS_DBL_VLANS_MAX 100
422
423
424
425
426
427
428
429
430#define MVPP2_PRS_AI_BITS 8
431#define MVPP2_PRS_PORT_MASK 0xff
432#define MVPP2_PRS_LU_MASK 0xf
433#define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
434 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
435#define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
436 (((offs) * 2) - ((offs) % 2) + 2)
437#define MVPP2_PRS_TCAM_AI_BYTE 16
438#define MVPP2_PRS_TCAM_PORT_BYTE 17
439#define MVPP2_PRS_TCAM_LU_BYTE 20
440#define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
441#define MVPP2_PRS_TCAM_INV_WORD 5
442
443#define MVPP2_PE_DROP_ALL 0
444#define MVPP2_PE_FIRST_FREE_TID 1
445#define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
446#define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
447#define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
448#define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
449#define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
450#define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
451#define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
452#define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
453#define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
454#define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
455#define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
456#define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
457#define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
458#define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
459#define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
460#define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
461#define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
462#define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
463#define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
464#define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
465#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
466#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
467#define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
468#define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
469#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
470
471
472
473
474#define MVPP2_PRS_SRAM_RI_OFFS 0
475#define MVPP2_PRS_SRAM_RI_WORD 0
476#define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
477#define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
478#define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
479#define MVPP2_PRS_SRAM_SHIFT_OFFS 64
480#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
481#define MVPP2_PRS_SRAM_UDF_OFFS 73
482#define MVPP2_PRS_SRAM_UDF_BITS 8
483#define MVPP2_PRS_SRAM_UDF_MASK 0xff
484#define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
485#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
486#define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
487#define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
488#define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
489#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
490#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
491#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
492#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
493#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
494#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
495#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
496#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
497#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
498#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
499#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
500#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
501#define MVPP2_PRS_SRAM_AI_OFFS 90
502#define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
503#define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
504#define MVPP2_PRS_SRAM_AI_MASK 0xff
505#define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
506#define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
507#define MVPP2_PRS_SRAM_LU_DONE_BIT 110
508#define MVPP2_PRS_SRAM_LU_GEN_BIT 111
509
510
511#define MVPP2_PRS_RI_MAC_ME_MASK 0x1
512#define MVPP2_PRS_RI_DSA_MASK 0x2
513#define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
514#define MVPP2_PRS_RI_VLAN_NONE 0x0
515#define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
516#define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
517#define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
518#define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
519#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
520#define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
521#define MVPP2_PRS_RI_L2_UCAST 0x0
522#define MVPP2_PRS_RI_L2_MCAST BIT(9)
523#define MVPP2_PRS_RI_L2_BCAST BIT(10)
524#define MVPP2_PRS_RI_PPPOE_MASK 0x800
525#define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
526#define MVPP2_PRS_RI_L3_UN 0x0
527#define MVPP2_PRS_RI_L3_IP4 BIT(12)
528#define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
529#define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
530#define MVPP2_PRS_RI_L3_IP6 BIT(14)
531#define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
532#define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
533#define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
534#define MVPP2_PRS_RI_L3_UCAST 0x0
535#define MVPP2_PRS_RI_L3_MCAST BIT(15)
536#define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
537#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
538#define MVPP2_PRS_RI_UDF3_MASK 0x300000
539#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
540#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
541#define MVPP2_PRS_RI_L4_TCP BIT(22)
542#define MVPP2_PRS_RI_L4_UDP BIT(23)
543#define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
544#define MVPP2_PRS_RI_UDF7_MASK 0x60000000
545#define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
546#define MVPP2_PRS_RI_DROP_MASK 0x80000000
547
548
549#define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
550#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
551#define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
552#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
553#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
554#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
555#define MVPP2_PRS_SINGLE_VLAN_AI 0
556#define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
557
558
559#define MVPP2_PRS_TAGGED true
560#define MVPP2_PRS_UNTAGGED false
561#define MVPP2_PRS_EDSA true
562#define MVPP2_PRS_DSA false
563
564
565enum mvpp2_prs_udf {
566 MVPP2_PRS_UDF_MAC_DEF,
567 MVPP2_PRS_UDF_MAC_RANGE,
568 MVPP2_PRS_UDF_L2_DEF,
569 MVPP2_PRS_UDF_L2_DEF_COPY,
570 MVPP2_PRS_UDF_L2_USER,
571};
572
573
574enum mvpp2_prs_lookup {
575 MVPP2_PRS_LU_MH,
576 MVPP2_PRS_LU_MAC,
577 MVPP2_PRS_LU_DSA,
578 MVPP2_PRS_LU_VLAN,
579 MVPP2_PRS_LU_L2,
580 MVPP2_PRS_LU_PPPOE,
581 MVPP2_PRS_LU_IP4,
582 MVPP2_PRS_LU_IP6,
583 MVPP2_PRS_LU_FLOWS,
584 MVPP2_PRS_LU_LAST,
585};
586
587
588enum mvpp2_prs_l3_cast {
589 MVPP2_PRS_L3_UNI_CAST,
590 MVPP2_PRS_L3_MULTI_CAST,
591 MVPP2_PRS_L3_BROAD_CAST
592};
593
594
595#define MVPP2_CLS_FLOWS_TBL_SIZE 512
596#define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
597#define MVPP2_CLS_LKP_TBL_SIZE 64
598
599
600#define MVPP2_BM_POOLS_NUM 8
601#define MVPP2_BM_LONG_BUF_NUM 1024
602#define MVPP2_BM_SHORT_BUF_NUM 2048
603#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
604#define MVPP2_BM_POOL_PTR_ALIGN 128
605#define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port)
606#define MVPP2_BM_SWF_SHORT_POOL 3
607
608
609#define MVPP2_BM_COOKIE_POOL_OFFS 8
610#define MVPP2_BM_COOKIE_CPU_OFFS 24
611
612
613
614
615
616#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
617
618enum mvpp2_bm_type {
619 MVPP2_BM_FREE,
620 MVPP2_BM_SWF_LONG,
621 MVPP2_BM_SWF_SHORT
622};
623
624
625
626
627struct mvpp2 {
628
629 void __iomem *base;
630 void __iomem *lms_base;
631
632
633 struct clk *pp_clk;
634 struct clk *gop_clk;
635
636
637 struct mvpp2_port **port_list;
638
639
640 struct mvpp2_tx_queue *aggr_txqs;
641
642
643 struct mvpp2_bm_pool *bm_pools;
644
645
646 struct mvpp2_prs_shadow *prs_shadow;
647
648 bool *prs_double_vlans;
649
650
651 u32 tclk;
652};
653
654struct mvpp2_pcpu_stats {
655 struct u64_stats_sync syncp;
656 u64 rx_packets;
657 u64 rx_bytes;
658 u64 tx_packets;
659 u64 tx_bytes;
660};
661
662
663struct mvpp2_port_pcpu {
664 struct hrtimer tx_done_timer;
665 bool timer_scheduled;
666
667 struct tasklet_struct tx_done_tasklet;
668};
669
670struct mvpp2_port {
671 u8 id;
672
673 int irq;
674
675 struct mvpp2 *priv;
676
677
678 void __iomem *base;
679
680 struct mvpp2_rx_queue **rxqs;
681 struct mvpp2_tx_queue **txqs;
682 struct net_device *dev;
683
684 int pkt_size;
685
686 u32 pending_cause_rx;
687 struct napi_struct napi;
688
689
690 struct mvpp2_port_pcpu __percpu *pcpu;
691
692
693 unsigned long flags;
694
695 u16 tx_ring_size;
696 u16 rx_ring_size;
697 struct mvpp2_pcpu_stats __percpu *stats;
698
699 phy_interface_t phy_interface;
700 struct device_node *phy_node;
701 unsigned int link;
702 unsigned int duplex;
703 unsigned int speed;
704
705 struct mvpp2_bm_pool *pool_long;
706 struct mvpp2_bm_pool *pool_short;
707
708
709 u8 first_rxq;
710};
711
712
713
714
715
716
717#define MVPP2_TXD_L3_OFF_SHIFT 0
718#define MVPP2_TXD_IP_HLEN_SHIFT 8
719#define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
720#define MVPP2_TXD_L4_CSUM_NOT BIT(14)
721#define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
722#define MVPP2_TXD_PADDING_DISABLE BIT(23)
723#define MVPP2_TXD_L4_UDP BIT(24)
724#define MVPP2_TXD_L3_IP6 BIT(26)
725#define MVPP2_TXD_L_DESC BIT(28)
726#define MVPP2_TXD_F_DESC BIT(29)
727
728#define MVPP2_RXD_ERR_SUMMARY BIT(15)
729#define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
730#define MVPP2_RXD_ERR_CRC 0x0
731#define MVPP2_RXD_ERR_OVERRUN BIT(13)
732#define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
733#define MVPP2_RXD_BM_POOL_ID_OFFS 16
734#define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
735#define MVPP2_RXD_HWF_SYNC BIT(21)
736#define MVPP2_RXD_L4_CSUM_OK BIT(22)
737#define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
738#define MVPP2_RXD_L4_TCP BIT(25)
739#define MVPP2_RXD_L4_UDP BIT(26)
740#define MVPP2_RXD_L3_IP4 BIT(28)
741#define MVPP2_RXD_L3_IP6 BIT(30)
742#define MVPP2_RXD_BUF_HDR BIT(31)
743
744struct mvpp2_tx_desc {
745 u32 command;
746 u8 packet_offset;
747 u8 phys_txq;
748 u16 data_size;
749 u32 buf_phys_addr;
750 u32 buf_cookie;
751 u32 reserved1[3];
752 u32 reserved2;
753};
754
755struct mvpp2_rx_desc {
756 u32 status;
757 u16 reserved1;
758 u16 data_size;
759 u32 buf_phys_addr;
760 u32 buf_cookie;
761 u16 reserved2;
762 u16 reserved3;
763 u8 reserved4;
764 u8 reserved5;
765 u16 reserved6;
766 u32 reserved7;
767 u32 reserved8;
768};
769
770struct mvpp2_txq_pcpu_buf {
771
772 struct sk_buff *skb;
773
774
775 dma_addr_t phys;
776
777
778 size_t size;
779};
780
781
782struct mvpp2_txq_pcpu {
783 int cpu;
784
785
786 int size;
787
788
789
790
791 int count;
792
793
794 int reserved_num;
795
796
797 struct mvpp2_txq_pcpu_buf *buffs;
798
799
800 int txq_put_index;
801
802
803 int txq_get_index;
804};
805
806struct mvpp2_tx_queue {
807
808 u8 id;
809
810
811 u8 log_id;
812
813
814 int size;
815
816
817 int count;
818
819
820 struct mvpp2_txq_pcpu __percpu *pcpu;
821
822 u32 done_pkts_coal;
823
824
825 struct mvpp2_tx_desc *descs;
826
827
828 dma_addr_t descs_phys;
829
830
831 int last_desc;
832
833
834 int next_desc_to_proc;
835};
836
837struct mvpp2_rx_queue {
838
839 u8 id;
840
841
842 int size;
843
844 u32 pkts_coal;
845 u32 time_coal;
846
847
848 struct mvpp2_rx_desc *descs;
849
850
851 dma_addr_t descs_phys;
852
853
854 int last_desc;
855
856
857 int next_desc_to_proc;
858
859
860 int port;
861
862
863 int logic_rxq;
864};
865
866union mvpp2_prs_tcam_entry {
867 u32 word[MVPP2_PRS_TCAM_WORDS];
868 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
869};
870
871union mvpp2_prs_sram_entry {
872 u32 word[MVPP2_PRS_SRAM_WORDS];
873 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
874};
875
876struct mvpp2_prs_entry {
877 u32 index;
878 union mvpp2_prs_tcam_entry tcam;
879 union mvpp2_prs_sram_entry sram;
880};
881
882struct mvpp2_prs_shadow {
883 bool valid;
884 bool finish;
885
886
887 int lu;
888
889
890 int udf;
891
892
893 u32 ri;
894 u32 ri_mask;
895};
896
897struct mvpp2_cls_flow_entry {
898 u32 index;
899 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
900};
901
902struct mvpp2_cls_lookup_entry {
903 u32 lkpid;
904 u32 way;
905 u32 data;
906};
907
908struct mvpp2_bm_pool {
909
910 int id;
911 enum mvpp2_bm_type type;
912
913
914 int size;
915
916 int buf_num;
917
918 int buf_size;
919
920 int pkt_size;
921 int frag_size;
922
923
924 u32 *virt_addr;
925
926 dma_addr_t phys_addr;
927
928
929 u32 port_map;
930};
931
932struct mvpp2_buff_hdr {
933 u32 next_buff_phys_addr;
934 u32 next_buff_virt_addr;
935 u16 byte_count;
936 u16 info;
937 u8 reserved1;
938};
939
940
941#define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
942#define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
943#define MVPP2_B_HDR_INFO_LAST_OFFS 12
944#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
945#define MVPP2_B_HDR_INFO_IS_LAST(info) \
946 ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
947
948
949
950
951static int rxq_number = MVPP2_DEFAULT_RXQ;
952
953static int txq_number = MVPP2_MAX_TXQ;
954
955#define MVPP2_DRIVER_NAME "mvpp2"
956#define MVPP2_DRIVER_VERSION "1.0"
957
958
959
960static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
961{
962 writel(data, priv->base + offset);
963}
964
965static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
966{
967 return readl(priv->base + offset);
968}
969
970static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
971{
972 txq_pcpu->txq_get_index++;
973 if (txq_pcpu->txq_get_index == txq_pcpu->size)
974 txq_pcpu->txq_get_index = 0;
975}
976
977static void mvpp2_txq_inc_put(struct mvpp2_txq_pcpu *txq_pcpu,
978 struct sk_buff *skb,
979 struct mvpp2_tx_desc *tx_desc)
980{
981 struct mvpp2_txq_pcpu_buf *tx_buf =
982 txq_pcpu->buffs + txq_pcpu->txq_put_index;
983 tx_buf->skb = skb;
984 tx_buf->size = tx_desc->data_size;
985 tx_buf->phys = tx_desc->buf_phys_addr + tx_desc->packet_offset;
986 txq_pcpu->txq_put_index++;
987 if (txq_pcpu->txq_put_index == txq_pcpu->size)
988 txq_pcpu->txq_put_index = 0;
989}
990
991
992static inline int mvpp2_egress_port(struct mvpp2_port *port)
993{
994 return MVPP2_MAX_TCONT + port->id;
995}
996
997
998static inline int mvpp2_txq_phys(int port, int txq)
999{
1000 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1001}
1002
1003
1004
1005
1006static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1007{
1008 int i;
1009
1010 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1011 return -EINVAL;
1012
1013
1014 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1015
1016
1017 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1018 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1019 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1020
1021
1022 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1023 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1024 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1025
1026 return 0;
1027}
1028
1029
1030static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1031{
1032 int i;
1033
1034 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1035 return -EINVAL;
1036
1037
1038 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1039
1040 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1041 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1042 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1043 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1044
1045 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1046 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1047
1048
1049 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1050 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1051 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1052
1053 return 0;
1054}
1055
1056
1057static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1058{
1059
1060 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1061 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1062 MVPP2_PRS_TCAM_INV_MASK);
1063}
1064
1065
1066static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1067{
1068 priv->prs_shadow[index].valid = true;
1069 priv->prs_shadow[index].lu = lu;
1070}
1071
1072
1073static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1074 unsigned int ri, unsigned int ri_mask)
1075{
1076 priv->prs_shadow[index].ri_mask = ri_mask;
1077 priv->prs_shadow[index].ri = ri;
1078}
1079
1080
1081static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1082{
1083 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1084
1085 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1086 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1087}
1088
1089
1090static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1091 unsigned int port, bool add)
1092{
1093 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1094
1095 if (add)
1096 pe->tcam.byte[enable_off] &= ~(1 << port);
1097 else
1098 pe->tcam.byte[enable_off] |= 1 << port;
1099}
1100
1101
1102static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1103 unsigned int ports)
1104{
1105 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1106 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1107
1108 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1109 pe->tcam.byte[enable_off] &= ~port_mask;
1110 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1111}
1112
1113
1114static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1115{
1116 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1117
1118 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1119}
1120
1121
1122static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1123 unsigned int offs, unsigned char byte,
1124 unsigned char enable)
1125{
1126 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1127 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1128}
1129
1130
1131static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1132 unsigned int offs, unsigned char *byte,
1133 unsigned char *enable)
1134{
1135 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1136 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1137}
1138
1139
1140static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs,
1141 u16 data)
1142{
1143 int off = MVPP2_PRS_TCAM_DATA_BYTE(offs);
1144 u16 tcam_data;
1145
1146 tcam_data = (8 << pe->tcam.byte[off + 1]) | pe->tcam.byte[off];
1147 if (tcam_data != data)
1148 return false;
1149 return true;
1150}
1151
1152
1153static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe,
1154 unsigned int bits, unsigned int enable)
1155{
1156 int i, ai_idx = MVPP2_PRS_TCAM_AI_BYTE;
1157
1158 for (i = 0; i < MVPP2_PRS_AI_BITS; i++) {
1159
1160 if (!(enable & BIT(i)))
1161 continue;
1162
1163 if (bits & BIT(i))
1164 pe->tcam.byte[ai_idx] |= 1 << i;
1165 else
1166 pe->tcam.byte[ai_idx] &= ~(1 << i);
1167 }
1168
1169 pe->tcam.byte[MVPP2_PRS_TCAM_EN_OFFS(ai_idx)] |= enable;
1170}
1171
1172
1173static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe)
1174{
1175 return pe->tcam.byte[MVPP2_PRS_TCAM_AI_BYTE];
1176}
1177
1178
1179static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1180 unsigned short ethertype)
1181{
1182 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1183 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1184}
1185
1186
1187static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1188 int val)
1189{
1190 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1191}
1192
1193
1194static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1195 int val)
1196{
1197 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1198}
1199
1200
1201static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1202 unsigned int bits, unsigned int mask)
1203{
1204 unsigned int i;
1205
1206 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1207 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1208
1209 if (!(mask & BIT(i)))
1210 continue;
1211
1212 if (bits & BIT(i))
1213 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1214 else
1215 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1216
1217 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1218 }
1219}
1220
1221
1222static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe)
1223{
1224 return pe->sram.word[MVPP2_PRS_SRAM_RI_WORD];
1225}
1226
1227
1228static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1229 unsigned int bits, unsigned int mask)
1230{
1231 unsigned int i;
1232 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1233
1234 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1235
1236 if (!(mask & BIT(i)))
1237 continue;
1238
1239 if (bits & BIT(i))
1240 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1241 else
1242 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1243
1244 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1245 }
1246}
1247
1248
1249static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1250{
1251 u8 bits;
1252 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1253 int ai_en_off = ai_off + 1;
1254 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1255
1256 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1257 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1258
1259 return bits;
1260}
1261
1262
1263
1264
1265static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1266 unsigned int lu)
1267{
1268 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1269
1270 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1271 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1272 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1273}
1274
1275
1276
1277
1278static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1279 unsigned int op)
1280{
1281
1282 if (shift < 0) {
1283 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1284 shift = 0 - shift;
1285 } else {
1286 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1287 }
1288
1289
1290 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1291 (unsigned char)shift;
1292
1293
1294 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1295 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1296 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1297
1298
1299 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1300}
1301
1302
1303
1304
1305static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1306 unsigned int type, int offset,
1307 unsigned int op)
1308{
1309
1310 if (offset < 0) {
1311 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1312 offset = 0 - offset;
1313 } else {
1314 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1315 }
1316
1317
1318 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1319 MVPP2_PRS_SRAM_UDF_MASK);
1320 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1321 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1322 MVPP2_PRS_SRAM_UDF_BITS)] &=
1323 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1324 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1325 MVPP2_PRS_SRAM_UDF_BITS)] |=
1326 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1327
1328
1329 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1330 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1331 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1332
1333
1334 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1335 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1336 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1337
1338 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1339 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1340 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1341 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1342
1343 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1344 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1345 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1346
1347
1348 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1349}
1350
1351
1352static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1353{
1354 struct mvpp2_prs_entry *pe;
1355 int tid;
1356
1357 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1358 if (!pe)
1359 return NULL;
1360 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1361
1362
1363 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1364 u8 bits;
1365
1366 if (!priv->prs_shadow[tid].valid ||
1367 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1368 continue;
1369
1370 pe->index = tid;
1371 mvpp2_prs_hw_read(priv, pe);
1372 bits = mvpp2_prs_sram_ai_get(pe);
1373
1374
1375 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1376 return pe;
1377 }
1378 kfree(pe);
1379
1380 return NULL;
1381}
1382
1383
1384static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1385 unsigned char end)
1386{
1387 int tid;
1388
1389 if (start > end)
1390 swap(start, end);
1391
1392 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1393 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1394
1395 for (tid = start; tid <= end; tid++) {
1396 if (!priv->prs_shadow[tid].valid)
1397 return tid;
1398 }
1399
1400 return -EINVAL;
1401}
1402
1403
1404static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1405{
1406 struct mvpp2_prs_entry pe;
1407
1408 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1409
1410 pe.index = MVPP2_PE_DROP_ALL;
1411 mvpp2_prs_hw_read(priv, &pe);
1412 } else {
1413
1414 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1415 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1416 pe.index = MVPP2_PE_DROP_ALL;
1417
1418
1419 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1420 MVPP2_PRS_RI_DROP_MASK);
1421
1422 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1423 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1424
1425
1426 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1427
1428
1429 mvpp2_prs_tcam_port_map_set(&pe, 0);
1430 }
1431
1432
1433 mvpp2_prs_tcam_port_set(&pe, port, add);
1434
1435 mvpp2_prs_hw_write(priv, &pe);
1436}
1437
1438
1439static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1440{
1441 struct mvpp2_prs_entry pe;
1442
1443
1444
1445 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1446
1447 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1448 mvpp2_prs_hw_read(priv, &pe);
1449 } else {
1450
1451 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1452 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1453 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1454
1455
1456 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1457
1458
1459 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1460 MVPP2_PRS_RI_L2_CAST_MASK);
1461
1462
1463 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1464 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1465
1466
1467 mvpp2_prs_tcam_port_map_set(&pe, 0);
1468
1469
1470 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1471 }
1472
1473
1474 mvpp2_prs_tcam_port_set(&pe, port, add);
1475
1476 mvpp2_prs_hw_write(priv, &pe);
1477}
1478
1479
1480static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1481 bool add)
1482{
1483 struct mvpp2_prs_entry pe;
1484 unsigned char da_mc;
1485
1486
1487
1488
1489 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1490
1491 if (priv->prs_shadow[index].valid) {
1492
1493 pe.index = index;
1494 mvpp2_prs_hw_read(priv, &pe);
1495 } else {
1496
1497 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1498 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1499 pe.index = index;
1500
1501
1502 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1503
1504
1505 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1506 MVPP2_PRS_RI_L2_CAST_MASK);
1507
1508
1509 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1510
1511
1512 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1513 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1514
1515
1516 mvpp2_prs_tcam_port_map_set(&pe, 0);
1517
1518
1519 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1520 }
1521
1522
1523 mvpp2_prs_tcam_port_set(&pe, port, add);
1524
1525 mvpp2_prs_hw_write(priv, &pe);
1526}
1527
1528
1529static void mvpp2_prs_dsa_tag_set(struct mvpp2 *priv, int port, bool add,
1530 bool tagged, bool extend)
1531{
1532 struct mvpp2_prs_entry pe;
1533 int tid, shift;
1534
1535 if (extend) {
1536 tid = tagged ? MVPP2_PE_EDSA_TAGGED : MVPP2_PE_EDSA_UNTAGGED;
1537 shift = 8;
1538 } else {
1539 tid = tagged ? MVPP2_PE_DSA_TAGGED : MVPP2_PE_DSA_UNTAGGED;
1540 shift = 4;
1541 }
1542
1543 if (priv->prs_shadow[tid].valid) {
1544
1545 pe.index = tid;
1546 mvpp2_prs_hw_read(priv, &pe);
1547 } else {
1548
1549 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1550 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
1551 pe.index = tid;
1552
1553
1554 mvpp2_prs_sram_shift_set(&pe, shift,
1555 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1556
1557
1558 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
1559
1560 if (tagged) {
1561
1562 mvpp2_prs_tcam_data_byte_set(&pe, 0,
1563 MVPP2_PRS_TCAM_DSA_TAGGED_BIT,
1564 MVPP2_PRS_TCAM_DSA_TAGGED_BIT);
1565
1566 mvpp2_prs_sram_ai_update(&pe, 0,
1567 MVPP2_PRS_SRAM_AI_MASK);
1568
1569 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1570 } else {
1571
1572 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
1573 MVPP2_PRS_RI_VLAN_MASK);
1574 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1575 }
1576
1577
1578 mvpp2_prs_tcam_port_map_set(&pe, 0);
1579 }
1580
1581
1582 mvpp2_prs_tcam_port_set(&pe, port, add);
1583
1584 mvpp2_prs_hw_write(priv, &pe);
1585}
1586
1587
1588static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2 *priv, int port,
1589 bool add, bool tagged, bool extend)
1590{
1591 struct mvpp2_prs_entry pe;
1592 int tid, shift, port_mask;
1593
1594 if (extend) {
1595 tid = tagged ? MVPP2_PE_ETYPE_EDSA_TAGGED :
1596 MVPP2_PE_ETYPE_EDSA_UNTAGGED;
1597 port_mask = 0;
1598 shift = 8;
1599 } else {
1600 tid = tagged ? MVPP2_PE_ETYPE_DSA_TAGGED :
1601 MVPP2_PE_ETYPE_DSA_UNTAGGED;
1602 port_mask = MVPP2_PRS_PORT_MASK;
1603 shift = 4;
1604 }
1605
1606 if (priv->prs_shadow[tid].valid) {
1607
1608 pe.index = tid;
1609 mvpp2_prs_hw_read(priv, &pe);
1610 } else {
1611
1612 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1613 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
1614 pe.index = tid;
1615
1616
1617 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA);
1618 mvpp2_prs_match_etype(&pe, 2, 0);
1619
1620 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK,
1621 MVPP2_PRS_RI_DSA_MASK);
1622
1623 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,
1624 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1625
1626
1627 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
1628
1629 if (tagged) {
1630
1631 mvpp2_prs_tcam_data_byte_set(&pe,
1632 MVPP2_ETH_TYPE_LEN + 2 + 3,
1633 MVPP2_PRS_TCAM_DSA_TAGGED_BIT,
1634 MVPP2_PRS_TCAM_DSA_TAGGED_BIT);
1635
1636 mvpp2_prs_sram_ai_update(&pe, 0,
1637 MVPP2_PRS_SRAM_AI_MASK);
1638
1639 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1640 } else {
1641
1642 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
1643 MVPP2_PRS_RI_VLAN_MASK);
1644 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1645 }
1646
1647 mvpp2_prs_tcam_port_map_set(&pe, port_mask);
1648 }
1649
1650
1651 mvpp2_prs_tcam_port_set(&pe, port, add);
1652
1653 mvpp2_prs_hw_write(priv, &pe);
1654}
1655
1656
1657static struct mvpp2_prs_entry *mvpp2_prs_vlan_find(struct mvpp2 *priv,
1658 unsigned short tpid, int ai)
1659{
1660 struct mvpp2_prs_entry *pe;
1661 int tid;
1662
1663 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1664 if (!pe)
1665 return NULL;
1666 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1667
1668
1669 for (tid = MVPP2_PE_FIRST_FREE_TID;
1670 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
1671 unsigned int ri_bits, ai_bits;
1672 bool match;
1673
1674 if (!priv->prs_shadow[tid].valid ||
1675 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)
1676 continue;
1677
1678 pe->index = tid;
1679
1680 mvpp2_prs_hw_read(priv, pe);
1681 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid));
1682 if (!match)
1683 continue;
1684
1685
1686 ri_bits = mvpp2_prs_sram_ri_get(pe);
1687 ri_bits &= MVPP2_PRS_RI_VLAN_MASK;
1688
1689
1690 ai_bits = mvpp2_prs_tcam_ai_get(pe);
1691
1692 ai_bits &= ~MVPP2_PRS_DBL_VLAN_AI_BIT;
1693
1694 if (ai != ai_bits)
1695 continue;
1696
1697 if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE ||
1698 ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE)
1699 return pe;
1700 }
1701 kfree(pe);
1702
1703 return NULL;
1704}
1705
1706
1707static int mvpp2_prs_vlan_add(struct mvpp2 *priv, unsigned short tpid, int ai,
1708 unsigned int port_map)
1709{
1710 struct mvpp2_prs_entry *pe;
1711 int tid_aux, tid;
1712 int ret = 0;
1713
1714 pe = mvpp2_prs_vlan_find(priv, tpid, ai);
1715
1716 if (!pe) {
1717
1718 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_LAST_FREE_TID,
1719 MVPP2_PE_FIRST_FREE_TID);
1720 if (tid < 0)
1721 return tid;
1722
1723 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1724 if (!pe)
1725 return -ENOMEM;
1726
1727
1728 for (tid_aux = MVPP2_PE_LAST_FREE_TID;
1729 tid_aux >= MVPP2_PE_FIRST_FREE_TID; tid_aux--) {
1730 unsigned int ri_bits;
1731
1732 if (!priv->prs_shadow[tid_aux].valid ||
1733 priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN)
1734 continue;
1735
1736 pe->index = tid_aux;
1737 mvpp2_prs_hw_read(priv, pe);
1738 ri_bits = mvpp2_prs_sram_ri_get(pe);
1739 if ((ri_bits & MVPP2_PRS_RI_VLAN_MASK) ==
1740 MVPP2_PRS_RI_VLAN_DOUBLE)
1741 break;
1742 }
1743
1744 if (tid <= tid_aux) {
1745 ret = -EINVAL;
1746 goto error;
1747 }
1748
1749 memset(pe, 0 , sizeof(struct mvpp2_prs_entry));
1750 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1751 pe->index = tid;
1752
1753 mvpp2_prs_match_etype(pe, 0, tpid);
1754
1755 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_L2);
1756
1757 mvpp2_prs_sram_shift_set(pe, MVPP2_VLAN_TAG_LEN,
1758 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1759
1760 mvpp2_prs_sram_ai_update(pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1761
1762 if (ai == MVPP2_PRS_SINGLE_VLAN_AI) {
1763 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_SINGLE,
1764 MVPP2_PRS_RI_VLAN_MASK);
1765 } else {
1766 ai |= MVPP2_PRS_DBL_VLAN_AI_BIT;
1767 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_TRIPLE,
1768 MVPP2_PRS_RI_VLAN_MASK);
1769 }
1770 mvpp2_prs_tcam_ai_update(pe, ai, MVPP2_PRS_SRAM_AI_MASK);
1771
1772 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN);
1773 }
1774
1775 mvpp2_prs_tcam_port_map_set(pe, port_map);
1776
1777 mvpp2_prs_hw_write(priv, pe);
1778
1779error:
1780 kfree(pe);
1781
1782 return ret;
1783}
1784
1785
1786static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2 *priv)
1787{
1788 int i;
1789
1790 for (i = 1; i < MVPP2_PRS_DBL_VLANS_MAX; i++) {
1791 if (!priv->prs_double_vlans[i])
1792 return i;
1793 }
1794
1795 return -EINVAL;
1796}
1797
1798
1799static struct mvpp2_prs_entry *mvpp2_prs_double_vlan_find(struct mvpp2 *priv,
1800 unsigned short tpid1,
1801 unsigned short tpid2)
1802{
1803 struct mvpp2_prs_entry *pe;
1804 int tid;
1805
1806 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1807 if (!pe)
1808 return NULL;
1809 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1810
1811
1812 for (tid = MVPP2_PE_FIRST_FREE_TID;
1813 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
1814 unsigned int ri_mask;
1815 bool match;
1816
1817 if (!priv->prs_shadow[tid].valid ||
1818 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)
1819 continue;
1820
1821 pe->index = tid;
1822 mvpp2_prs_hw_read(priv, pe);
1823
1824 match = mvpp2_prs_tcam_data_cmp(pe, 0, swab16(tpid1))
1825 && mvpp2_prs_tcam_data_cmp(pe, 4, swab16(tpid2));
1826
1827 if (!match)
1828 continue;
1829
1830 ri_mask = mvpp2_prs_sram_ri_get(pe) & MVPP2_PRS_RI_VLAN_MASK;
1831 if (ri_mask == MVPP2_PRS_RI_VLAN_DOUBLE)
1832 return pe;
1833 }
1834 kfree(pe);
1835
1836 return NULL;
1837}
1838
1839
1840static int mvpp2_prs_double_vlan_add(struct mvpp2 *priv, unsigned short tpid1,
1841 unsigned short tpid2,
1842 unsigned int port_map)
1843{
1844 struct mvpp2_prs_entry *pe;
1845 int tid_aux, tid, ai, ret = 0;
1846
1847 pe = mvpp2_prs_double_vlan_find(priv, tpid1, tpid2);
1848
1849 if (!pe) {
1850
1851 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1852 MVPP2_PE_LAST_FREE_TID);
1853 if (tid < 0)
1854 return tid;
1855
1856 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1857 if (!pe)
1858 return -ENOMEM;
1859
1860
1861 ai = mvpp2_prs_double_vlan_ai_free_get(priv);
1862 if (ai < 0) {
1863 ret = ai;
1864 goto error;
1865 }
1866
1867
1868 for (tid_aux = MVPP2_PE_FIRST_FREE_TID;
1869 tid_aux <= MVPP2_PE_LAST_FREE_TID; tid_aux++) {
1870 unsigned int ri_bits;
1871
1872 if (!priv->prs_shadow[tid_aux].valid ||
1873 priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN)
1874 continue;
1875
1876 pe->index = tid_aux;
1877 mvpp2_prs_hw_read(priv, pe);
1878 ri_bits = mvpp2_prs_sram_ri_get(pe);
1879 ri_bits &= MVPP2_PRS_RI_VLAN_MASK;
1880 if (ri_bits == MVPP2_PRS_RI_VLAN_SINGLE ||
1881 ri_bits == MVPP2_PRS_RI_VLAN_TRIPLE)
1882 break;
1883 }
1884
1885 if (tid >= tid_aux) {
1886 ret = -ERANGE;
1887 goto error;
1888 }
1889
1890 memset(pe, 0, sizeof(struct mvpp2_prs_entry));
1891 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_VLAN);
1892 pe->index = tid;
1893
1894 priv->prs_double_vlans[ai] = true;
1895
1896 mvpp2_prs_match_etype(pe, 0, tpid1);
1897 mvpp2_prs_match_etype(pe, 4, tpid2);
1898
1899 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_VLAN);
1900
1901 mvpp2_prs_sram_shift_set(pe, 2 * MVPP2_VLAN_TAG_LEN,
1902 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1903 mvpp2_prs_sram_ri_update(pe, MVPP2_PRS_RI_VLAN_DOUBLE,
1904 MVPP2_PRS_RI_VLAN_MASK);
1905 mvpp2_prs_sram_ai_update(pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT,
1906 MVPP2_PRS_SRAM_AI_MASK);
1907
1908 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_VLAN);
1909 }
1910
1911
1912 mvpp2_prs_tcam_port_map_set(pe, port_map);
1913 mvpp2_prs_hw_write(priv, pe);
1914
1915error:
1916 kfree(pe);
1917 return ret;
1918}
1919
1920
1921static int mvpp2_prs_ip4_proto(struct mvpp2 *priv, unsigned short proto,
1922 unsigned int ri, unsigned int ri_mask)
1923{
1924 struct mvpp2_prs_entry pe;
1925 int tid;
1926
1927 if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) &&
1928 (proto != IPPROTO_IGMP))
1929 return -EINVAL;
1930
1931
1932 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1933 MVPP2_PE_LAST_FREE_TID);
1934 if (tid < 0)
1935 return tid;
1936
1937 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1938 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1939 pe.index = tid;
1940
1941
1942 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1943 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1944
1945 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1946 sizeof(struct iphdr) - 4,
1947 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1948 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1949 MVPP2_PRS_IPV4_DIP_AI_BIT);
1950 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_MASK,
1951 ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);
1952
1953 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);
1954 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
1955
1956 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1957
1958
1959 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1960 mvpp2_prs_hw_write(priv, &pe);
1961
1962
1963 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1964 MVPP2_PE_LAST_FREE_TID);
1965 if (tid < 0)
1966 return tid;
1967
1968 pe.index = tid;
1969
1970 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1971 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1972 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
1973
1974 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L);
1975 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK);
1976
1977
1978 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1979 mvpp2_prs_hw_write(priv, &pe);
1980
1981 return 0;
1982}
1983
1984
1985static int mvpp2_prs_ip4_cast(struct mvpp2 *priv, unsigned short l3_cast)
1986{
1987 struct mvpp2_prs_entry pe;
1988 int mask, tid;
1989
1990 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1991 MVPP2_PE_LAST_FREE_TID);
1992 if (tid < 0)
1993 return tid;
1994
1995 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1996 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1997 pe.index = tid;
1998
1999 switch (l3_cast) {
2000 case MVPP2_PRS_L3_MULTI_CAST:
2001 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC,
2002 MVPP2_PRS_IPV4_MC_MASK);
2003 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
2004 MVPP2_PRS_RI_L3_ADDR_MASK);
2005 break;
2006 case MVPP2_PRS_L3_BROAD_CAST:
2007 mask = MVPP2_PRS_IPV4_BC_MASK;
2008 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask);
2009 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask);
2010 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask);
2011 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask);
2012 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST,
2013 MVPP2_PRS_RI_L3_ADDR_MASK);
2014 break;
2015 default:
2016 return -EINVAL;
2017 }
2018
2019
2020 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2021 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2022
2023 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2024 MVPP2_PRS_IPV4_DIP_AI_BIT);
2025
2026 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2027
2028
2029 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2030 mvpp2_prs_hw_write(priv, &pe);
2031
2032 return 0;
2033}
2034
2035
2036static int mvpp2_prs_ip6_proto(struct mvpp2 *priv, unsigned short proto,
2037 unsigned int ri, unsigned int ri_mask)
2038{
2039 struct mvpp2_prs_entry pe;
2040 int tid;
2041
2042 if ((proto != IPPROTO_TCP) && (proto != IPPROTO_UDP) &&
2043 (proto != IPPROTO_ICMPV6) && (proto != IPPROTO_IPIP))
2044 return -EINVAL;
2045
2046 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2047 MVPP2_PE_LAST_FREE_TID);
2048 if (tid < 0)
2049 return tid;
2050
2051 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2052 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2053 pe.index = tid;
2054
2055
2056 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2057 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2058 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
2059 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2060 sizeof(struct ipv6hdr) - 6,
2061 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2062
2063 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK);
2064 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2065 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2066
2067 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2068
2069
2070 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
2071 mvpp2_prs_hw_write(priv, &pe);
2072
2073 return 0;
2074}
2075
2076
2077static int mvpp2_prs_ip6_cast(struct mvpp2 *priv, unsigned short l3_cast)
2078{
2079 struct mvpp2_prs_entry pe;
2080 int tid;
2081
2082 if (l3_cast != MVPP2_PRS_L3_MULTI_CAST)
2083 return -EINVAL;
2084
2085 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2086 MVPP2_PE_LAST_FREE_TID);
2087 if (tid < 0)
2088 return tid;
2089
2090 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2091 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2092 pe.index = tid;
2093
2094
2095 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2096 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
2097 MVPP2_PRS_RI_L3_ADDR_MASK);
2098 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2099 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2100
2101 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2102
2103 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC,
2104 MVPP2_PRS_IPV6_MC_MASK);
2105 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2106
2107 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2108
2109
2110 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
2111 mvpp2_prs_hw_write(priv, &pe);
2112
2113 return 0;
2114}
2115
2116
2117static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
2118 int lu_max, int offset)
2119{
2120 u32 val;
2121
2122
2123 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
2124 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
2125 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
2126 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
2127
2128
2129 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
2130 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
2131 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
2132 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
2133
2134
2135
2136
2137 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
2138 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
2139 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
2140 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
2141}
2142
2143
2144static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
2145{
2146 struct mvpp2_prs_entry pe;
2147 int port;
2148
2149 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
2150 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2151 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2152 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
2153
2154
2155 mvpp2_prs_tcam_port_map_set(&pe, 0);
2156
2157
2158 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
2159 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2160
2161
2162 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
2163 mvpp2_prs_hw_write(priv, &pe);
2164 }
2165}
2166
2167
2168static void mvpp2_prs_mh_init(struct mvpp2 *priv)
2169{
2170 struct mvpp2_prs_entry pe;
2171
2172 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2173
2174 pe.index = MVPP2_PE_MH_DEFAULT;
2175 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
2176 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
2177 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2178 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
2179
2180
2181 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2182
2183
2184 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
2185 mvpp2_prs_hw_write(priv, &pe);
2186}
2187
2188
2189
2190
2191static void mvpp2_prs_mac_init(struct mvpp2 *priv)
2192{
2193 struct mvpp2_prs_entry pe;
2194
2195 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2196
2197
2198 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
2199 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
2200
2201 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
2202 MVPP2_PRS_RI_DROP_MASK);
2203 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2204 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2205
2206
2207 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2208
2209
2210 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
2211 mvpp2_prs_hw_write(priv, &pe);
2212
2213
2214 mvpp2_prs_mac_drop_all_set(priv, 0, false);
2215 mvpp2_prs_mac_promisc_set(priv, 0, false);
2216 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
2217 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
2218}
2219
2220
2221static void mvpp2_prs_dsa_init(struct mvpp2 *priv)
2222{
2223 struct mvpp2_prs_entry pe;
2224
2225
2226 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED,
2227 MVPP2_PRS_EDSA);
2228
2229
2230 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
2231
2232
2233 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_UNTAGGED,
2234 MVPP2_PRS_DSA);
2235
2236
2237 mvpp2_prs_dsa_tag_set(priv, 0, false, MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
2238
2239
2240 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false,
2241 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
2242
2243
2244 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, false,
2245 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
2246
2247
2248 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true,
2249 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
2250
2251
2252 mvpp2_prs_dsa_tag_ethertype_set(priv, 0, true,
2253 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
2254
2255
2256 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2257 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
2258 pe.index = MVPP2_PE_DSA_DEFAULT;
2259 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2260
2261
2262 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2263 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
2264
2265
2266 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2267
2268
2269 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2270
2271 mvpp2_prs_hw_write(priv, &pe);
2272}
2273
2274
2275static int mvpp2_prs_etype_init(struct mvpp2 *priv)
2276{
2277 struct mvpp2_prs_entry pe;
2278 int tid;
2279
2280
2281 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2282 MVPP2_PE_LAST_FREE_TID);
2283 if (tid < 0)
2284 return tid;
2285
2286 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2287 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2288 pe.index = tid;
2289
2290 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES);
2291
2292 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
2293 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2294 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2295 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
2296 MVPP2_PRS_RI_PPPOE_MASK);
2297
2298
2299 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2300 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2301 priv->prs_shadow[pe.index].finish = false;
2302 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2303 MVPP2_PRS_RI_PPPOE_MASK);
2304 mvpp2_prs_hw_write(priv, &pe);
2305
2306
2307 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2308 MVPP2_PE_LAST_FREE_TID);
2309 if (tid < 0)
2310 return tid;
2311
2312 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2313 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2314 pe.index = tid;
2315
2316 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP);
2317
2318
2319 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2320 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2321 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2322 MVPP2_PRS_RI_L3_PROTO_MASK);
2323
2324 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2325 MVPP2_ETH_TYPE_LEN,
2326 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2327
2328
2329 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2330 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2331 priv->prs_shadow[pe.index].finish = true;
2332 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2333 MVPP2_PRS_RI_L3_PROTO_MASK);
2334 mvpp2_prs_hw_write(priv, &pe);
2335
2336
2337 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2338 MVPP2_PE_LAST_FREE_TID);
2339 if (tid < 0)
2340 return tid;
2341
2342 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2343 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2344 pe.index = tid;
2345
2346 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2347
2348
2349 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2350 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2351 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2352 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2353 MVPP2_PRS_RI_CPU_CODE_MASK |
2354 MVPP2_PRS_RI_UDF3_MASK);
2355
2356 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2357 MVPP2_ETH_TYPE_LEN,
2358 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2359
2360
2361 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2362 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2363 priv->prs_shadow[pe.index].finish = true;
2364 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2365 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2366 MVPP2_PRS_RI_CPU_CODE_MASK |
2367 MVPP2_PRS_RI_UDF3_MASK);
2368 mvpp2_prs_hw_write(priv, &pe);
2369
2370
2371 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2372 MVPP2_PE_LAST_FREE_TID);
2373 if (tid < 0)
2374 return tid;
2375
2376 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2377 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2378 pe.index = tid;
2379
2380 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP);
2381 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2382 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2383 MVPP2_PRS_IPV4_HEAD_MASK |
2384 MVPP2_PRS_IPV4_IHL_MASK);
2385
2386 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2387 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2388 MVPP2_PRS_RI_L3_PROTO_MASK);
2389
2390 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2391 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2392
2393 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2394 MVPP2_ETH_TYPE_LEN,
2395 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2396
2397
2398 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2399 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2400 priv->prs_shadow[pe.index].finish = false;
2401 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2402 MVPP2_PRS_RI_L3_PROTO_MASK);
2403 mvpp2_prs_hw_write(priv, &pe);
2404
2405
2406 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2407 MVPP2_PE_LAST_FREE_TID);
2408 if (tid < 0)
2409 return tid;
2410
2411 pe.index = tid;
2412
2413
2414 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2415 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2416
2417 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2418 MVPP2_PRS_IPV4_HEAD,
2419 MVPP2_PRS_IPV4_HEAD_MASK);
2420
2421
2422 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2423 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2424 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2425 MVPP2_PRS_RI_L3_PROTO_MASK);
2426
2427
2428 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2429 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2430 priv->prs_shadow[pe.index].finish = false;
2431 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2432 MVPP2_PRS_RI_L3_PROTO_MASK);
2433 mvpp2_prs_hw_write(priv, &pe);
2434
2435
2436 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2437 MVPP2_PE_LAST_FREE_TID);
2438 if (tid < 0)
2439 return tid;
2440
2441 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2442 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2443 pe.index = tid;
2444
2445 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6);
2446
2447
2448 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2449 MVPP2_MAX_L3_ADDR_SIZE,
2450 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2451 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2452 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2453 MVPP2_PRS_RI_L3_PROTO_MASK);
2454
2455 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2456 MVPP2_ETH_TYPE_LEN,
2457 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2458
2459 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2460 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2461 priv->prs_shadow[pe.index].finish = false;
2462 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2463 MVPP2_PRS_RI_L3_PROTO_MASK);
2464 mvpp2_prs_hw_write(priv, &pe);
2465
2466
2467 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2468 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2469 pe.index = MVPP2_PE_ETH_TYPE_UN;
2470
2471
2472 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2473
2474
2475 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2476 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2477 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2478 MVPP2_PRS_RI_L3_PROTO_MASK);
2479
2480 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2481 MVPP2_ETH_TYPE_LEN,
2482 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2483
2484
2485 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2486 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2487 priv->prs_shadow[pe.index].finish = true;
2488 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2489 MVPP2_PRS_RI_L3_PROTO_MASK);
2490 mvpp2_prs_hw_write(priv, &pe);
2491
2492 return 0;
2493}
2494
2495
2496
2497
2498
2499
2500
2501
2502static int mvpp2_prs_vlan_init(struct platform_device *pdev, struct mvpp2 *priv)
2503{
2504 struct mvpp2_prs_entry pe;
2505 int err;
2506
2507 priv->prs_double_vlans = devm_kcalloc(&pdev->dev, sizeof(bool),
2508 MVPP2_PRS_DBL_VLANS_MAX,
2509 GFP_KERNEL);
2510 if (!priv->prs_double_vlans)
2511 return -ENOMEM;
2512
2513
2514 err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021AD,
2515 MVPP2_PRS_PORT_MASK);
2516 if (err)
2517 return err;
2518
2519
2520 err = mvpp2_prs_double_vlan_add(priv, ETH_P_8021Q, ETH_P_8021Q,
2521 MVPP2_PRS_PORT_MASK);
2522 if (err)
2523 return err;
2524
2525
2526 err = mvpp2_prs_vlan_add(priv, ETH_P_8021AD, MVPP2_PRS_SINGLE_VLAN_AI,
2527 MVPP2_PRS_PORT_MASK);
2528 if (err)
2529 return err;
2530
2531
2532 err = mvpp2_prs_vlan_add(priv, ETH_P_8021Q, MVPP2_PRS_SINGLE_VLAN_AI,
2533 MVPP2_PRS_PORT_MASK);
2534 if (err)
2535 return err;
2536
2537
2538 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2539 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2540 pe.index = MVPP2_PE_VLAN_DBL;
2541
2542 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2543
2544 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2545 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
2546 MVPP2_PRS_RI_VLAN_MASK);
2547
2548 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT,
2549 MVPP2_PRS_DBL_VLAN_AI_BIT);
2550
2551 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2552
2553
2554 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
2555 mvpp2_prs_hw_write(priv, &pe);
2556
2557
2558 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2559 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
2560 pe.index = MVPP2_PE_VLAN_NONE;
2561
2562 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2563 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
2564 MVPP2_PRS_RI_VLAN_MASK);
2565
2566
2567 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2568
2569
2570 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
2571 mvpp2_prs_hw_write(priv, &pe);
2572
2573 return 0;
2574}
2575
2576
2577static int mvpp2_prs_pppoe_init(struct mvpp2 *priv)
2578{
2579 struct mvpp2_prs_entry pe;
2580 int tid;
2581
2582
2583 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2584 MVPP2_PE_LAST_FREE_TID);
2585 if (tid < 0)
2586 return tid;
2587
2588 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2589 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2590 pe.index = tid;
2591
2592 mvpp2_prs_match_etype(&pe, 0, PPP_IP);
2593
2594 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2595 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2596 MVPP2_PRS_RI_L3_PROTO_MASK);
2597
2598 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2599 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2600
2601 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2602 MVPP2_ETH_TYPE_LEN,
2603 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2604
2605
2606 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2607 mvpp2_prs_hw_write(priv, &pe);
2608
2609
2610 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2611 MVPP2_PE_LAST_FREE_TID);
2612 if (tid < 0)
2613 return tid;
2614
2615 pe.index = tid;
2616
2617 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2618 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2619 MVPP2_PRS_IPV4_HEAD_MASK |
2620 MVPP2_PRS_IPV4_IHL_MASK);
2621
2622
2623 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2624 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2625 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2626 MVPP2_PRS_RI_L3_PROTO_MASK);
2627
2628
2629 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2630 mvpp2_prs_hw_write(priv, &pe);
2631
2632
2633 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2634 MVPP2_PE_LAST_FREE_TID);
2635 if (tid < 0)
2636 return tid;
2637
2638 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2639 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2640 pe.index = tid;
2641
2642 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6);
2643
2644 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2645 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2646 MVPP2_PRS_RI_L3_PROTO_MASK);
2647
2648 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2649 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2650
2651 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2652 MVPP2_ETH_TYPE_LEN,
2653 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2654
2655
2656 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2657 mvpp2_prs_hw_write(priv, &pe);
2658
2659
2660 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2661 MVPP2_PE_LAST_FREE_TID);
2662 if (tid < 0)
2663 return tid;
2664
2665 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2666 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2667 pe.index = tid;
2668
2669 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2670 MVPP2_PRS_RI_L3_PROTO_MASK);
2671
2672
2673 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2674 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2675
2676 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2677 MVPP2_ETH_TYPE_LEN,
2678 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2679
2680
2681 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
2682 mvpp2_prs_hw_write(priv, &pe);
2683
2684 return 0;
2685}
2686
2687
2688static int mvpp2_prs_ip4_init(struct mvpp2 *priv)
2689{
2690 struct mvpp2_prs_entry pe;
2691 int err;
2692
2693
2694 err = mvpp2_prs_ip4_proto(priv, IPPROTO_TCP, MVPP2_PRS_RI_L4_TCP,
2695 MVPP2_PRS_RI_L4_PROTO_MASK);
2696 if (err)
2697 return err;
2698
2699 err = mvpp2_prs_ip4_proto(priv, IPPROTO_UDP, MVPP2_PRS_RI_L4_UDP,
2700 MVPP2_PRS_RI_L4_PROTO_MASK);
2701 if (err)
2702 return err;
2703
2704 err = mvpp2_prs_ip4_proto(priv, IPPROTO_IGMP,
2705 MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2706 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2707 MVPP2_PRS_RI_CPU_CODE_MASK |
2708 MVPP2_PRS_RI_UDF3_MASK);
2709 if (err)
2710 return err;
2711
2712
2713 err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_BROAD_CAST);
2714 if (err)
2715 return err;
2716
2717
2718 err = mvpp2_prs_ip4_cast(priv, MVPP2_PRS_L3_MULTI_CAST);
2719 if (err)
2720 return err;
2721
2722
2723 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2724 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
2725 pe.index = MVPP2_PE_IP4_PROTO_UN;
2726
2727
2728 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2729 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2730
2731 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2732 sizeof(struct iphdr) - 4,
2733 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2734 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2735 MVPP2_PRS_IPV4_DIP_AI_BIT);
2736 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
2737 MVPP2_PRS_RI_L4_PROTO_MASK);
2738
2739 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
2740
2741 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2742
2743
2744 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2745 mvpp2_prs_hw_write(priv, &pe);
2746
2747
2748 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2749 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
2750 pe.index = MVPP2_PE_IP4_ADDR_UN;
2751
2752
2753 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2754 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2755 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
2756 MVPP2_PRS_RI_L3_ADDR_MASK);
2757
2758 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
2759 MVPP2_PRS_IPV4_DIP_AI_BIT);
2760
2761 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2762
2763
2764 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2765 mvpp2_prs_hw_write(priv, &pe);
2766
2767 return 0;
2768}
2769
2770
2771static int mvpp2_prs_ip6_init(struct mvpp2 *priv)
2772{
2773 struct mvpp2_prs_entry pe;
2774 int tid, err;
2775
2776
2777 err = mvpp2_prs_ip6_proto(priv, IPPROTO_TCP,
2778 MVPP2_PRS_RI_L4_TCP,
2779 MVPP2_PRS_RI_L4_PROTO_MASK);
2780 if (err)
2781 return err;
2782
2783 err = mvpp2_prs_ip6_proto(priv, IPPROTO_UDP,
2784 MVPP2_PRS_RI_L4_UDP,
2785 MVPP2_PRS_RI_L4_PROTO_MASK);
2786 if (err)
2787 return err;
2788
2789 err = mvpp2_prs_ip6_proto(priv, IPPROTO_ICMPV6,
2790 MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2791 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2792 MVPP2_PRS_RI_CPU_CODE_MASK |
2793 MVPP2_PRS_RI_UDF3_MASK);
2794 if (err)
2795 return err;
2796
2797
2798
2799 err = mvpp2_prs_ip6_proto(priv, IPPROTO_IPIP,
2800 MVPP2_PRS_RI_UDF7_IP6_LITE,
2801 MVPP2_PRS_RI_UDF7_MASK);
2802 if (err)
2803 return err;
2804
2805
2806 err = mvpp2_prs_ip6_cast(priv, MVPP2_PRS_L3_MULTI_CAST);
2807 if (err)
2808 return err;
2809
2810
2811 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2812 MVPP2_PE_LAST_FREE_TID);
2813 if (tid < 0)
2814 return tid;
2815
2816 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2817 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2818 pe.index = tid;
2819
2820
2821 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2822 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2823 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN |
2824 MVPP2_PRS_RI_DROP_MASK,
2825 MVPP2_PRS_RI_L3_PROTO_MASK |
2826 MVPP2_PRS_RI_DROP_MASK);
2827
2828 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK);
2829 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2830 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2831
2832
2833 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2834 mvpp2_prs_hw_write(priv, &pe);
2835
2836
2837 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2838 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2839 pe.index = MVPP2_PE_IP6_PROTO_UN;
2840
2841
2842 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2843 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2844 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
2845 MVPP2_PRS_RI_L4_PROTO_MASK);
2846
2847 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
2848 sizeof(struct ipv6hdr) - 4,
2849 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2850
2851 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2852 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2853
2854 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2855
2856
2857 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2858 mvpp2_prs_hw_write(priv, &pe);
2859
2860
2861 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2862 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2863 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN;
2864
2865
2866 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2867 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2868 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
2869 MVPP2_PRS_RI_L4_PROTO_MASK);
2870
2871 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT,
2872 MVPP2_PRS_IPV6_EXT_AI_BIT);
2873
2874 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2875
2876
2877 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
2878 mvpp2_prs_hw_write(priv, &pe);
2879
2880
2881 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2882 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
2883 pe.index = MVPP2_PE_IP6_ADDR_UN;
2884
2885
2886 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2887 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
2888 MVPP2_PRS_RI_L3_ADDR_MASK);
2889 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
2890 MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2891
2892 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2893
2894 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
2895
2896 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2897
2898
2899 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
2900 mvpp2_prs_hw_write(priv, &pe);
2901
2902 return 0;
2903}
2904
2905
2906static int mvpp2_prs_default_init(struct platform_device *pdev,
2907 struct mvpp2 *priv)
2908{
2909 int err, index, i;
2910
2911
2912 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2913
2914
2915 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2916 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2917 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2918 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2919
2920 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2921 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2922 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2923 }
2924
2925
2926 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2927 mvpp2_prs_hw_inv(priv, index);
2928
2929 priv->prs_shadow = devm_kcalloc(&pdev->dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2930 sizeof(struct mvpp2_prs_shadow),
2931 GFP_KERNEL);
2932 if (!priv->prs_shadow)
2933 return -ENOMEM;
2934
2935
2936 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2937 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2938 MVPP2_PRS_PORT_LU_MAX, 0);
2939
2940 mvpp2_prs_def_flow_init(priv);
2941
2942 mvpp2_prs_mh_init(priv);
2943
2944 mvpp2_prs_mac_init(priv);
2945
2946 mvpp2_prs_dsa_init(priv);
2947
2948 err = mvpp2_prs_etype_init(priv);
2949 if (err)
2950 return err;
2951
2952 err = mvpp2_prs_vlan_init(pdev, priv);
2953 if (err)
2954 return err;
2955
2956 err = mvpp2_prs_pppoe_init(priv);
2957 if (err)
2958 return err;
2959
2960 err = mvpp2_prs_ip6_init(priv);
2961 if (err)
2962 return err;
2963
2964 err = mvpp2_prs_ip4_init(priv);
2965 if (err)
2966 return err;
2967
2968 return 0;
2969}
2970
2971
2972static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2973 const u8 *da, unsigned char *mask)
2974{
2975 unsigned char tcam_byte, tcam_mask;
2976 int index;
2977
2978 for (index = 0; index < ETH_ALEN; index++) {
2979 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2980 if (tcam_mask != mask[index])
2981 return false;
2982
2983 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2984 return false;
2985 }
2986
2987 return true;
2988}
2989
2990
2991static struct mvpp2_prs_entry *
2992mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2993 unsigned char *mask, int udf_type)
2994{
2995 struct mvpp2_prs_entry *pe;
2996 int tid;
2997
2998 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2999 if (!pe)
3000 return NULL;
3001 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
3002
3003
3004 for (tid = MVPP2_PE_FIRST_FREE_TID;
3005 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
3006 unsigned int entry_pmap;
3007
3008 if (!priv->prs_shadow[tid].valid ||
3009 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
3010 (priv->prs_shadow[tid].udf != udf_type))
3011 continue;
3012
3013 pe->index = tid;
3014 mvpp2_prs_hw_read(priv, pe);
3015 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
3016
3017 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
3018 entry_pmap == pmap)
3019 return pe;
3020 }
3021 kfree(pe);
3022
3023 return NULL;
3024}
3025
3026
3027static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
3028 const u8 *da, bool add)
3029{
3030 struct mvpp2_prs_entry *pe;
3031 unsigned int pmap, len, ri;
3032 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3033 int tid;
3034
3035
3036 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
3037 MVPP2_PRS_UDF_MAC_DEF);
3038
3039
3040 if (!pe) {
3041 if (!add)
3042 return 0;
3043
3044
3045
3046 for (tid = MVPP2_PE_FIRST_FREE_TID;
3047 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
3048 if (priv->prs_shadow[tid].valid &&
3049 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
3050 (priv->prs_shadow[tid].udf ==
3051 MVPP2_PRS_UDF_MAC_RANGE))
3052 break;
3053
3054
3055 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
3056 tid - 1);
3057 if (tid < 0)
3058 return tid;
3059
3060 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
3061 if (!pe)
3062 return -ENOMEM;
3063 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
3064 pe->index = tid;
3065
3066
3067 mvpp2_prs_tcam_port_map_set(pe, 0);
3068 }
3069
3070
3071 mvpp2_prs_tcam_port_set(pe, port, add);
3072
3073
3074 pmap = mvpp2_prs_tcam_port_map_get(pe);
3075 if (pmap == 0) {
3076 if (add) {
3077 kfree(pe);
3078 return -EINVAL;
3079 }
3080 mvpp2_prs_hw_inv(priv, pe->index);
3081 priv->prs_shadow[pe->index].valid = false;
3082 kfree(pe);
3083 return 0;
3084 }
3085
3086
3087 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
3088
3089
3090 len = ETH_ALEN;
3091 while (len--)
3092 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
3093
3094
3095 if (is_broadcast_ether_addr(da))
3096 ri = MVPP2_PRS_RI_L2_BCAST;
3097 else if (is_multicast_ether_addr(da))
3098 ri = MVPP2_PRS_RI_L2_MCAST;
3099 else
3100 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
3101
3102 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
3103 MVPP2_PRS_RI_MAC_ME_MASK);
3104 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
3105 MVPP2_PRS_RI_MAC_ME_MASK);
3106
3107
3108 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
3109 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
3110
3111
3112 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
3113 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
3114 mvpp2_prs_hw_write(priv, pe);
3115
3116 kfree(pe);
3117
3118 return 0;
3119}
3120
3121static int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da)
3122{
3123 struct mvpp2_port *port = netdev_priv(dev);
3124 int err;
3125
3126
3127 err = mvpp2_prs_mac_da_accept(port->priv, port->id, dev->dev_addr,
3128 false);
3129 if (err)
3130 return err;
3131
3132
3133 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
3134 if (err)
3135 return err;
3136
3137
3138 ether_addr_copy(dev->dev_addr, da);
3139
3140 return 0;
3141}
3142
3143
3144static void mvpp2_prs_mcast_del_all(struct mvpp2 *priv, int port)
3145{
3146 struct mvpp2_prs_entry pe;
3147 int index, tid;
3148
3149 for (tid = MVPP2_PE_FIRST_FREE_TID;
3150 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
3151 unsigned char da[ETH_ALEN], da_mask[ETH_ALEN];
3152
3153 if (!priv->prs_shadow[tid].valid ||
3154 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
3155 (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF))
3156 continue;
3157
3158
3159 pe.index = tid;
3160 mvpp2_prs_hw_read(priv, &pe);
3161
3162
3163 for (index = 0; index < ETH_ALEN; index++)
3164 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],
3165 &da_mask[index]);
3166
3167 if (is_multicast_ether_addr(da) && !is_broadcast_ether_addr(da))
3168
3169 mvpp2_prs_mac_da_accept(priv, port, da, false);
3170 }
3171}
3172
3173static int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type)
3174{
3175 switch (type) {
3176 case MVPP2_TAG_TYPE_EDSA:
3177
3178 mvpp2_prs_dsa_tag_set(priv, port, true,
3179 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3180 mvpp2_prs_dsa_tag_set(priv, port, true,
3181 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3182
3183 mvpp2_prs_dsa_tag_set(priv, port, false,
3184 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3185 mvpp2_prs_dsa_tag_set(priv, port, false,
3186 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3187 break;
3188
3189 case MVPP2_TAG_TYPE_DSA:
3190
3191 mvpp2_prs_dsa_tag_set(priv, port, true,
3192 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3193 mvpp2_prs_dsa_tag_set(priv, port, true,
3194 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3195
3196 mvpp2_prs_dsa_tag_set(priv, port, false,
3197 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3198 mvpp2_prs_dsa_tag_set(priv, port, false,
3199 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3200 break;
3201
3202 case MVPP2_TAG_TYPE_MH:
3203 case MVPP2_TAG_TYPE_NONE:
3204
3205 mvpp2_prs_dsa_tag_set(priv, port, false,
3206 MVPP2_PRS_TAGGED, MVPP2_PRS_DSA);
3207 mvpp2_prs_dsa_tag_set(priv, port, false,
3208 MVPP2_PRS_UNTAGGED, MVPP2_PRS_DSA);
3209 mvpp2_prs_dsa_tag_set(priv, port, false,
3210 MVPP2_PRS_TAGGED, MVPP2_PRS_EDSA);
3211 mvpp2_prs_dsa_tag_set(priv, port, false,
3212 MVPP2_PRS_UNTAGGED, MVPP2_PRS_EDSA);
3213 break;
3214
3215 default:
3216 if ((type < 0) || (type > MVPP2_TAG_TYPE_EDSA))
3217 return -EINVAL;
3218 }
3219
3220 return 0;
3221}
3222
3223
3224static int mvpp2_prs_def_flow(struct mvpp2_port *port)
3225{
3226 struct mvpp2_prs_entry *pe;
3227 int tid;
3228
3229 pe = mvpp2_prs_flow_find(port->priv, port->id);
3230
3231
3232 if (!pe) {
3233
3234 tid = mvpp2_prs_tcam_first_free(port->priv,
3235 MVPP2_PE_LAST_FREE_TID,
3236 MVPP2_PE_FIRST_FREE_TID);
3237 if (tid < 0)
3238 return tid;
3239
3240 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
3241 if (!pe)
3242 return -ENOMEM;
3243
3244 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
3245 pe->index = tid;
3246
3247
3248 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
3249 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
3250
3251
3252 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
3253 }
3254
3255 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
3256 mvpp2_prs_hw_write(port->priv, pe);
3257 kfree(pe);
3258
3259 return 0;
3260}
3261
3262
3263
3264
3265static void mvpp2_cls_flow_write(struct mvpp2 *priv,
3266 struct mvpp2_cls_flow_entry *fe)
3267{
3268 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
3269 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
3270 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
3271 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
3272}
3273
3274
3275static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
3276 struct mvpp2_cls_lookup_entry *le)
3277{
3278 u32 val;
3279
3280 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
3281 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
3282 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
3283}
3284
3285
3286static void mvpp2_cls_init(struct mvpp2 *priv)
3287{
3288 struct mvpp2_cls_lookup_entry le;
3289 struct mvpp2_cls_flow_entry fe;
3290 int index;
3291
3292
3293 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
3294
3295
3296 memset(&fe.data, 0, sizeof(fe.data));
3297 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
3298 fe.index = index;
3299 mvpp2_cls_flow_write(priv, &fe);
3300 }
3301
3302
3303 le.data = 0;
3304 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
3305 le.lkpid = index;
3306 le.way = 0;
3307 mvpp2_cls_lookup_write(priv, &le);
3308
3309 le.way = 1;
3310 mvpp2_cls_lookup_write(priv, &le);
3311 }
3312}
3313
3314static void mvpp2_cls_port_config(struct mvpp2_port *port)
3315{
3316 struct mvpp2_cls_lookup_entry le;
3317 u32 val;
3318
3319
3320 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
3321 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
3322 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
3323
3324
3325
3326
3327 le.lkpid = port->id;
3328 le.way = 0;
3329 le.data = 0;
3330
3331
3332 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
3333 le.data |= port->first_rxq;
3334
3335
3336 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
3337
3338
3339 mvpp2_cls_lookup_write(port->priv, &le);
3340}
3341
3342
3343static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
3344{
3345 u32 val;
3346
3347 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
3348 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
3349
3350 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
3351 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
3352
3353 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
3354 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
3355 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
3356}
3357
3358static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
3359{
3360 if (likely(pool->frag_size <= PAGE_SIZE))
3361 return netdev_alloc_frag(pool->frag_size);
3362 else
3363 return kmalloc(pool->frag_size, GFP_ATOMIC);
3364}
3365
3366static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
3367{
3368 if (likely(pool->frag_size <= PAGE_SIZE))
3369 skb_free_frag(data);
3370 else
3371 kfree(data);
3372}
3373
3374
3375
3376
3377static int mvpp2_bm_pool_create(struct platform_device *pdev,
3378 struct mvpp2 *priv,
3379 struct mvpp2_bm_pool *bm_pool, int size)
3380{
3381 int size_bytes;
3382 u32 val;
3383
3384 size_bytes = sizeof(u32) * size;
3385 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes,
3386 &bm_pool->phys_addr,
3387 GFP_KERNEL);
3388 if (!bm_pool->virt_addr)
3389 return -ENOMEM;
3390
3391 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
3392 MVPP2_BM_POOL_PTR_ALIGN)) {
3393 dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
3394 bm_pool->phys_addr);
3395 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
3396 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
3397 return -ENOMEM;
3398 }
3399
3400 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
3401 bm_pool->phys_addr);
3402 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
3403
3404 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
3405 val |= MVPP2_BM_START_MASK;
3406 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
3407
3408 bm_pool->type = MVPP2_BM_FREE;
3409 bm_pool->size = size;
3410 bm_pool->pkt_size = 0;
3411 bm_pool->buf_num = 0;
3412
3413 return 0;
3414}
3415
3416
3417static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
3418 struct mvpp2_bm_pool *bm_pool,
3419 int buf_size)
3420{
3421 u32 val;
3422
3423 bm_pool->buf_size = buf_size;
3424
3425 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
3426 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
3427}
3428
3429
3430static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
3431 struct mvpp2_bm_pool *bm_pool)
3432{
3433 int i;
3434
3435 for (i = 0; i < bm_pool->buf_num; i++) {
3436 dma_addr_t buf_phys_addr;
3437 unsigned long vaddr;
3438
3439
3440 buf_phys_addr = mvpp2_read(priv,
3441 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
3442 vaddr = mvpp2_read(priv, MVPP2_BM_VIRT_ALLOC_REG);
3443
3444 dma_unmap_single(dev, buf_phys_addr,
3445 bm_pool->buf_size, DMA_FROM_DEVICE);
3446
3447 if (!vaddr)
3448 break;
3449
3450 mvpp2_frag_free(bm_pool, (void *)vaddr);
3451 }
3452
3453
3454 bm_pool->buf_num -= i;
3455}
3456
3457
3458static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
3459 struct mvpp2 *priv,
3460 struct mvpp2_bm_pool *bm_pool)
3461{
3462 u32 val;
3463
3464 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool);
3465 if (bm_pool->buf_num) {
3466 WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id);
3467 return 0;
3468 }
3469
3470 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
3471 val |= MVPP2_BM_STOP_MASK;
3472 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
3473
3474 dma_free_coherent(&pdev->dev, sizeof(u32) * bm_pool->size,
3475 bm_pool->virt_addr,
3476 bm_pool->phys_addr);
3477 return 0;
3478}
3479
3480static int mvpp2_bm_pools_init(struct platform_device *pdev,
3481 struct mvpp2 *priv)
3482{
3483 int i, err, size;
3484 struct mvpp2_bm_pool *bm_pool;
3485
3486
3487 size = MVPP2_BM_POOL_SIZE_MAX;
3488 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
3489 bm_pool = &priv->bm_pools[i];
3490 bm_pool->id = i;
3491 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
3492 if (err)
3493 goto err_unroll_pools;
3494 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
3495 }
3496 return 0;
3497
3498err_unroll_pools:
3499 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
3500 for (i = i - 1; i >= 0; i--)
3501 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
3502 return err;
3503}
3504
3505static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
3506{
3507 int i, err;
3508
3509 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
3510
3511 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
3512
3513 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
3514 }
3515
3516
3517 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
3518 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
3519 if (!priv->bm_pools)
3520 return -ENOMEM;
3521
3522 err = mvpp2_bm_pools_init(pdev, priv);
3523 if (err < 0)
3524 return err;
3525 return 0;
3526}
3527
3528
3529static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
3530 int lrxq, int long_pool)
3531{
3532 u32 val;
3533 int prxq;
3534
3535
3536 prxq = port->rxqs[lrxq]->id;
3537
3538 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3539 val &= ~MVPP2_RXQ_POOL_LONG_MASK;
3540 val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) &
3541 MVPP2_RXQ_POOL_LONG_MASK);
3542
3543 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3544}
3545
3546
3547static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
3548 int lrxq, int short_pool)
3549{
3550 u32 val;
3551 int prxq;
3552
3553
3554 prxq = port->rxqs[lrxq]->id;
3555
3556 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3557 val &= ~MVPP2_RXQ_POOL_SHORT_MASK;
3558 val |= ((short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) &
3559 MVPP2_RXQ_POOL_SHORT_MASK);
3560
3561 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3562}
3563
3564static void *mvpp2_buf_alloc(struct mvpp2_port *port,
3565 struct mvpp2_bm_pool *bm_pool,
3566 dma_addr_t *buf_phys_addr,
3567 gfp_t gfp_mask)
3568{
3569 dma_addr_t phys_addr;
3570 void *data;
3571
3572 data = mvpp2_frag_alloc(bm_pool);
3573 if (!data)
3574 return NULL;
3575
3576 phys_addr = dma_map_single(port->dev->dev.parent, data,
3577 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
3578 DMA_FROM_DEVICE);
3579 if (unlikely(dma_mapping_error(port->dev->dev.parent, phys_addr))) {
3580 mvpp2_frag_free(bm_pool, data);
3581 return NULL;
3582 }
3583 *buf_phys_addr = phys_addr;
3584
3585 return data;
3586}
3587
3588
3589static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
3590{
3591 u32 bm;
3592
3593 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
3594 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
3595
3596 return bm;
3597}
3598
3599
3600static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
3601{
3602 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
3603}
3604
3605
3606static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
3607 dma_addr_t buf_phys_addr,
3608 unsigned long buf_virt_addr)
3609{
3610 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr);
3611 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr);
3612}
3613
3614
3615static void mvpp2_bm_pool_mc_put(struct mvpp2_port *port, int pool,
3616 dma_addr_t buf_phys_addr,
3617 unsigned long buf_virt_addr,
3618 int mc_id)
3619{
3620 u32 val = 0;
3621
3622 val |= (mc_id & MVPP2_BM_MC_ID_MASK);
3623 mvpp2_write(port->priv, MVPP2_BM_MC_RLS_REG, val);
3624
3625 mvpp2_bm_pool_put(port, pool,
3626 buf_phys_addr | MVPP2_BM_PHY_RLS_MC_BUFF_MASK,
3627 buf_virt_addr);
3628}
3629
3630
3631static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
3632 dma_addr_t phys_addr,
3633 unsigned long cookie)
3634{
3635 int pool = mvpp2_bm_cookie_pool_get(bm);
3636
3637 mvpp2_bm_pool_put(port, pool, phys_addr, cookie);
3638}
3639
3640
3641static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
3642 struct mvpp2_bm_pool *bm_pool, int buf_num)
3643{
3644 int i, buf_size, total_size;
3645 dma_addr_t phys_addr;
3646 void *buf;
3647
3648 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
3649 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
3650
3651 if (buf_num < 0 ||
3652 (buf_num + bm_pool->buf_num > bm_pool->size)) {
3653 netdev_err(port->dev,
3654 "cannot allocate %d buffers for pool %d\n",
3655 buf_num, bm_pool->id);
3656 return 0;
3657 }
3658
3659 for (i = 0; i < buf_num; i++) {
3660 buf = mvpp2_buf_alloc(port, bm_pool, &phys_addr, GFP_KERNEL);
3661 if (!buf)
3662 break;
3663
3664 mvpp2_bm_pool_put(port, bm_pool->id, phys_addr,
3665 (unsigned long)buf);
3666 }
3667
3668
3669 bm_pool->buf_num += i;
3670
3671 netdev_dbg(port->dev,
3672 "%s pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
3673 bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long",
3674 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
3675
3676 netdev_dbg(port->dev,
3677 "%s pool %d: %d of %d buffers added\n",
3678 bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long",
3679 bm_pool->id, i, buf_num);
3680 return i;
3681}
3682
3683
3684
3685
3686static struct mvpp2_bm_pool *
3687mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
3688 int pkt_size)
3689{
3690 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
3691 int num;
3692
3693 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
3694 netdev_err(port->dev, "mixing pool types is forbidden\n");
3695 return NULL;
3696 }
3697
3698 if (new_pool->type == MVPP2_BM_FREE)
3699 new_pool->type = type;
3700
3701
3702
3703
3704 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
3705 (new_pool->pkt_size == 0)) {
3706 int pkts_num;
3707
3708
3709
3710
3711 pkts_num = new_pool->buf_num;
3712 if (pkts_num == 0)
3713 pkts_num = type == MVPP2_BM_SWF_LONG ?
3714 MVPP2_BM_LONG_BUF_NUM :
3715 MVPP2_BM_SHORT_BUF_NUM;
3716 else
3717 mvpp2_bm_bufs_free(port->dev->dev.parent,
3718 port->priv, new_pool);
3719
3720 new_pool->pkt_size = pkt_size;
3721 new_pool->frag_size =
3722 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
3723 MVPP2_SKB_SHINFO_SIZE;
3724
3725
3726 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
3727 if (num != pkts_num) {
3728 WARN(1, "pool %d: %d of %d allocated\n",
3729 new_pool->id, num, pkts_num);
3730 return NULL;
3731 }
3732 }
3733
3734 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
3735 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
3736
3737 return new_pool;
3738}
3739
3740
3741static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
3742{
3743 int rxq;
3744
3745 if (!port->pool_long) {
3746 port->pool_long =
3747 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
3748 MVPP2_BM_SWF_LONG,
3749 port->pkt_size);
3750 if (!port->pool_long)
3751 return -ENOMEM;
3752
3753 port->pool_long->port_map |= (1 << port->id);
3754
3755 for (rxq = 0; rxq < rxq_number; rxq++)
3756 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
3757 }
3758
3759 if (!port->pool_short) {
3760 port->pool_short =
3761 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_SHORT_POOL,
3762 MVPP2_BM_SWF_SHORT,
3763 MVPP2_BM_SHORT_PKT_SIZE);
3764 if (!port->pool_short)
3765 return -ENOMEM;
3766
3767 port->pool_short->port_map |= (1 << port->id);
3768
3769 for (rxq = 0; rxq < rxq_number; rxq++)
3770 mvpp2_rxq_short_pool_set(port, rxq,
3771 port->pool_short->id);
3772 }
3773
3774 return 0;
3775}
3776
3777static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
3778{
3779 struct mvpp2_port *port = netdev_priv(dev);
3780 struct mvpp2_bm_pool *port_pool = port->pool_long;
3781 int num, pkts_num = port_pool->buf_num;
3782 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3783
3784
3785 mvpp2_bm_bufs_free(dev->dev.parent, port->priv, port_pool);
3786 if (port_pool->buf_num) {
3787 WARN(1, "cannot free all buffers in pool %d\n", port_pool->id);
3788 return -EIO;
3789 }
3790
3791 port_pool->pkt_size = pkt_size;
3792 port_pool->frag_size = SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
3793 MVPP2_SKB_SHINFO_SIZE;
3794 num = mvpp2_bm_bufs_add(port, port_pool, pkts_num);
3795 if (num != pkts_num) {
3796 WARN(1, "pool %d: %d of %d allocated\n",
3797 port_pool->id, num, pkts_num);
3798 return -EIO;
3799 }
3800
3801 mvpp2_bm_pool_bufsize_set(port->priv, port_pool,
3802 MVPP2_RX_BUF_SIZE(port_pool->pkt_size));
3803 dev->mtu = mtu;
3804 netdev_update_features(dev);
3805 return 0;
3806}
3807
3808static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
3809{
3810 int cpu, cpu_mask = 0;
3811
3812 for_each_present_cpu(cpu)
3813 cpu_mask |= 1 << cpu;
3814 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
3815 MVPP2_ISR_ENABLE_INTERRUPT(cpu_mask));
3816}
3817
3818static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
3819{
3820 int cpu, cpu_mask = 0;
3821
3822 for_each_present_cpu(cpu)
3823 cpu_mask |= 1 << cpu;
3824 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
3825 MVPP2_ISR_DISABLE_INTERRUPT(cpu_mask));
3826}
3827
3828
3829static void mvpp2_interrupts_mask(void *arg)
3830{
3831 struct mvpp2_port *port = arg;
3832
3833 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
3834}
3835
3836
3837static void mvpp2_interrupts_unmask(void *arg)
3838{
3839 struct mvpp2_port *port = arg;
3840
3841 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_MASK_REG(port->id),
3842 (MVPP2_CAUSE_MISC_SUM_MASK |
3843 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK));
3844}
3845
3846
3847
3848static void mvpp2_port_mii_set(struct mvpp2_port *port)
3849{
3850 u32 val;
3851
3852 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3853
3854 switch (port->phy_interface) {
3855 case PHY_INTERFACE_MODE_SGMII:
3856 val |= MVPP2_GMAC_INBAND_AN_MASK;
3857 break;
3858 case PHY_INTERFACE_MODE_RGMII:
3859 val |= MVPP2_GMAC_PORT_RGMII_MASK;
3860 default:
3861 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
3862 }
3863
3864 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3865}
3866
3867static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
3868{
3869 u32 val;
3870
3871 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3872 val |= MVPP2_GMAC_FC_ADV_EN;
3873 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3874}
3875
3876static void mvpp2_port_enable(struct mvpp2_port *port)
3877{
3878 u32 val;
3879
3880 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3881 val |= MVPP2_GMAC_PORT_EN_MASK;
3882 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
3883 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3884}
3885
3886static void mvpp2_port_disable(struct mvpp2_port *port)
3887{
3888 u32 val;
3889
3890 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3891 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
3892 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3893}
3894
3895
3896static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
3897{
3898 u32 val;
3899
3900 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
3901 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3902 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3903}
3904
3905
3906static void mvpp2_port_loopback_set(struct mvpp2_port *port)
3907{
3908 u32 val;
3909
3910 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3911
3912 if (port->speed == 1000)
3913 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
3914 else
3915 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
3916
3917 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
3918 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
3919 else
3920 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
3921
3922 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3923}
3924
3925static void mvpp2_port_reset(struct mvpp2_port *port)
3926{
3927 u32 val;
3928
3929 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
3930 ~MVPP2_GMAC_PORT_RESET_MASK;
3931 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3932
3933 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
3934 MVPP2_GMAC_PORT_RESET_MASK)
3935 continue;
3936}
3937
3938
3939static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
3940{
3941 u32 val;
3942
3943 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3944 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3945 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
3946 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
3947 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3948}
3949
3950
3951static void mvpp2_defaults_set(struct mvpp2_port *port)
3952{
3953 int tx_port_num, val, queue, ptxq, lrxq;
3954
3955
3956 if (port->flags & MVPP2_F_LOOPBACK)
3957 mvpp2_port_loopback_set(port);
3958
3959
3960 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3961 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3962
3963 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3964 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3965
3966
3967 tx_port_num = mvpp2_egress_port(port);
3968 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3969 tx_port_num);
3970 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3971
3972
3973 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3974 ptxq = mvpp2_txq_phys(port->id, queue);
3975 mvpp2_write(port->priv,
3976 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3977 }
3978
3979
3980
3981
3982 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
3983 port->priv->tclk / USEC_PER_SEC);
3984 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3985 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3986 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3987 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3988 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3989 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3990 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3991
3992
3993 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3994 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3995 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3996
3997
3998 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3999 queue = port->rxqs[lrxq]->id;
4000 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
4001 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
4002 MVPP2_SNOOP_BUF_HDR_MASK;
4003 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
4004 }
4005
4006
4007 mvpp2_interrupts_disable(port);
4008}
4009
4010
4011static void mvpp2_ingress_enable(struct mvpp2_port *port)
4012{
4013 u32 val;
4014 int lrxq, queue;
4015
4016 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
4017 queue = port->rxqs[lrxq]->id;
4018 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
4019 val &= ~MVPP2_RXQ_DISABLE_MASK;
4020 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
4021 }
4022}
4023
4024static void mvpp2_ingress_disable(struct mvpp2_port *port)
4025{
4026 u32 val;
4027 int lrxq, queue;
4028
4029 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
4030 queue = port->rxqs[lrxq]->id;
4031 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
4032 val |= MVPP2_RXQ_DISABLE_MASK;
4033 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
4034 }
4035}
4036
4037
4038
4039
4040static void mvpp2_egress_enable(struct mvpp2_port *port)
4041{
4042 u32 qmap;
4043 int queue;
4044 int tx_port_num = mvpp2_egress_port(port);
4045
4046
4047 qmap = 0;
4048 for (queue = 0; queue < txq_number; queue++) {
4049 struct mvpp2_tx_queue *txq = port->txqs[queue];
4050
4051 if (txq->descs != NULL)
4052 qmap |= (1 << queue);
4053 }
4054
4055 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4056 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
4057}
4058
4059
4060
4061
4062static void mvpp2_egress_disable(struct mvpp2_port *port)
4063{
4064 u32 reg_data;
4065 int delay;
4066 int tx_port_num = mvpp2_egress_port(port);
4067
4068
4069 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4070 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
4071 MVPP2_TXP_SCHED_ENQ_MASK;
4072 if (reg_data != 0)
4073 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
4074 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
4075
4076
4077 delay = 0;
4078 do {
4079 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
4080 netdev_warn(port->dev,
4081 "Tx stop timed out, status=0x%08x\n",
4082 reg_data);
4083 break;
4084 }
4085 mdelay(1);
4086 delay++;
4087
4088
4089
4090
4091 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
4092 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
4093}
4094
4095
4096
4097
4098static inline int
4099mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
4100{
4101 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
4102
4103 return val & MVPP2_RXQ_OCCUPIED_MASK;
4104}
4105
4106
4107
4108
4109static inline void
4110mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
4111 int used_count, int free_count)
4112{
4113
4114
4115
4116 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
4117
4118 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
4119}
4120
4121
4122static inline struct mvpp2_rx_desc *
4123mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
4124{
4125 int rx_desc = rxq->next_desc_to_proc;
4126
4127 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
4128 prefetch(rxq->descs + rxq->next_desc_to_proc);
4129 return rxq->descs + rx_desc;
4130}
4131
4132
4133static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
4134 int prxq, int offset)
4135{
4136 u32 val;
4137
4138
4139 offset = offset >> 5;
4140
4141 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
4142 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
4143
4144
4145 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
4146 MVPP2_RXQ_PACKET_OFFSET_MASK);
4147
4148 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
4149}
4150
4151
4152static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc)
4153{
4154 int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >>
4155 MVPP2_RXD_BM_POOL_ID_OFFS;
4156 int cpu = smp_processor_id();
4157
4158 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
4159 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
4160}
4161
4162
4163
4164
4165static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
4166 struct mvpp2_tx_queue *txq)
4167{
4168 u32 val;
4169
4170 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4171 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4172
4173 return val & MVPP2_TXQ_PENDING_MASK;
4174}
4175
4176
4177static struct mvpp2_tx_desc *
4178mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
4179{
4180 int tx_desc = txq->next_desc_to_proc;
4181
4182 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
4183 return txq->descs + tx_desc;
4184}
4185
4186
4187static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
4188{
4189
4190 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
4191}
4192
4193
4194
4195
4196
4197static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv,
4198 struct mvpp2_tx_queue *aggr_txq, int num)
4199{
4200 if ((aggr_txq->count + num) > aggr_txq->size) {
4201
4202 int cpu = smp_processor_id();
4203 u32 val = mvpp2_read(priv, MVPP2_AGGR_TXQ_STATUS_REG(cpu));
4204
4205 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
4206 }
4207
4208 if ((aggr_txq->count + num) > aggr_txq->size)
4209 return -ENOMEM;
4210
4211 return 0;
4212}
4213
4214
4215static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv,
4216 struct mvpp2_tx_queue *txq, int num)
4217{
4218 u32 val;
4219
4220 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
4221 mvpp2_write(priv, MVPP2_TXQ_RSVD_REQ_REG, val);
4222
4223 val = mvpp2_read(priv, MVPP2_TXQ_RSVD_RSLT_REG);
4224
4225 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
4226}
4227
4228
4229
4230
4231static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv,
4232 struct mvpp2_tx_queue *txq,
4233 struct mvpp2_txq_pcpu *txq_pcpu,
4234 int num)
4235{
4236 int req, cpu, desc_count;
4237
4238 if (txq_pcpu->reserved_num >= num)
4239 return 0;
4240
4241
4242
4243
4244
4245 desc_count = 0;
4246
4247 for_each_present_cpu(cpu) {
4248 struct mvpp2_txq_pcpu *txq_pcpu_aux;
4249
4250 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu);
4251 desc_count += txq_pcpu_aux->count;
4252 desc_count += txq_pcpu_aux->reserved_num;
4253 }
4254
4255 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
4256 desc_count += req;
4257
4258 if (desc_count >
4259 (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK)))
4260 return -ENOMEM;
4261
4262 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req);
4263
4264
4265 if (txq_pcpu->reserved_num < num)
4266 return -ENOMEM;
4267 return 0;
4268}
4269
4270
4271
4272
4273static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
4274{
4275 if (txq->next_desc_to_proc == 0)
4276 txq->next_desc_to_proc = txq->last_desc - 1;
4277 else
4278 txq->next_desc_to_proc--;
4279}
4280
4281
4282static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto,
4283 int ip_hdr_len, int l4_proto)
4284{
4285 u32 command;
4286
4287
4288
4289
4290 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
4291 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
4292 command |= MVPP2_TXD_IP_CSUM_DISABLE;
4293
4294 if (l3_proto == swab16(ETH_P_IP)) {
4295 command &= ~MVPP2_TXD_IP_CSUM_DISABLE;
4296 command &= ~MVPP2_TXD_L3_IP6;
4297 } else {
4298 command |= MVPP2_TXD_L3_IP6;
4299 }
4300
4301 if (l4_proto == IPPROTO_TCP) {
4302 command &= ~MVPP2_TXD_L4_UDP;
4303 command &= ~MVPP2_TXD_L4_CSUM_FRAG;
4304 } else if (l4_proto == IPPROTO_UDP) {
4305 command |= MVPP2_TXD_L4_UDP;
4306 command &= ~MVPP2_TXD_L4_CSUM_FRAG;
4307 } else {
4308 command |= MVPP2_TXD_L4_CSUM_NOT;
4309 }
4310
4311 return command;
4312}
4313
4314
4315
4316
4317
4318static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
4319 struct mvpp2_tx_queue *txq)
4320{
4321 u32 val;
4322
4323
4324 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
4325
4326 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
4327 MVPP2_TRANSMITTED_COUNT_OFFSET;
4328}
4329
4330static void mvpp2_txq_sent_counter_clear(void *arg)
4331{
4332 struct mvpp2_port *port = arg;
4333 int queue;
4334
4335 for (queue = 0; queue < txq_number; queue++) {
4336 int id = port->txqs[queue]->id;
4337
4338 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
4339 }
4340}
4341
4342
4343static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
4344{
4345 u32 val, size, mtu;
4346 int txq, tx_port_num;
4347
4348 mtu = port->pkt_size * 8;
4349 if (mtu > MVPP2_TXP_MTU_MAX)
4350 mtu = MVPP2_TXP_MTU_MAX;
4351
4352
4353 mtu = 3 * mtu;
4354
4355
4356 tx_port_num = mvpp2_egress_port(port);
4357 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4358
4359
4360 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
4361 val &= ~MVPP2_TXP_MTU_MAX;
4362 val |= mtu;
4363 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
4364
4365
4366 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
4367 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
4368 if (size < mtu) {
4369 size = mtu;
4370 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
4371 val |= size;
4372 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
4373 }
4374
4375 for (txq = 0; txq < txq_number; txq++) {
4376 val = mvpp2_read(port->priv,
4377 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
4378 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
4379
4380 if (size < mtu) {
4381 size = mtu;
4382 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
4383 val |= size;
4384 mvpp2_write(port->priv,
4385 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4386 val);
4387 }
4388 }
4389}
4390
4391
4392
4393
4394static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
4395 struct mvpp2_rx_queue *rxq)
4396{
4397 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
4398 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
4399
4400 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4401 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG,
4402 rxq->pkts_coal);
4403}
4404
4405static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
4406{
4407 u64 tmp = (u64)clk_hz * usec;
4408
4409 do_div(tmp, USEC_PER_SEC);
4410
4411 return tmp > U32_MAX ? U32_MAX : tmp;
4412}
4413
4414static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
4415{
4416 u64 tmp = (u64)cycles * USEC_PER_SEC;
4417
4418 do_div(tmp, clk_hz);
4419
4420 return tmp > U32_MAX ? U32_MAX : tmp;
4421}
4422
4423
4424static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
4425 struct mvpp2_rx_queue *rxq)
4426{
4427 unsigned long freq = port->priv->tclk;
4428 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
4429
4430 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
4431 rxq->time_coal =
4432 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
4433
4434
4435 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
4436 }
4437
4438 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
4439}
4440
4441
4442static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4443 struct mvpp2_tx_queue *txq,
4444 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4445{
4446 int i;
4447
4448 for (i = 0; i < num; i++) {
4449 struct mvpp2_txq_pcpu_buf *tx_buf =
4450 txq_pcpu->buffs + txq_pcpu->txq_get_index;
4451
4452 dma_unmap_single(port->dev->dev.parent, tx_buf->phys,
4453 tx_buf->size, DMA_TO_DEVICE);
4454 if (tx_buf->skb)
4455 dev_kfree_skb_any(tx_buf->skb);
4456
4457 mvpp2_txq_inc_get(txq_pcpu);
4458 }
4459}
4460
4461static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4462 u32 cause)
4463{
4464 int queue = fls(cause) - 1;
4465
4466 return port->rxqs[queue];
4467}
4468
4469static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4470 u32 cause)
4471{
4472 int queue = fls(cause) - 1;
4473
4474 return port->txqs[queue];
4475}
4476
4477
4478static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4479 struct mvpp2_txq_pcpu *txq_pcpu)
4480{
4481 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
4482 int tx_done;
4483
4484 if (txq_pcpu->cpu != smp_processor_id())
4485 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
4486
4487 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4488 if (!tx_done)
4489 return;
4490 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
4491
4492 txq_pcpu->count -= tx_done;
4493
4494 if (netif_tx_queue_stopped(nq))
4495 if (txq_pcpu->size - txq_pcpu->count >= MAX_SKB_FRAGS + 1)
4496 netif_tx_wake_queue(nq);
4497}
4498
4499static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause)
4500{
4501 struct mvpp2_tx_queue *txq;
4502 struct mvpp2_txq_pcpu *txq_pcpu;
4503 unsigned int tx_todo = 0;
4504
4505 while (cause) {
4506 txq = mvpp2_get_tx_queue(port, cause);
4507 if (!txq)
4508 break;
4509
4510 txq_pcpu = this_cpu_ptr(txq->pcpu);
4511
4512 if (txq_pcpu->count) {
4513 mvpp2_txq_done(port, txq, txq_pcpu);
4514 tx_todo += txq_pcpu->count;
4515 }
4516
4517 cause &= ~(1 << txq->log_id);
4518 }
4519 return tx_todo;
4520}
4521
4522
4523
4524
4525static int mvpp2_aggr_txq_init(struct platform_device *pdev,
4526 struct mvpp2_tx_queue *aggr_txq,
4527 int desc_num, int cpu,
4528 struct mvpp2 *priv)
4529{
4530
4531 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
4532 desc_num * MVPP2_DESC_ALIGNED_SIZE,
4533 &aggr_txq->descs_phys, GFP_KERNEL);
4534 if (!aggr_txq->descs)
4535 return -ENOMEM;
4536
4537 aggr_txq->last_desc = aggr_txq->size - 1;
4538
4539
4540 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4541 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4542
4543
4544
4545 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
4546 aggr_txq->descs_phys);
4547 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4548
4549 return 0;
4550}
4551
4552
4553static int mvpp2_rxq_init(struct mvpp2_port *port,
4554 struct mvpp2_rx_queue *rxq)
4555
4556{
4557 rxq->size = port->rx_ring_size;
4558
4559
4560 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
4561 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
4562 &rxq->descs_phys, GFP_KERNEL);
4563 if (!rxq->descs)
4564 return -ENOMEM;
4565
4566 rxq->last_desc = rxq->size - 1;
4567
4568
4569 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4570
4571
4572 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4573 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys);
4574 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4575 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4576
4577
4578 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4579
4580
4581 mvpp2_rx_pkts_coal_set(port, rxq);
4582 mvpp2_rx_time_coal_set(port, rxq);
4583
4584
4585 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4586
4587 return 0;
4588}
4589
4590
4591static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4592 struct mvpp2_rx_queue *rxq)
4593{
4594 int rx_received, i;
4595
4596 rx_received = mvpp2_rxq_received(port, rxq->id);
4597 if (!rx_received)
4598 return;
4599
4600 for (i = 0; i < rx_received; i++) {
4601 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4602 u32 bm = mvpp2_bm_cookie_build(rx_desc);
4603
4604 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
4605 rx_desc->buf_cookie);
4606 }
4607 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4608}
4609
4610
4611static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4612 struct mvpp2_rx_queue *rxq)
4613{
4614 mvpp2_rxq_drop_pkts(port, rxq);
4615
4616 if (rxq->descs)
4617 dma_free_coherent(port->dev->dev.parent,
4618 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
4619 rxq->descs,
4620 rxq->descs_phys);
4621
4622 rxq->descs = NULL;
4623 rxq->last_desc = 0;
4624 rxq->next_desc_to_proc = 0;
4625 rxq->descs_phys = 0;
4626
4627
4628
4629
4630 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4631 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4632 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4633 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4634}
4635
4636
4637static int mvpp2_txq_init(struct mvpp2_port *port,
4638 struct mvpp2_tx_queue *txq)
4639{
4640 u32 val;
4641 int cpu, desc, desc_per_txq, tx_port_num;
4642 struct mvpp2_txq_pcpu *txq_pcpu;
4643
4644 txq->size = port->tx_ring_size;
4645
4646
4647 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
4648 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4649 &txq->descs_phys, GFP_KERNEL);
4650 if (!txq->descs)
4651 return -ENOMEM;
4652
4653 txq->last_desc = txq->size - 1;
4654
4655
4656 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4657 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys);
4658 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4659 MVPP2_TXQ_DESC_SIZE_MASK);
4660 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4661 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4662 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4663 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4664 val &= ~MVPP2_TXQ_PENDING_MASK;
4665 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4666
4667
4668
4669
4670
4671
4672 desc_per_txq = 16;
4673 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4674 (txq->log_id * desc_per_txq);
4675
4676 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4677 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4678 MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
4679
4680
4681 tx_port_num = mvpp2_egress_port(port);
4682 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4683
4684 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4685 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4686 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4687 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4688 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4689
4690 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4691 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4692 val);
4693
4694 for_each_present_cpu(cpu) {
4695 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4696 txq_pcpu->size = txq->size;
4697 txq_pcpu->buffs = kmalloc(txq_pcpu->size *
4698 sizeof(struct mvpp2_txq_pcpu_buf),
4699 GFP_KERNEL);
4700 if (!txq_pcpu->buffs)
4701 goto error;
4702
4703 txq_pcpu->count = 0;
4704 txq_pcpu->reserved_num = 0;
4705 txq_pcpu->txq_put_index = 0;
4706 txq_pcpu->txq_get_index = 0;
4707 }
4708
4709 return 0;
4710
4711error:
4712 for_each_present_cpu(cpu) {
4713 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4714 kfree(txq_pcpu->buffs);
4715 }
4716
4717 dma_free_coherent(port->dev->dev.parent,
4718 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4719 txq->descs, txq->descs_phys);
4720
4721 return -ENOMEM;
4722}
4723
4724
4725static void mvpp2_txq_deinit(struct mvpp2_port *port,
4726 struct mvpp2_tx_queue *txq)
4727{
4728 struct mvpp2_txq_pcpu *txq_pcpu;
4729 int cpu;
4730
4731 for_each_present_cpu(cpu) {
4732 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4733 kfree(txq_pcpu->buffs);
4734 }
4735
4736 if (txq->descs)
4737 dma_free_coherent(port->dev->dev.parent,
4738 txq->size * MVPP2_DESC_ALIGNED_SIZE,
4739 txq->descs, txq->descs_phys);
4740
4741 txq->descs = NULL;
4742 txq->last_desc = 0;
4743 txq->next_desc_to_proc = 0;
4744 txq->descs_phys = 0;
4745
4746
4747 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4748
4749
4750 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4751 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4752 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4753}
4754
4755
4756static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4757{
4758 struct mvpp2_txq_pcpu *txq_pcpu;
4759 int delay, pending, cpu;
4760 u32 val;
4761
4762 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4763 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4764 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4765 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4766
4767
4768
4769
4770 delay = 0;
4771 do {
4772 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4773 netdev_warn(port->dev,
4774 "port %d: cleaning queue %d timed out\n",
4775 port->id, txq->log_id);
4776 break;
4777 }
4778 mdelay(1);
4779 delay++;
4780
4781 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4782 } while (pending);
4783
4784 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4785 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4786
4787 for_each_present_cpu(cpu) {
4788 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4789
4790
4791 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4792
4793
4794 txq_pcpu->count = 0;
4795 txq_pcpu->txq_put_index = 0;
4796 txq_pcpu->txq_get_index = 0;
4797 }
4798}
4799
4800
4801static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4802{
4803 struct mvpp2_tx_queue *txq;
4804 int queue;
4805 u32 val;
4806
4807 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4808
4809
4810 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4811 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4812
4813 for (queue = 0; queue < txq_number; queue++) {
4814 txq = port->txqs[queue];
4815 mvpp2_txq_clean(port, txq);
4816 mvpp2_txq_deinit(port, txq);
4817 }
4818
4819 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
4820
4821 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4822 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4823}
4824
4825
4826static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4827{
4828 int queue;
4829
4830 for (queue = 0; queue < rxq_number; queue++)
4831 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4832}
4833
4834
4835static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4836{
4837 int queue, err;
4838
4839 for (queue = 0; queue < rxq_number; queue++) {
4840 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4841 if (err)
4842 goto err_cleanup;
4843 }
4844 return 0;
4845
4846err_cleanup:
4847 mvpp2_cleanup_rxqs(port);
4848 return err;
4849}
4850
4851
4852static int mvpp2_setup_txqs(struct mvpp2_port *port)
4853{
4854 struct mvpp2_tx_queue *txq;
4855 int queue, err;
4856
4857 for (queue = 0; queue < txq_number; queue++) {
4858 txq = port->txqs[queue];
4859 err = mvpp2_txq_init(port, txq);
4860 if (err)
4861 goto err_cleanup;
4862 }
4863
4864 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
4865 return 0;
4866
4867err_cleanup:
4868 mvpp2_cleanup_txqs(port);
4869 return err;
4870}
4871
4872
4873static irqreturn_t mvpp2_isr(int irq, void *dev_id)
4874{
4875 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
4876
4877 mvpp2_interrupts_disable(port);
4878
4879 napi_schedule(&port->napi);
4880
4881 return IRQ_HANDLED;
4882}
4883
4884
4885static void mvpp2_link_event(struct net_device *dev)
4886{
4887 struct mvpp2_port *port = netdev_priv(dev);
4888 struct phy_device *phydev = dev->phydev;
4889 int status_change = 0;
4890 u32 val;
4891
4892 if (phydev->link) {
4893 if ((port->speed != phydev->speed) ||
4894 (port->duplex != phydev->duplex)) {
4895 u32 val;
4896
4897 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4898 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4899 MVPP2_GMAC_CONFIG_GMII_SPEED |
4900 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4901 MVPP2_GMAC_AN_SPEED_EN |
4902 MVPP2_GMAC_AN_DUPLEX_EN);
4903
4904 if (phydev->duplex)
4905 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4906
4907 if (phydev->speed == SPEED_1000)
4908 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4909 else if (phydev->speed == SPEED_100)
4910 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4911
4912 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4913
4914 port->duplex = phydev->duplex;
4915 port->speed = phydev->speed;
4916 }
4917 }
4918
4919 if (phydev->link != port->link) {
4920 if (!phydev->link) {
4921 port->duplex = -1;
4922 port->speed = 0;
4923 }
4924
4925 port->link = phydev->link;
4926 status_change = 1;
4927 }
4928
4929 if (status_change) {
4930 if (phydev->link) {
4931 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4932 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4933 MVPP2_GMAC_FORCE_LINK_DOWN);
4934 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4935 mvpp2_egress_enable(port);
4936 mvpp2_ingress_enable(port);
4937 } else {
4938 mvpp2_ingress_disable(port);
4939 mvpp2_egress_disable(port);
4940 }
4941 phy_print_status(phydev);
4942 }
4943}
4944
4945static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
4946{
4947 ktime_t interval;
4948
4949 if (!port_pcpu->timer_scheduled) {
4950 port_pcpu->timer_scheduled = true;
4951 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
4952 hrtimer_start(&port_pcpu->tx_done_timer, interval,
4953 HRTIMER_MODE_REL_PINNED);
4954 }
4955}
4956
4957static void mvpp2_tx_proc_cb(unsigned long data)
4958{
4959 struct net_device *dev = (struct net_device *)data;
4960 struct mvpp2_port *port = netdev_priv(dev);
4961 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
4962 unsigned int tx_todo, cause;
4963
4964 if (!netif_running(dev))
4965 return;
4966 port_pcpu->timer_scheduled = false;
4967
4968
4969 cause = (1 << txq_number) - 1;
4970 tx_todo = mvpp2_tx_done(port, cause);
4971
4972
4973 if (tx_todo)
4974 mvpp2_timer_set(port_pcpu);
4975}
4976
4977static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
4978{
4979 struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
4980 struct mvpp2_port_pcpu,
4981 tx_done_timer);
4982
4983 tasklet_schedule(&port_pcpu->tx_done_tasklet);
4984
4985 return HRTIMER_NORESTART;
4986}
4987
4988
4989
4990
4991static void mvpp2_rx_error(struct mvpp2_port *port,
4992 struct mvpp2_rx_desc *rx_desc)
4993{
4994 u32 status = rx_desc->status;
4995
4996 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4997 case MVPP2_RXD_ERR_CRC:
4998 netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n",
4999 status, rx_desc->data_size);
5000 break;
5001 case MVPP2_RXD_ERR_OVERRUN:
5002 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n",
5003 status, rx_desc->data_size);
5004 break;
5005 case MVPP2_RXD_ERR_RESOURCE:
5006 netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n",
5007 status, rx_desc->data_size);
5008 break;
5009 }
5010}
5011
5012
5013static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
5014 struct sk_buff *skb)
5015{
5016 if (((status & MVPP2_RXD_L3_IP4) &&
5017 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
5018 (status & MVPP2_RXD_L3_IP6))
5019 if (((status & MVPP2_RXD_L4_UDP) ||
5020 (status & MVPP2_RXD_L4_TCP)) &&
5021 (status & MVPP2_RXD_L4_CSUM_OK)) {
5022 skb->csum = 0;
5023 skb->ip_summed = CHECKSUM_UNNECESSARY;
5024 return;
5025 }
5026
5027 skb->ip_summed = CHECKSUM_NONE;
5028}
5029
5030
5031static int mvpp2_rx_refill(struct mvpp2_port *port,
5032 struct mvpp2_bm_pool *bm_pool, u32 bm)
5033{
5034 dma_addr_t phys_addr;
5035 void *buf;
5036
5037
5038 buf = mvpp2_buf_alloc(port, bm_pool, &phys_addr, GFP_ATOMIC);
5039 if (!buf)
5040 return -ENOMEM;
5041
5042 mvpp2_pool_refill(port, bm, phys_addr, (unsigned long)buf);
5043
5044 return 0;
5045}
5046
5047
5048static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
5049{
5050 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5051 int ip_hdr_len = 0;
5052 u8 l4_proto;
5053
5054 if (skb->protocol == htons(ETH_P_IP)) {
5055 struct iphdr *ip4h = ip_hdr(skb);
5056
5057
5058 ip_hdr_len = ip4h->ihl;
5059 l4_proto = ip4h->protocol;
5060 } else if (skb->protocol == htons(ETH_P_IPV6)) {
5061 struct ipv6hdr *ip6h = ipv6_hdr(skb);
5062
5063
5064 if (skb_network_header_len(skb) > 0)
5065 ip_hdr_len = (skb_network_header_len(skb) >> 2);
5066 l4_proto = ip6h->nexthdr;
5067 } else {
5068 return MVPP2_TXD_L4_CSUM_NOT;
5069 }
5070
5071 return mvpp2_txq_desc_csum(skb_network_offset(skb),
5072 skb->protocol, ip_hdr_len, l4_proto);
5073 }
5074
5075 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
5076}
5077
5078static void mvpp2_buff_hdr_rx(struct mvpp2_port *port,
5079 struct mvpp2_rx_desc *rx_desc)
5080{
5081 struct mvpp2_buff_hdr *buff_hdr;
5082 struct sk_buff *skb;
5083 u32 rx_status = rx_desc->status;
5084 dma_addr_t buff_phys_addr;
5085 unsigned long buff_virt_addr;
5086 dma_addr_t buff_phys_addr_next;
5087 unsigned long buff_virt_addr_next;
5088 int mc_id;
5089 int pool_id;
5090
5091 pool_id = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
5092 MVPP2_RXD_BM_POOL_ID_OFFS;
5093 buff_phys_addr = rx_desc->buf_phys_addr;
5094 buff_virt_addr = rx_desc->buf_cookie;
5095
5096 do {
5097 skb = (struct sk_buff *)buff_virt_addr;
5098 buff_hdr = (struct mvpp2_buff_hdr *)skb->head;
5099
5100 mc_id = MVPP2_B_HDR_INFO_MC_ID(buff_hdr->info);
5101
5102 buff_phys_addr_next = buff_hdr->next_buff_phys_addr;
5103 buff_virt_addr_next = buff_hdr->next_buff_virt_addr;
5104
5105
5106 mvpp2_bm_pool_mc_put(port, pool_id, buff_phys_addr,
5107 buff_virt_addr, mc_id);
5108
5109 buff_phys_addr = buff_phys_addr_next;
5110 buff_virt_addr = buff_virt_addr_next;
5111
5112 } while (!MVPP2_B_HDR_INFO_IS_LAST(buff_hdr->info));
5113}
5114
5115
5116static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
5117 struct mvpp2_rx_queue *rxq)
5118{
5119 struct net_device *dev = port->dev;
5120 int rx_received;
5121 int rx_done = 0;
5122 u32 rcvd_pkts = 0;
5123 u32 rcvd_bytes = 0;
5124
5125
5126 rx_received = mvpp2_rxq_received(port, rxq->id);
5127 if (rx_todo > rx_received)
5128 rx_todo = rx_received;
5129
5130 while (rx_done < rx_todo) {
5131 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
5132 struct mvpp2_bm_pool *bm_pool;
5133 struct sk_buff *skb;
5134 unsigned int frag_size;
5135 dma_addr_t phys_addr;
5136 u32 bm, rx_status;
5137 int pool, rx_bytes, err;
5138 void *data;
5139
5140 rx_done++;
5141 rx_status = rx_desc->status;
5142 rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE;
5143 phys_addr = rx_desc->buf_phys_addr;
5144 data = (void *)(uintptr_t)rx_desc->buf_cookie;
5145
5146 bm = mvpp2_bm_cookie_build(rx_desc);
5147 pool = mvpp2_bm_cookie_pool_get(bm);
5148 bm_pool = &port->priv->bm_pools[pool];
5149
5150 if (rx_status & MVPP2_RXD_BUF_HDR) {
5151 mvpp2_buff_hdr_rx(port, rx_desc);
5152 continue;
5153 }
5154
5155
5156
5157
5158
5159
5160 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5161 err_drop_frame:
5162 dev->stats.rx_errors++;
5163 mvpp2_rx_error(port, rx_desc);
5164
5165
5166 mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr,
5167 rx_desc->buf_cookie);
5168 continue;
5169 }
5170
5171 if (bm_pool->frag_size > PAGE_SIZE)
5172 frag_size = 0;
5173 else
5174 frag_size = bm_pool->frag_size;
5175
5176 skb = build_skb(data, frag_size);
5177 if (!skb) {
5178 netdev_warn(port->dev, "skb build failed\n");
5179 goto err_drop_frame;
5180 }
5181
5182 err = mvpp2_rx_refill(port, bm_pool, bm);
5183 if (err) {
5184 netdev_err(port->dev, "failed to refill BM pools\n");
5185 goto err_drop_frame;
5186 }
5187
5188 dma_unmap_single(dev->dev.parent, phys_addr,
5189 bm_pool->buf_size, DMA_FROM_DEVICE);
5190
5191 rcvd_pkts++;
5192 rcvd_bytes += rx_bytes;
5193
5194 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
5195 skb_put(skb, rx_bytes);
5196 skb->protocol = eth_type_trans(skb, dev);
5197 mvpp2_rx_csum(port, rx_status, skb);
5198
5199 napi_gro_receive(&port->napi, skb);
5200 }
5201
5202 if (rcvd_pkts) {
5203 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
5204
5205 u64_stats_update_begin(&stats->syncp);
5206 stats->rx_packets += rcvd_pkts;
5207 stats->rx_bytes += rcvd_bytes;
5208 u64_stats_update_end(&stats->syncp);
5209 }
5210
5211
5212 wmb();
5213 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
5214
5215 return rx_todo;
5216}
5217
5218static inline void
5219tx_desc_unmap_put(struct device *dev, struct mvpp2_tx_queue *txq,
5220 struct mvpp2_tx_desc *desc)
5221{
5222 dma_unmap_single(dev, desc->buf_phys_addr,
5223 desc->data_size, DMA_TO_DEVICE);
5224 mvpp2_txq_desc_put(txq);
5225}
5226
5227
5228static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
5229 struct mvpp2_tx_queue *aggr_txq,
5230 struct mvpp2_tx_queue *txq)
5231{
5232 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
5233 struct mvpp2_tx_desc *tx_desc;
5234 int i;
5235 dma_addr_t buf_phys_addr;
5236
5237 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5238 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5239 void *addr = page_address(frag->page.p) + frag->page_offset;
5240
5241 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5242 tx_desc->phys_txq = txq->id;
5243 tx_desc->data_size = frag->size;
5244
5245 buf_phys_addr = dma_map_single(port->dev->dev.parent, addr,
5246 tx_desc->data_size,
5247 DMA_TO_DEVICE);
5248 if (dma_mapping_error(port->dev->dev.parent, buf_phys_addr)) {
5249 mvpp2_txq_desc_put(txq);
5250 goto error;
5251 }
5252
5253 tx_desc->packet_offset = buf_phys_addr & MVPP2_TX_DESC_ALIGN;
5254 tx_desc->buf_phys_addr = buf_phys_addr & (~MVPP2_TX_DESC_ALIGN);
5255
5256 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
5257
5258 tx_desc->command = MVPP2_TXD_L_DESC;
5259 mvpp2_txq_inc_put(txq_pcpu, skb, tx_desc);
5260 } else {
5261
5262 tx_desc->command = 0;
5263 mvpp2_txq_inc_put(txq_pcpu, NULL, tx_desc);
5264 }
5265 }
5266
5267 return 0;
5268
5269error:
5270
5271
5272
5273 for (i = i - 1; i >= 0; i--) {
5274 tx_desc = txq->descs + i;
5275 tx_desc_unmap_put(port->dev->dev.parent, txq, tx_desc);
5276 }
5277
5278 return -ENOMEM;
5279}
5280
5281
5282static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
5283{
5284 struct mvpp2_port *port = netdev_priv(dev);
5285 struct mvpp2_tx_queue *txq, *aggr_txq;
5286 struct mvpp2_txq_pcpu *txq_pcpu;
5287 struct mvpp2_tx_desc *tx_desc;
5288 dma_addr_t buf_phys_addr;
5289 int frags = 0;
5290 u16 txq_id;
5291 u32 tx_cmd;
5292
5293 txq_id = skb_get_queue_mapping(skb);
5294 txq = port->txqs[txq_id];
5295 txq_pcpu = this_cpu_ptr(txq->pcpu);
5296 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5297
5298 frags = skb_shinfo(skb)->nr_frags + 1;
5299
5300
5301 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) ||
5302 mvpp2_txq_reserved_desc_num_proc(port->priv, txq,
5303 txq_pcpu, frags)) {
5304 frags = 0;
5305 goto out;
5306 }
5307
5308
5309 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5310 tx_desc->phys_txq = txq->id;
5311 tx_desc->data_size = skb_headlen(skb);
5312
5313 buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
5314 tx_desc->data_size, DMA_TO_DEVICE);
5315 if (unlikely(dma_mapping_error(dev->dev.parent, buf_phys_addr))) {
5316 mvpp2_txq_desc_put(txq);
5317 frags = 0;
5318 goto out;
5319 }
5320 tx_desc->packet_offset = buf_phys_addr & MVPP2_TX_DESC_ALIGN;
5321 tx_desc->buf_phys_addr = buf_phys_addr & ~MVPP2_TX_DESC_ALIGN;
5322
5323 tx_cmd = mvpp2_skb_tx_csum(port, skb);
5324
5325 if (frags == 1) {
5326
5327 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
5328 tx_desc->command = tx_cmd;
5329 mvpp2_txq_inc_put(txq_pcpu, skb, tx_desc);
5330 } else {
5331
5332 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
5333 tx_desc->command = tx_cmd;
5334 mvpp2_txq_inc_put(txq_pcpu, NULL, tx_desc);
5335
5336
5337 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
5338 tx_desc_unmap_put(port->dev->dev.parent, txq, tx_desc);
5339 frags = 0;
5340 goto out;
5341 }
5342 }
5343
5344 txq_pcpu->reserved_num -= frags;
5345 txq_pcpu->count += frags;
5346 aggr_txq->count += frags;
5347
5348
5349 wmb();
5350 mvpp2_aggr_txq_pend_desc_add(port, frags);
5351
5352 if (txq_pcpu->size - txq_pcpu->count < MAX_SKB_FRAGS + 1) {
5353 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
5354
5355 netif_tx_stop_queue(nq);
5356 }
5357out:
5358 if (frags > 0) {
5359 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
5360
5361 u64_stats_update_begin(&stats->syncp);
5362 stats->tx_packets++;
5363 stats->tx_bytes += skb->len;
5364 u64_stats_update_end(&stats->syncp);
5365 } else {
5366 dev->stats.tx_dropped++;
5367 dev_kfree_skb_any(skb);
5368 }
5369
5370
5371 if (txq_pcpu->count >= txq->done_pkts_coal)
5372 mvpp2_txq_done(port, txq, txq_pcpu);
5373
5374
5375 if (txq_pcpu->count <= frags && txq_pcpu->count > 0) {
5376 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
5377
5378 mvpp2_timer_set(port_pcpu);
5379 }
5380
5381 return NETDEV_TX_OK;
5382}
5383
5384static inline void mvpp2_cause_error(struct net_device *dev, int cause)
5385{
5386 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
5387 netdev_err(dev, "FCS error\n");
5388 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
5389 netdev_err(dev, "rx fifo overrun error\n");
5390 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
5391 netdev_err(dev, "tx fifo underrun error\n");
5392}
5393
5394static int mvpp2_poll(struct napi_struct *napi, int budget)
5395{
5396 u32 cause_rx_tx, cause_rx, cause_misc;
5397 int rx_done = 0;
5398 struct mvpp2_port *port = netdev_priv(napi->dev);
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410 cause_rx_tx = mvpp2_read(port->priv,
5411 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5412 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
5413 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
5414
5415 if (cause_misc) {
5416 mvpp2_cause_error(port->dev, cause_misc);
5417
5418
5419 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
5420 mvpp2_write(port->priv, MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
5421 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
5422 }
5423
5424 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
5425
5426
5427 cause_rx |= port->pending_cause_rx;
5428 while (cause_rx && budget > 0) {
5429 int count;
5430 struct mvpp2_rx_queue *rxq;
5431
5432 rxq = mvpp2_get_rx_queue(port, cause_rx);
5433 if (!rxq)
5434 break;
5435
5436 count = mvpp2_rx(port, budget, rxq);
5437 rx_done += count;
5438 budget -= count;
5439 if (budget > 0) {
5440
5441
5442
5443
5444 cause_rx &= ~(1 << rxq->logic_rxq);
5445 }
5446 }
5447
5448 if (budget > 0) {
5449 cause_rx = 0;
5450 napi_complete_done(napi, rx_done);
5451
5452 mvpp2_interrupts_enable(port);
5453 }
5454 port->pending_cause_rx = cause_rx;
5455 return rx_done;
5456}
5457
5458
5459static void mvpp2_start_dev(struct mvpp2_port *port)
5460{
5461 struct net_device *ndev = port->dev;
5462
5463 mvpp2_gmac_max_rx_size_set(port);
5464 mvpp2_txp_max_tx_size_set(port);
5465
5466 napi_enable(&port->napi);
5467
5468
5469 mvpp2_interrupts_enable(port);
5470
5471 mvpp2_port_enable(port);
5472 phy_start(ndev->phydev);
5473 netif_tx_start_all_queues(port->dev);
5474}
5475
5476
5477static void mvpp2_stop_dev(struct mvpp2_port *port)
5478{
5479 struct net_device *ndev = port->dev;
5480
5481
5482 mvpp2_ingress_disable(port);
5483
5484 mdelay(10);
5485
5486
5487 mvpp2_interrupts_disable(port);
5488
5489 napi_disable(&port->napi);
5490
5491 netif_carrier_off(port->dev);
5492 netif_tx_stop_all_queues(port->dev);
5493
5494 mvpp2_egress_disable(port);
5495 mvpp2_port_disable(port);
5496 phy_stop(ndev->phydev);
5497}
5498
5499static int mvpp2_check_ringparam_valid(struct net_device *dev,
5500 struct ethtool_ringparam *ring)
5501{
5502 u16 new_rx_pending = ring->rx_pending;
5503 u16 new_tx_pending = ring->tx_pending;
5504
5505 if (ring->rx_pending == 0 || ring->tx_pending == 0)
5506 return -EINVAL;
5507
5508 if (ring->rx_pending > MVPP2_MAX_RXD)
5509 new_rx_pending = MVPP2_MAX_RXD;
5510 else if (!IS_ALIGNED(ring->rx_pending, 16))
5511 new_rx_pending = ALIGN(ring->rx_pending, 16);
5512
5513 if (ring->tx_pending > MVPP2_MAX_TXD)
5514 new_tx_pending = MVPP2_MAX_TXD;
5515 else if (!IS_ALIGNED(ring->tx_pending, 32))
5516 new_tx_pending = ALIGN(ring->tx_pending, 32);
5517
5518 if (ring->rx_pending != new_rx_pending) {
5519 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
5520 ring->rx_pending, new_rx_pending);
5521 ring->rx_pending = new_rx_pending;
5522 }
5523
5524 if (ring->tx_pending != new_tx_pending) {
5525 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
5526 ring->tx_pending, new_tx_pending);
5527 ring->tx_pending = new_tx_pending;
5528 }
5529
5530 return 0;
5531}
5532
5533static void mvpp2_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
5534{
5535 u32 mac_addr_l, mac_addr_m, mac_addr_h;
5536
5537 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
5538 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
5539 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
5540 addr[0] = (mac_addr_h >> 24) & 0xFF;
5541 addr[1] = (mac_addr_h >> 16) & 0xFF;
5542 addr[2] = (mac_addr_h >> 8) & 0xFF;
5543 addr[3] = mac_addr_h & 0xFF;
5544 addr[4] = mac_addr_m & 0xFF;
5545 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
5546}
5547
5548static int mvpp2_phy_connect(struct mvpp2_port *port)
5549{
5550 struct phy_device *phy_dev;
5551
5552 phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0,
5553 port->phy_interface);
5554 if (!phy_dev) {
5555 netdev_err(port->dev, "cannot connect to phy\n");
5556 return -ENODEV;
5557 }
5558 phy_dev->supported &= PHY_GBIT_FEATURES;
5559 phy_dev->advertising = phy_dev->supported;
5560
5561 port->link = 0;
5562 port->duplex = 0;
5563 port->speed = 0;
5564
5565 return 0;
5566}
5567
5568static void mvpp2_phy_disconnect(struct mvpp2_port *port)
5569{
5570 struct net_device *ndev = port->dev;
5571
5572 phy_disconnect(ndev->phydev);
5573}
5574
5575static int mvpp2_open(struct net_device *dev)
5576{
5577 struct mvpp2_port *port = netdev_priv(dev);
5578 unsigned char mac_bcast[ETH_ALEN] = {
5579 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
5580 int err;
5581
5582 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
5583 if (err) {
5584 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
5585 return err;
5586 }
5587 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
5588 dev->dev_addr, true);
5589 if (err) {
5590 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
5591 return err;
5592 }
5593 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
5594 if (err) {
5595 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
5596 return err;
5597 }
5598 err = mvpp2_prs_def_flow(port);
5599 if (err) {
5600 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
5601 return err;
5602 }
5603
5604
5605 err = mvpp2_setup_rxqs(port);
5606 if (err) {
5607 netdev_err(port->dev, "cannot allocate Rx queues\n");
5608 return err;
5609 }
5610
5611 err = mvpp2_setup_txqs(port);
5612 if (err) {
5613 netdev_err(port->dev, "cannot allocate Tx queues\n");
5614 goto err_cleanup_rxqs;
5615 }
5616
5617 err = request_irq(port->irq, mvpp2_isr, 0, dev->name, port);
5618 if (err) {
5619 netdev_err(port->dev, "cannot request IRQ %d\n", port->irq);
5620 goto err_cleanup_txqs;
5621 }
5622
5623
5624 netif_carrier_off(port->dev);
5625
5626 err = mvpp2_phy_connect(port);
5627 if (err < 0)
5628 goto err_free_irq;
5629
5630
5631 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
5632
5633 mvpp2_start_dev(port);
5634
5635 return 0;
5636
5637err_free_irq:
5638 free_irq(port->irq, port);
5639err_cleanup_txqs:
5640 mvpp2_cleanup_txqs(port);
5641err_cleanup_rxqs:
5642 mvpp2_cleanup_rxqs(port);
5643 return err;
5644}
5645
5646static int mvpp2_stop(struct net_device *dev)
5647{
5648 struct mvpp2_port *port = netdev_priv(dev);
5649 struct mvpp2_port_pcpu *port_pcpu;
5650 int cpu;
5651
5652 mvpp2_stop_dev(port);
5653 mvpp2_phy_disconnect(port);
5654
5655
5656 on_each_cpu(mvpp2_interrupts_mask, port, 1);
5657
5658 free_irq(port->irq, port);
5659 for_each_present_cpu(cpu) {
5660 port_pcpu = per_cpu_ptr(port->pcpu, cpu);
5661
5662 hrtimer_cancel(&port_pcpu->tx_done_timer);
5663 port_pcpu->timer_scheduled = false;
5664 tasklet_kill(&port_pcpu->tx_done_tasklet);
5665 }
5666 mvpp2_cleanup_rxqs(port);
5667 mvpp2_cleanup_txqs(port);
5668
5669 return 0;
5670}
5671
5672static void mvpp2_set_rx_mode(struct net_device *dev)
5673{
5674 struct mvpp2_port *port = netdev_priv(dev);
5675 struct mvpp2 *priv = port->priv;
5676 struct netdev_hw_addr *ha;
5677 int id = port->id;
5678 bool allmulti = dev->flags & IFF_ALLMULTI;
5679
5680 mvpp2_prs_mac_promisc_set(priv, id, dev->flags & IFF_PROMISC);
5681 mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_ALL, allmulti);
5682 mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_IP6, allmulti);
5683
5684
5685 mvpp2_prs_mcast_del_all(priv, id);
5686
5687 if (allmulti && !netdev_mc_empty(dev)) {
5688 netdev_for_each_mc_addr(ha, dev)
5689 mvpp2_prs_mac_da_accept(priv, id, ha->addr, true);
5690 }
5691}
5692
5693static int mvpp2_set_mac_address(struct net_device *dev, void *p)
5694{
5695 struct mvpp2_port *port = netdev_priv(dev);
5696 const struct sockaddr *addr = p;
5697 int err;
5698
5699 if (!is_valid_ether_addr(addr->sa_data)) {
5700 err = -EADDRNOTAVAIL;
5701 goto error;
5702 }
5703
5704 if (!netif_running(dev)) {
5705 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5706 if (!err)
5707 return 0;
5708
5709 err = mvpp2_prs_update_mac_da(dev, dev->dev_addr);
5710 if (err)
5711 goto error;
5712 }
5713
5714 mvpp2_stop_dev(port);
5715
5716 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
5717 if (!err)
5718 goto out_start;
5719
5720
5721 err = mvpp2_prs_update_mac_da(dev, dev->dev_addr);
5722 if (err)
5723 goto error;
5724out_start:
5725 mvpp2_start_dev(port);
5726 mvpp2_egress_enable(port);
5727 mvpp2_ingress_enable(port);
5728 return 0;
5729
5730error:
5731 netdev_err(dev, "fail to change MAC address\n");
5732 return err;
5733}
5734
5735static int mvpp2_change_mtu(struct net_device *dev, int mtu)
5736{
5737 struct mvpp2_port *port = netdev_priv(dev);
5738 int err;
5739
5740 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
5741 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
5742 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
5743 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
5744 }
5745
5746 if (!netif_running(dev)) {
5747 err = mvpp2_bm_update_mtu(dev, mtu);
5748 if (!err) {
5749 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
5750 return 0;
5751 }
5752
5753
5754 err = mvpp2_bm_update_mtu(dev, dev->mtu);
5755 if (err)
5756 goto error;
5757 }
5758
5759 mvpp2_stop_dev(port);
5760
5761 err = mvpp2_bm_update_mtu(dev, mtu);
5762 if (!err) {
5763 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
5764 goto out_start;
5765 }
5766
5767
5768 err = mvpp2_bm_update_mtu(dev, dev->mtu);
5769 if (err)
5770 goto error;
5771
5772out_start:
5773 mvpp2_start_dev(port);
5774 mvpp2_egress_enable(port);
5775 mvpp2_ingress_enable(port);
5776
5777 return 0;
5778
5779error:
5780 netdev_err(dev, "fail to change MTU\n");
5781 return err;
5782}
5783
5784static void
5785mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5786{
5787 struct mvpp2_port *port = netdev_priv(dev);
5788 unsigned int start;
5789 int cpu;
5790
5791 for_each_possible_cpu(cpu) {
5792 struct mvpp2_pcpu_stats *cpu_stats;
5793 u64 rx_packets;
5794 u64 rx_bytes;
5795 u64 tx_packets;
5796 u64 tx_bytes;
5797
5798 cpu_stats = per_cpu_ptr(port->stats, cpu);
5799 do {
5800 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
5801 rx_packets = cpu_stats->rx_packets;
5802 rx_bytes = cpu_stats->rx_bytes;
5803 tx_packets = cpu_stats->tx_packets;
5804 tx_bytes = cpu_stats->tx_bytes;
5805 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
5806
5807 stats->rx_packets += rx_packets;
5808 stats->rx_bytes += rx_bytes;
5809 stats->tx_packets += tx_packets;
5810 stats->tx_bytes += tx_bytes;
5811 }
5812
5813 stats->rx_errors = dev->stats.rx_errors;
5814 stats->rx_dropped = dev->stats.rx_dropped;
5815 stats->tx_dropped = dev->stats.tx_dropped;
5816}
5817
5818static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5819{
5820 int ret;
5821
5822 if (!dev->phydev)
5823 return -ENOTSUPP;
5824
5825 ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
5826 if (!ret)
5827 mvpp2_link_event(dev);
5828
5829 return ret;
5830}
5831
5832
5833
5834
5835static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
5836 struct ethtool_coalesce *c)
5837{
5838 struct mvpp2_port *port = netdev_priv(dev);
5839 int queue;
5840
5841 for (queue = 0; queue < rxq_number; queue++) {
5842 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5843
5844 rxq->time_coal = c->rx_coalesce_usecs;
5845 rxq->pkts_coal = c->rx_max_coalesced_frames;
5846 mvpp2_rx_pkts_coal_set(port, rxq);
5847 mvpp2_rx_time_coal_set(port, rxq);
5848 }
5849
5850 for (queue = 0; queue < txq_number; queue++) {
5851 struct mvpp2_tx_queue *txq = port->txqs[queue];
5852
5853 txq->done_pkts_coal = c->tx_max_coalesced_frames;
5854 }
5855
5856 return 0;
5857}
5858
5859
5860static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
5861 struct ethtool_coalesce *c)
5862{
5863 struct mvpp2_port *port = netdev_priv(dev);
5864
5865 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
5866 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
5867 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
5868 return 0;
5869}
5870
5871static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
5872 struct ethtool_drvinfo *drvinfo)
5873{
5874 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
5875 sizeof(drvinfo->driver));
5876 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
5877 sizeof(drvinfo->version));
5878 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
5879 sizeof(drvinfo->bus_info));
5880}
5881
5882static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
5883 struct ethtool_ringparam *ring)
5884{
5885 struct mvpp2_port *port = netdev_priv(dev);
5886
5887 ring->rx_max_pending = MVPP2_MAX_RXD;
5888 ring->tx_max_pending = MVPP2_MAX_TXD;
5889 ring->rx_pending = port->rx_ring_size;
5890 ring->tx_pending = port->tx_ring_size;
5891}
5892
5893static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
5894 struct ethtool_ringparam *ring)
5895{
5896 struct mvpp2_port *port = netdev_priv(dev);
5897 u16 prev_rx_ring_size = port->rx_ring_size;
5898 u16 prev_tx_ring_size = port->tx_ring_size;
5899 int err;
5900
5901 err = mvpp2_check_ringparam_valid(dev, ring);
5902 if (err)
5903 return err;
5904
5905 if (!netif_running(dev)) {
5906 port->rx_ring_size = ring->rx_pending;
5907 port->tx_ring_size = ring->tx_pending;
5908 return 0;
5909 }
5910
5911
5912
5913
5914 mvpp2_stop_dev(port);
5915 mvpp2_cleanup_rxqs(port);
5916 mvpp2_cleanup_txqs(port);
5917
5918 port->rx_ring_size = ring->rx_pending;
5919 port->tx_ring_size = ring->tx_pending;
5920
5921 err = mvpp2_setup_rxqs(port);
5922 if (err) {
5923
5924 port->rx_ring_size = prev_rx_ring_size;
5925 ring->rx_pending = prev_rx_ring_size;
5926 err = mvpp2_setup_rxqs(port);
5927 if (err)
5928 goto err_out;
5929 }
5930 err = mvpp2_setup_txqs(port);
5931 if (err) {
5932
5933 port->tx_ring_size = prev_tx_ring_size;
5934 ring->tx_pending = prev_tx_ring_size;
5935 err = mvpp2_setup_txqs(port);
5936 if (err)
5937 goto err_clean_rxqs;
5938 }
5939
5940 mvpp2_start_dev(port);
5941 mvpp2_egress_enable(port);
5942 mvpp2_ingress_enable(port);
5943
5944 return 0;
5945
5946err_clean_rxqs:
5947 mvpp2_cleanup_rxqs(port);
5948err_out:
5949 netdev_err(dev, "fail to change ring parameters");
5950 return err;
5951}
5952
5953
5954
5955static const struct net_device_ops mvpp2_netdev_ops = {
5956 .ndo_open = mvpp2_open,
5957 .ndo_stop = mvpp2_stop,
5958 .ndo_start_xmit = mvpp2_tx,
5959 .ndo_set_rx_mode = mvpp2_set_rx_mode,
5960 .ndo_set_mac_address = mvpp2_set_mac_address,
5961 .ndo_change_mtu = mvpp2_change_mtu,
5962 .ndo_get_stats64 = mvpp2_get_stats64,
5963 .ndo_do_ioctl = mvpp2_ioctl,
5964};
5965
5966static const struct ethtool_ops mvpp2_eth_tool_ops = {
5967 .nway_reset = phy_ethtool_nway_reset,
5968 .get_link = ethtool_op_get_link,
5969 .set_coalesce = mvpp2_ethtool_set_coalesce,
5970 .get_coalesce = mvpp2_ethtool_get_coalesce,
5971 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
5972 .get_ringparam = mvpp2_ethtool_get_ringparam,
5973 .set_ringparam = mvpp2_ethtool_set_ringparam,
5974 .get_link_ksettings = phy_ethtool_get_link_ksettings,
5975 .set_link_ksettings = phy_ethtool_set_link_ksettings,
5976};
5977
5978
5979
5980static void mvpp2_port_power_up(struct mvpp2_port *port)
5981{
5982 mvpp2_port_mii_set(port);
5983 mvpp2_port_periodic_xon_disable(port);
5984 mvpp2_port_fc_adv_enable(port);
5985 mvpp2_port_reset(port);
5986}
5987
5988
5989static int mvpp2_port_init(struct mvpp2_port *port)
5990{
5991 struct device *dev = port->dev->dev.parent;
5992 struct mvpp2 *priv = port->priv;
5993 struct mvpp2_txq_pcpu *txq_pcpu;
5994 int queue, cpu, err;
5995
5996 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
5997 return -EINVAL;
5998
5999
6000 mvpp2_egress_disable(port);
6001 mvpp2_port_disable(port);
6002
6003 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
6004 GFP_KERNEL);
6005 if (!port->txqs)
6006 return -ENOMEM;
6007
6008
6009
6010
6011 for (queue = 0; queue < txq_number; queue++) {
6012 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
6013 struct mvpp2_tx_queue *txq;
6014
6015 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
6016 if (!txq) {
6017 err = -ENOMEM;
6018 goto err_free_percpu;
6019 }
6020
6021 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
6022 if (!txq->pcpu) {
6023 err = -ENOMEM;
6024 goto err_free_percpu;
6025 }
6026
6027 txq->id = queue_phy_id;
6028 txq->log_id = queue;
6029 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
6030 for_each_present_cpu(cpu) {
6031 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
6032 txq_pcpu->cpu = cpu;
6033 }
6034
6035 port->txqs[queue] = txq;
6036 }
6037
6038 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
6039 GFP_KERNEL);
6040 if (!port->rxqs) {
6041 err = -ENOMEM;
6042 goto err_free_percpu;
6043 }
6044
6045
6046 for (queue = 0; queue < rxq_number; queue++) {
6047 struct mvpp2_rx_queue *rxq;
6048
6049
6050 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
6051 if (!rxq) {
6052 err = -ENOMEM;
6053 goto err_free_percpu;
6054 }
6055
6056 rxq->id = port->first_rxq + queue;
6057 rxq->port = port->id;
6058 rxq->logic_rxq = queue;
6059
6060 port->rxqs[queue] = rxq;
6061 }
6062
6063
6064 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), rxq_number);
6065
6066
6067 for (queue = 0; queue < rxq_number; queue++) {
6068 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
6069
6070 rxq->size = port->rx_ring_size;
6071 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
6072 rxq->time_coal = MVPP2_RX_COAL_USEC;
6073 }
6074
6075 mvpp2_ingress_disable(port);
6076
6077
6078 mvpp2_defaults_set(port);
6079
6080
6081 mvpp2_cls_oversize_rxq_set(port);
6082 mvpp2_cls_port_config(port);
6083
6084
6085 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
6086
6087
6088 err = mvpp2_swf_bm_pool_init(port);
6089 if (err)
6090 goto err_free_percpu;
6091
6092 return 0;
6093
6094err_free_percpu:
6095 for (queue = 0; queue < txq_number; queue++) {
6096 if (!port->txqs[queue])
6097 continue;
6098 free_percpu(port->txqs[queue]->pcpu);
6099 }
6100 return err;
6101}
6102
6103
6104static int mvpp2_port_probe(struct platform_device *pdev,
6105 struct device_node *port_node,
6106 struct mvpp2 *priv,
6107 int *next_first_rxq)
6108{
6109 struct device_node *phy_node;
6110 struct mvpp2_port *port;
6111 struct mvpp2_port_pcpu *port_pcpu;
6112 struct net_device *dev;
6113 struct resource *res;
6114 const char *dt_mac_addr;
6115 const char *mac_from;
6116 char hw_mac_addr[ETH_ALEN];
6117 u32 id;
6118 int features;
6119 int phy_mode;
6120 int priv_common_regs_num = 2;
6121 int err, i, cpu;
6122
6123 dev = alloc_etherdev_mqs(sizeof(struct mvpp2_port), txq_number,
6124 rxq_number);
6125 if (!dev)
6126 return -ENOMEM;
6127
6128 phy_node = of_parse_phandle(port_node, "phy", 0);
6129 if (!phy_node) {
6130 dev_err(&pdev->dev, "missing phy\n");
6131 err = -ENODEV;
6132 goto err_free_netdev;
6133 }
6134
6135 phy_mode = of_get_phy_mode(port_node);
6136 if (phy_mode < 0) {
6137 dev_err(&pdev->dev, "incorrect phy mode\n");
6138 err = phy_mode;
6139 goto err_free_netdev;
6140 }
6141
6142 if (of_property_read_u32(port_node, "port-id", &id)) {
6143 err = -EINVAL;
6144 dev_err(&pdev->dev, "missing port-id value\n");
6145 goto err_free_netdev;
6146 }
6147
6148 dev->tx_queue_len = MVPP2_MAX_TXD;
6149 dev->watchdog_timeo = 5 * HZ;
6150 dev->netdev_ops = &mvpp2_netdev_ops;
6151 dev->ethtool_ops = &mvpp2_eth_tool_ops;
6152
6153 port = netdev_priv(dev);
6154
6155 port->irq = irq_of_parse_and_map(port_node, 0);
6156 if (port->irq <= 0) {
6157 err = -EINVAL;
6158 goto err_free_netdev;
6159 }
6160
6161 if (of_property_read_bool(port_node, "marvell,loopback"))
6162 port->flags |= MVPP2_F_LOOPBACK;
6163
6164 port->priv = priv;
6165 port->id = id;
6166 port->first_rxq = *next_first_rxq;
6167 port->phy_node = phy_node;
6168 port->phy_interface = phy_mode;
6169
6170 res = platform_get_resource(pdev, IORESOURCE_MEM,
6171 priv_common_regs_num + id);
6172 port->base = devm_ioremap_resource(&pdev->dev, res);
6173 if (IS_ERR(port->base)) {
6174 err = PTR_ERR(port->base);
6175 goto err_free_irq;
6176 }
6177
6178
6179 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6180 if (!port->stats) {
6181 err = -ENOMEM;
6182 goto err_free_irq;
6183 }
6184
6185 dt_mac_addr = of_get_mac_address(port_node);
6186 if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) {
6187 mac_from = "device tree";
6188 ether_addr_copy(dev->dev_addr, dt_mac_addr);
6189 } else {
6190 mvpp2_get_mac_address(port, hw_mac_addr);
6191 if (is_valid_ether_addr(hw_mac_addr)) {
6192 mac_from = "hardware";
6193 ether_addr_copy(dev->dev_addr, hw_mac_addr);
6194 } else {
6195 mac_from = "random";
6196 eth_hw_addr_random(dev);
6197 }
6198 }
6199
6200 port->tx_ring_size = MVPP2_MAX_TXD;
6201 port->rx_ring_size = MVPP2_MAX_RXD;
6202 port->dev = dev;
6203 SET_NETDEV_DEV(dev, &pdev->dev);
6204
6205 err = mvpp2_port_init(port);
6206 if (err < 0) {
6207 dev_err(&pdev->dev, "failed to init port %d\n", id);
6208 goto err_free_stats;
6209 }
6210 mvpp2_port_power_up(port);
6211
6212 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6213 if (!port->pcpu) {
6214 err = -ENOMEM;
6215 goto err_free_txq_pcpu;
6216 }
6217
6218 for_each_present_cpu(cpu) {
6219 port_pcpu = per_cpu_ptr(port->pcpu, cpu);
6220
6221 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6222 HRTIMER_MODE_REL_PINNED);
6223 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6224 port_pcpu->timer_scheduled = false;
6225
6226 tasklet_init(&port_pcpu->tx_done_tasklet, mvpp2_tx_proc_cb,
6227 (unsigned long)dev);
6228 }
6229
6230 netif_napi_add(dev, &port->napi, mvpp2_poll, NAPI_POLL_WEIGHT);
6231 features = NETIF_F_SG | NETIF_F_IP_CSUM;
6232 dev->features = features | NETIF_F_RXCSUM;
6233 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO;
6234 dev->vlan_features |= features;
6235
6236
6237 dev->min_mtu = ETH_MIN_MTU;
6238
6239 dev->max_mtu = 9676;
6240
6241 err = register_netdev(dev);
6242 if (err < 0) {
6243 dev_err(&pdev->dev, "failed to register netdev\n");
6244 goto err_free_port_pcpu;
6245 }
6246 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6247
6248
6249 *next_first_rxq += rxq_number;
6250 priv->port_list[id] = port;
6251 return 0;
6252
6253err_free_port_pcpu:
6254 free_percpu(port->pcpu);
6255err_free_txq_pcpu:
6256 for (i = 0; i < txq_number; i++)
6257 free_percpu(port->txqs[i]->pcpu);
6258err_free_stats:
6259 free_percpu(port->stats);
6260err_free_irq:
6261 irq_dispose_mapping(port->irq);
6262err_free_netdev:
6263 of_node_put(phy_node);
6264 free_netdev(dev);
6265 return err;
6266}
6267
6268
6269static void mvpp2_port_remove(struct mvpp2_port *port)
6270{
6271 int i;
6272
6273 unregister_netdev(port->dev);
6274 of_node_put(port->phy_node);
6275 free_percpu(port->pcpu);
6276 free_percpu(port->stats);
6277 for (i = 0; i < txq_number; i++)
6278 free_percpu(port->txqs[i]->pcpu);
6279 irq_dispose_mapping(port->irq);
6280 free_netdev(port->dev);
6281}
6282
6283
6284static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
6285 struct mvpp2 *priv)
6286{
6287 u32 win_enable;
6288 int i;
6289
6290 for (i = 0; i < 6; i++) {
6291 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
6292 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
6293
6294 if (i < 4)
6295 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
6296 }
6297
6298 win_enable = 0;
6299
6300 for (i = 0; i < dram->num_cs; i++) {
6301 const struct mbus_dram_window *cs = dram->cs + i;
6302
6303 mvpp2_write(priv, MVPP2_WIN_BASE(i),
6304 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
6305 dram->mbus_dram_target_id);
6306
6307 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
6308 (cs->size - 1) & 0xffff0000);
6309
6310 win_enable |= (1 << i);
6311 }
6312
6313 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
6314}
6315
6316
6317static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
6318{
6319 int port;
6320
6321 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
6322 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
6323 MVPP2_RX_FIFO_PORT_DATA_SIZE);
6324 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
6325 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
6326 }
6327
6328 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
6329 MVPP2_RX_FIFO_PORT_MIN_PKT);
6330 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
6331}
6332
6333
6334static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
6335{
6336 const struct mbus_dram_target_info *dram_target_info;
6337 int err, i;
6338 u32 val;
6339
6340
6341 if (rxq_number % 4 || (rxq_number > MVPP2_MAX_RXQ) ||
6342 (txq_number > MVPP2_MAX_TXQ)) {
6343 dev_err(&pdev->dev, "invalid queue size parameter\n");
6344 return -EINVAL;
6345 }
6346
6347
6348 dram_target_info = mv_mbus_dram_info();
6349 if (dram_target_info)
6350 mvpp2_conf_mbus_windows(dram_target_info, priv);
6351
6352
6353 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6354 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
6355 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
6356
6357
6358 priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(),
6359 sizeof(struct mvpp2_tx_queue),
6360 GFP_KERNEL);
6361 if (!priv->aggr_txqs)
6362 return -ENOMEM;
6363
6364 for_each_present_cpu(i) {
6365 priv->aggr_txqs[i].id = i;
6366 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
6367 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i],
6368 MVPP2_AGGR_TXQ_SIZE, i, priv);
6369 if (err < 0)
6370 return err;
6371 }
6372
6373
6374 mvpp2_rx_fifo_init(priv);
6375
6376
6377 for (i = 0; i < MVPP2_MAX_PORTS; i++)
6378 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i), rxq_number);
6379
6380 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
6381 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
6382
6383
6384 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
6385
6386
6387 err = mvpp2_bm_init(pdev, priv);
6388 if (err < 0)
6389 return err;
6390
6391
6392 err = mvpp2_prs_default_init(pdev, priv);
6393 if (err < 0)
6394 return err;
6395
6396
6397 mvpp2_cls_init(priv);
6398
6399 return 0;
6400}
6401
6402static int mvpp2_probe(struct platform_device *pdev)
6403{
6404 struct device_node *dn = pdev->dev.of_node;
6405 struct device_node *port_node;
6406 struct mvpp2 *priv;
6407 struct resource *res;
6408 int port_count, first_rxq;
6409 int err;
6410
6411 priv = devm_kzalloc(&pdev->dev, sizeof(struct mvpp2), GFP_KERNEL);
6412 if (!priv)
6413 return -ENOMEM;
6414
6415 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6416 priv->base = devm_ioremap_resource(&pdev->dev, res);
6417 if (IS_ERR(priv->base))
6418 return PTR_ERR(priv->base);
6419
6420 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
6421 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
6422 if (IS_ERR(priv->lms_base))
6423 return PTR_ERR(priv->lms_base);
6424
6425 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
6426 if (IS_ERR(priv->pp_clk))
6427 return PTR_ERR(priv->pp_clk);
6428 err = clk_prepare_enable(priv->pp_clk);
6429 if (err < 0)
6430 return err;
6431
6432 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
6433 if (IS_ERR(priv->gop_clk)) {
6434 err = PTR_ERR(priv->gop_clk);
6435 goto err_pp_clk;
6436 }
6437 err = clk_prepare_enable(priv->gop_clk);
6438 if (err < 0)
6439 goto err_pp_clk;
6440
6441
6442 priv->tclk = clk_get_rate(priv->pp_clk);
6443
6444
6445 err = mvpp2_init(pdev, priv);
6446 if (err < 0) {
6447 dev_err(&pdev->dev, "failed to initialize controller\n");
6448 goto err_gop_clk;
6449 }
6450
6451 port_count = of_get_available_child_count(dn);
6452 if (port_count == 0) {
6453 dev_err(&pdev->dev, "no ports enabled\n");
6454 err = -ENODEV;
6455 goto err_gop_clk;
6456 }
6457
6458 priv->port_list = devm_kcalloc(&pdev->dev, port_count,
6459 sizeof(struct mvpp2_port *),
6460 GFP_KERNEL);
6461 if (!priv->port_list) {
6462 err = -ENOMEM;
6463 goto err_gop_clk;
6464 }
6465
6466
6467 first_rxq = 0;
6468 for_each_available_child_of_node(dn, port_node) {
6469 err = mvpp2_port_probe(pdev, port_node, priv, &first_rxq);
6470 if (err < 0)
6471 goto err_gop_clk;
6472 }
6473
6474 platform_set_drvdata(pdev, priv);
6475 return 0;
6476
6477err_gop_clk:
6478 clk_disable_unprepare(priv->gop_clk);
6479err_pp_clk:
6480 clk_disable_unprepare(priv->pp_clk);
6481 return err;
6482}
6483
6484static int mvpp2_remove(struct platform_device *pdev)
6485{
6486 struct mvpp2 *priv = platform_get_drvdata(pdev);
6487 struct device_node *dn = pdev->dev.of_node;
6488 struct device_node *port_node;
6489 int i = 0;
6490
6491 for_each_available_child_of_node(dn, port_node) {
6492 if (priv->port_list[i])
6493 mvpp2_port_remove(priv->port_list[i]);
6494 i++;
6495 }
6496
6497 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
6498 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
6499
6500 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
6501 }
6502
6503 for_each_present_cpu(i) {
6504 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
6505
6506 dma_free_coherent(&pdev->dev,
6507 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
6508 aggr_txq->descs,
6509 aggr_txq->descs_phys);
6510 }
6511
6512 clk_disable_unprepare(priv->pp_clk);
6513 clk_disable_unprepare(priv->gop_clk);
6514
6515 return 0;
6516}
6517
6518static const struct of_device_id mvpp2_match[] = {
6519 { .compatible = "marvell,armada-375-pp2" },
6520 { }
6521};
6522MODULE_DEVICE_TABLE(of, mvpp2_match);
6523
6524static struct platform_driver mvpp2_driver = {
6525 .probe = mvpp2_probe,
6526 .remove = mvpp2_remove,
6527 .driver = {
6528 .name = MVPP2_DRIVER_NAME,
6529 .of_match_table = mvpp2_match,
6530 },
6531};
6532
6533module_platform_driver(mvpp2_driver);
6534
6535MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
6536MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
6537MODULE_LICENSE("GPL v2");
6538