/* QLogic qed NIC Driver
 * Copyright (c) 2015-2017  QLogic Corporation
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and /or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef _QED_HSI_H
#define _QED_HSI_H

#include <linux/types.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/qed/common_hsi.h>
#include <linux/qed/storage_common.h>
#include <linux/qed/tcp_common.h>
#include <linux/qed/fcoe_common.h>
#include <linux/qed/eth_common.h>
#include <linux/qed/iscsi_common.h>
#include <linux/qed/rdma_common.h>
#include <linux/qed/roce_common.h>
#include <linux/qed/qed_fcoe_if.h>

struct qed_hwfn;
struct qed_ptt;

/* opcodes for the event ring */
enum common_event_opcode {
        COMMON_EVENT_PF_START,
        COMMON_EVENT_PF_STOP,
        COMMON_EVENT_VF_START,
        COMMON_EVENT_VF_STOP,
        COMMON_EVENT_VF_PF_CHANNEL,
        COMMON_EVENT_VF_FLR,
        COMMON_EVENT_PF_UPDATE,
        COMMON_EVENT_MALICIOUS_VF,
        COMMON_EVENT_RL_UPDATE,
        COMMON_EVENT_EMPTY,
        MAX_COMMON_EVENT_OPCODE
};

/* Common Ramrod Command IDs */
enum common_ramrod_cmd_id {
        COMMON_RAMROD_UNUSED,
        COMMON_RAMROD_PF_START,
        COMMON_RAMROD_PF_STOP,
        COMMON_RAMROD_VF_START,
        COMMON_RAMROD_VF_STOP,
        COMMON_RAMROD_PF_UPDATE,
        COMMON_RAMROD_RL_UPDATE,
        COMMON_RAMROD_EMPTY,
        MAX_COMMON_RAMROD_CMD_ID
};

/* The core storm context for the Ystorm */
struct ystorm_core_conn_st_ctx {
        __le32 reserved[4];
};

/* The core storm context for the Pstorm */
struct pstorm_core_conn_st_ctx {
        __le32 reserved[4];
};

/* Core Slowpath Connection storm context of Xstorm */
struct xstorm_core_conn_st_ctx {
        __le32 spq_base_lo;
        __le32 spq_base_hi;
        struct regpair consolid_base_addr;
        __le16 spq_cons;
        __le16 consolid_cons;
        __le32 reserved0[55];
};

struct xstorm_core_conn_ag_ctx {
        u8 reserved0;
        u8 core_state;
        u8 flags0;
#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT         1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT         2
#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT      3
#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT         4
#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT         5
#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT         6
#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT         7
        u8 flags1;
#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT         0
#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT         1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK          0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT         2
#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK              0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT             3
#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK              0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT             4
#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK              0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT             5
#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK     0x1
#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT    6
#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT      7
        u8 flags2;
#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT       0
#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT       2
#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT       4
#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT       6
        u8 flags3;
#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT       0
#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT       2
#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT       4
#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT       6
        u8 flags4;
#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT       0
#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK        0x3
#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT       2
#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK       0x3
#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT      4
#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK       0x3
#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT      6
        u8 flags5;
#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK       0x3
#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT      0
#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK       0x3
#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT      2
#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK       0x3
#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT      4
#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK       0x3
#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT      6
        u8 flags6;
#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK   0x3
#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT  0
#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK               0x3
#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT              2
#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK              0x3
#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT             4
#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK       0x3
#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT      6
        u8 flags7;
#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK           0x3
#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK         0x3
#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT        2
#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK          0x3
#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT         4
#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK              0x1
#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT             6
#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK              0x1
#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT             7
        u8 flags8;
#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     0
#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT     1
#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT     2
#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT     3
#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT     4
#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT     5
#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT     6
#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT     7
        u8 flags9;
#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK                     0x1
#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT                    0
#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK                     0x1
#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT                    1
#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK                     0x1
#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT                    2
#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK                     0x1
#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT                    3
#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK                     0x1
#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT                    4
#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK                     0x1
#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT                    5
#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK        0x1
#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT       6
#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK                     0x1
#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT                    7
        u8 flags10;
#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT          0
#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK    0x1
#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT   1
#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1
#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       2
#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK         0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT        3
#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT      4
#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK             0x1
#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT            5
#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK         0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT        6
#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK         0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT        7
        u8 flags11;
#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK         0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT        0
#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK         0x1
#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT        1
#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK     0x1
#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT    2
#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK            0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT           3
#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK            0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT           4
#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK            0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT           5
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT      6
#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK            0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT           7
        u8 flags12;
#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT          0
#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT          1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT      2
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT      3
#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT          4
#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT          5
#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT          6
#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT          7
        u8 flags13;
#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT          0
#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK           0x1
#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT          1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT      2
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT      3
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT      4
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT      5
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT      6
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK       0x1
#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT      7
        u8 flags14;
#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT     0
#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT     1
#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT     2
#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT     3
#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT     4
#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK      0x1
#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT     5
#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK       0x3
#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT      6
        u8 byte2;
        __le16 physical_q0;
        __le16 consolid_prod;
        __le16 reserved16;
        __le16 tx_bd_cons;
        __le16 tx_bd_or_spq_prod;
        __le16 word5;
        __le16 conn_dpi;
        u8 byte3;
        u8 byte4;
        u8 byte5;
        u8 byte6;
        __le32 reg0;
        __le32 reg1;
        __le32 reg2;
        __le32 reg3;
        __le32 reg4;
        __le32 reg5;
        __le32 reg6;
        __le16 word7;
        __le16 word8;
        __le16 word9;
        __le16 word10;
        __le32 reg7;
        __le32 reg8;
        __le32 reg9;
        u8 byte7;
        u8 byte8;
        u8 byte9;
        u8 byte10;
        u8 byte11;
        u8 byte12;
        u8 byte13;
        u8 byte14;
        u8 byte15;
        u8 byte16;
        __le16 word11;
        __le32 reg10;
        __le32 reg11;
        __le32 reg12;
        __le32 reg13;
        __le32 reg14;
        __le32 reg15;
        __le32 reg16;
        __le32 reg17;
        __le32 reg18;
        __le32 reg19;
        __le16 word12;
        __le16 word13;
        __le16 word14;
        __le16 word15;
};

struct tstorm_core_conn_ag_ctx {
        u8 byte0;
        u8 byte1;
        u8 flags0;
#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK       0x1
#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT      0
#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK       0x1
#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT      1
#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK       0x1
#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT      2
#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK       0x1
#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT      3
#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK       0x1
#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT      4
#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK       0x1
#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT      5
#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT       6
        u8 flags1;
#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT       0
#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT       2
#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT       4
#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT       6
        u8 flags2;
#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT       0
#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT       2
#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT       4
#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT       6
        u8 flags3;
#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK        0x3
#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT       0
#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK       0x3
#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT      2
#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT     4
#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT     5
#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     6
#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT     7
        u8 flags4;
#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT     0
#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT     1
#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT     2
#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT     3
#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT     4
#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK      0x1
#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT     5
#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK     0x1
#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT    6
#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT   7
        u8 flags5;
#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT   0
#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT   1
#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT   2
#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT   3
#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT   4
#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT   5
#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT   6
#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK    0x1
#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT   7
        __le32 reg0;
        __le32 reg1;
        __le32 reg2;
        __le32 reg3;
        __le32 reg4;
        __le32 reg5;
        __le32 reg6;
        __le32 reg7;
        __le32 reg8;
        u8 byte2;
        u8 byte3;
        __le16 word0;
        u8 byte4;
        u8 byte5;
        __le16 word1;
        __le16 word2;
        __le16 word3;
        __le32 reg9;
        __le32 reg10;
};

struct ustorm_core_conn_ag_ctx {
        u8 reserved;
        u8 byte1;
        u8 flags0;
#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK       0x1
#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT      0
#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK       0x1
#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT      1
#define USTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT       2
#define USTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT       4
#define USTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT       6
        u8 flags1;
#define USTORM_CORE_CONN_AG_CTX_CF3_MASK        0x3
#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT       0
#define USTORM_CORE_CONN_AG_CTX_CF4_MASK        0x3
#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT       2
#define USTORM_CORE_CONN_AG_CTX_CF5_MASK        0x3
#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT       4
#define USTORM_CORE_CONN_AG_CTX_CF6_MASK        0x3
#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT       6
        u8 flags2;
#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK      0x1
#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT     0
#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK      0x1
#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT     1
#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     2
#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK      0x1
#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT     3
#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK      0x1
#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT     4
#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK      0x1
#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT     5
#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK      0x1
#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT     6
#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT   7
        u8 flags3;
#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT   0
#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT   1
#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT   2
#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT   3
#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT   4
#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT   5
#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT   6
#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK    0x1
#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT   7
        u8 byte2;
        u8 byte3;
        __le16 word0;
        __le16 word1;
        __le32 rx_producers;
        __le32 reg1;
        __le32 reg2;
        __le32 reg3;
        __le16 word2;
        __le16 word3;
};

/* The core storm context for the Mstorm */
struct mstorm_core_conn_st_ctx {
        __le32 reserved[24];
};

/* The core storm context for the Ustorm */
struct ustorm_core_conn_st_ctx {
        __le32 reserved[4];
};

/* core connection context */
struct core_conn_context {
        struct ystorm_core_conn_st_ctx ystorm_st_context;
        struct regpair ystorm_st_padding[2];
        struct pstorm_core_conn_st_ctx pstorm_st_context;
        struct regpair pstorm_st_padding[2];
        struct xstorm_core_conn_st_ctx xstorm_st_context;
        struct xstorm_core_conn_ag_ctx xstorm_ag_context;
        struct tstorm_core_conn_ag_ctx tstorm_ag_context;
        struct ustorm_core_conn_ag_ctx ustorm_ag_context;
        struct mstorm_core_conn_st_ctx mstorm_st_context;
        struct ustorm_core_conn_st_ctx ustorm_st_context;
        struct regpair ustorm_st_padding[2];
};

enum core_error_handle {
        LL2_DROP_PACKET,
        LL2_DO_NOTHING,
        LL2_ASSERT,
        MAX_CORE_ERROR_HANDLE
};

enum core_event_opcode {
        CORE_EVENT_TX_QUEUE_START,
        CORE_EVENT_TX_QUEUE_STOP,
        CORE_EVENT_RX_QUEUE_START,
        CORE_EVENT_RX_QUEUE_STOP,
        MAX_CORE_EVENT_OPCODE
};

enum core_l4_pseudo_checksum_mode {
        CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
        CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
        MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
};

struct core_ll2_port_stats {
        struct regpair gsi_invalid_hdr;
        struct regpair gsi_invalid_pkt_length;
        struct regpair gsi_unsupported_pkt_typ;
        struct regpair gsi_crcchksm_error;
};

struct core_ll2_pstorm_per_queue_stat {
        struct regpair sent_ucast_bytes;
        struct regpair sent_mcast_bytes;
        struct regpair sent_bcast_bytes;
        struct regpair sent_ucast_pkts;
        struct regpair sent_mcast_pkts;
        struct regpair sent_bcast_pkts;
};

struct core_ll2_rx_prod {
        __le16 bd_prod;
        __le16 cqe_prod;
        __le32 reserved;
};

struct core_ll2_tstorm_per_queue_stat {
        struct regpair packet_too_big_discard;
        struct regpair no_buff_discard;
};

struct core_ll2_ustorm_per_queue_stat {
        struct regpair rcv_ucast_bytes;
        struct regpair rcv_mcast_bytes;
        struct regpair rcv_bcast_bytes;
        struct regpair rcv_ucast_pkts;
        struct regpair rcv_mcast_pkts;
        struct regpair rcv_bcast_pkts;
};

enum core_ramrod_cmd_id {
        CORE_RAMROD_UNUSED,
        CORE_RAMROD_RX_QUEUE_START,
        CORE_RAMROD_TX_QUEUE_START,
        CORE_RAMROD_RX_QUEUE_STOP,
        CORE_RAMROD_TX_QUEUE_STOP,
        MAX_CORE_RAMROD_CMD_ID
};

enum core_roce_flavor_type {
        CORE_ROCE,
        CORE_RROCE,
        MAX_CORE_ROCE_FLAVOR_TYPE
};

struct core_rx_action_on_error {
        u8 error_type;
#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK     0x3
#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK    0x3
#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT   2
#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK   0xF
#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT  4
};

struct core_rx_bd {
        struct regpair addr;
        __le16 reserved[4];
};

struct core_rx_bd_with_buff_len {
        struct regpair addr;
        __le16 buff_length;
        __le16 reserved[3];
};

union core_rx_bd_union {
        struct core_rx_bd rx_bd;
        struct core_rx_bd_with_buff_len rx_bd_with_len;
};

struct core_rx_cqe_opaque_data {
        __le32 data[2];
};

enum core_rx_cqe_type {
        CORE_RX_CQE_ILLIGAL_TYPE,
        CORE_RX_CQE_TYPE_REGULAR,
        CORE_RX_CQE_TYPE_GSI_OFFLOAD,
        CORE_RX_CQE_TYPE_SLOW_PATH,
        MAX_CORE_RX_CQE_TYPE
};

struct core_rx_fast_path_cqe {
        u8 type;
        u8 placement_offset;
        struct parsing_and_err_flags parse_flags;
        __le16 packet_length;
        __le16 vlan;
        struct core_rx_cqe_opaque_data opaque_data;
        __le32 reserved[4];
};

struct core_rx_gsi_offload_cqe {
        u8 type;
        u8 data_length_error;
        struct parsing_and_err_flags parse_flags;
        __le16 data_length;
        __le16 vlan;
        __le32 src_mac_addrhi;
        __le16 src_mac_addrlo;
        u8 reserved1[2];
        __le32 gid_dst[4];
};

struct core_rx_slow_path_cqe {
        u8 type;
        u8 ramrod_cmd_id;
        __le16 echo;
        __le32 reserved1[7];
};

union core_rx_cqe_union {
        struct core_rx_fast_path_cqe rx_cqe_fp;
        struct core_rx_gsi_offload_cqe rx_cqe_gsi;
        struct core_rx_slow_path_cqe rx_cqe_sp;
};

struct core_rx_start_ramrod_data {
        struct regpair bd_base;
        struct regpair cqe_pbl_addr;
        __le16 mtu;
        __le16 sb_id;
        u8 sb_index;
        u8 complete_cqe_flg;
        u8 complete_event_flg;
        u8 drop_ttl0_flg;
        __le16 num_of_pbl_pages;
        u8 inner_vlan_removal_en;
        u8 queue_id;
        u8 main_func_queue;
        u8 mf_si_bcast_accept_all;
        u8 mf_si_mcast_accept_all;
        struct core_rx_action_on_error action_on_error;
        u8 gsi_offload_flag;
        u8 reserved[7];
};

struct core_rx_stop_ramrod_data {
        u8 complete_cqe_flg;
        u8 complete_event_flg;
        u8 queue_id;
        u8 reserved1;
        __le16 reserved2[2];
};

struct core_tx_bd_flags {
        u8 as_bitfield;
#define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_MASK   0x1
#define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_SHIFT  0
#define CORE_TX_BD_FLAGS_VLAN_INSERTION_MASK    0x1
#define CORE_TX_BD_FLAGS_VLAN_INSERTION_SHIFT   1
#define CORE_TX_BD_FLAGS_START_BD_MASK  0x1
#define CORE_TX_BD_FLAGS_START_BD_SHIFT 2
#define CORE_TX_BD_FLAGS_IP_CSUM_MASK   0x1
#define CORE_TX_BD_FLAGS_IP_CSUM_SHIFT  3
#define CORE_TX_BD_FLAGS_L4_CSUM_MASK   0x1
#define CORE_TX_BD_FLAGS_L4_CSUM_SHIFT  4
#define CORE_TX_BD_FLAGS_IPV6_EXT_MASK  0x1
#define CORE_TX_BD_FLAGS_IPV6_EXT_SHIFT 5
#define CORE_TX_BD_FLAGS_L4_PROTOCOL_MASK       0x1
#define CORE_TX_BD_FLAGS_L4_PROTOCOL_SHIFT      6
#define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_MASK       0x1
#define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_SHIFT 7
};

struct core_tx_bd {
        struct regpair addr;
        __le16 nbytes;
        __le16 nw_vlan_or_lb_echo;
        u8 bitfield0;
#define CORE_TX_BD_NBDS_MASK    0xF
#define CORE_TX_BD_NBDS_SHIFT   0
#define CORE_TX_BD_ROCE_FLAV_MASK       0x1
#define CORE_TX_BD_ROCE_FLAV_SHIFT      4
#define CORE_TX_BD_RESERVED0_MASK       0x7
#define CORE_TX_BD_RESERVED0_SHIFT      5
        struct core_tx_bd_flags bd_flags;
        __le16 bitfield1;
#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
#define CORE_TX_BD_TX_DST_MASK  0x1
#define CORE_TX_BD_TX_DST_SHIFT 14
#define CORE_TX_BD_RESERVED1_MASK       0x1
#define CORE_TX_BD_RESERVED1_SHIFT      15
};

enum core_tx_dest {
        CORE_TX_DEST_NW,
        CORE_TX_DEST_LB,
        MAX_CORE_TX_DEST
};

struct core_tx_start_ramrod_data {
        struct regpair pbl_base_addr;
        __le16 mtu;
        __le16 sb_id;
        u8 sb_index;
        u8 stats_en;
        u8 stats_id;
        u8 conn_type;
        __le16 pbl_size;
        __le16 qm_pq_id;
        u8 gsi_offload_flag;
        u8 resrved[3];
};

struct core_tx_stop_ramrod_data {
        __le32 reserved0[2];
};

struct eth_mstorm_per_pf_stat {
        struct regpair gre_discard_pkts;
        struct regpair vxlan_discard_pkts;
        struct regpair geneve_discard_pkts;
        struct regpair lb_discard_pkts;
};

struct eth_mstorm_per_queue_stat {
        struct regpair ttl0_discard;
        struct regpair packet_too_big_discard;
        struct regpair no_buff_discard;
        struct regpair not_active_discard;
        struct regpair tpa_coalesced_pkts;
        struct regpair tpa_coalesced_events;
        struct regpair tpa_aborts_num;
        struct regpair tpa_coalesced_bytes;
};

/* Ethernet TX Per PF */
struct eth_pstorm_per_pf_stat {
        struct regpair sent_lb_ucast_bytes;
        struct regpair sent_lb_mcast_bytes;
        struct regpair sent_lb_bcast_bytes;
        struct regpair sent_lb_ucast_pkts;
        struct regpair sent_lb_mcast_pkts;
        struct regpair sent_lb_bcast_pkts;
        struct regpair sent_gre_bytes;
        struct regpair sent_vxlan_bytes;
        struct regpair sent_geneve_bytes;
        struct regpair sent_gre_pkts;
        struct regpair sent_vxlan_pkts;
        struct regpair sent_geneve_pkts;
        struct regpair gre_drop_pkts;
        struct regpair vxlan_drop_pkts;
        struct regpair geneve_drop_pkts;
};

/* Ethernet TX Per Queue Stats */
struct eth_pstorm_per_queue_stat {
        struct regpair sent_ucast_bytes;
        struct regpair sent_mcast_bytes;
        struct regpair sent_bcast_bytes;
        struct regpair sent_ucast_pkts;
        struct regpair sent_mcast_pkts;
        struct regpair sent_bcast_pkts;
        struct regpair error_drop_pkts;
};

/* ETH Rx producers data */
struct eth_rx_rate_limit {
        __le16 mult;
        __le16 cnst;
        u8 add_sub_cnst;
        u8 reserved0;
        __le16 reserved1;
};

struct eth_ustorm_per_pf_stat {
        struct regpair rcv_lb_ucast_bytes;
        struct regpair rcv_lb_mcast_bytes;
        struct regpair rcv_lb_bcast_bytes;
        struct regpair rcv_lb_ucast_pkts;
        struct regpair rcv_lb_mcast_pkts;
        struct regpair rcv_lb_bcast_pkts;
        struct regpair rcv_gre_bytes;
        struct regpair rcv_vxlan_bytes;
        struct regpair rcv_geneve_bytes;
        struct regpair rcv_gre_pkts;
        struct regpair rcv_vxlan_pkts;
        struct regpair rcv_geneve_pkts;
};

struct eth_ustorm_per_queue_stat {
        struct regpair rcv_ucast_bytes;
        struct regpair rcv_mcast_bytes;
        struct regpair rcv_bcast_bytes;
        struct regpair rcv_ucast_pkts;
        struct regpair rcv_mcast_pkts;
        struct regpair rcv_bcast_pkts;
};

/* Event Ring Next Page Address */
struct event_ring_next_addr {
        struct regpair addr;
        __le32 reserved[2];
};

/* Event Ring Element */
union event_ring_element {
        struct event_ring_entry entry;
        struct event_ring_next_addr next_addr;
};

/* Major and Minor hsi Versions */
struct hsi_fp_ver_struct {
        u8 minor_ver_arr[2];
        u8 major_ver_arr[2];
};

/* Mstorm non-triggering VF zone */
enum malicious_vf_error_id {
        MALICIOUS_VF_NO_ERROR,
        VF_PF_CHANNEL_NOT_READY,
        VF_ZONE_MSG_NOT_VALID,
        VF_ZONE_FUNC_NOT_ENABLED,
        ETH_PACKET_TOO_SMALL,
        ETH_ILLEGAL_VLAN_MODE,
        ETH_MTU_VIOLATION,
        ETH_ILLEGAL_INBAND_TAGS,
        ETH_VLAN_INSERT_AND_INBAND_VLAN,
        ETH_ILLEGAL_NBDS,
        ETH_FIRST_BD_WO_SOP,
        ETH_INSUFFICIENT_BDS,
        ETH_ILLEGAL_LSO_HDR_NBDS,
        ETH_ILLEGAL_LSO_MSS,
        ETH_ZERO_SIZE_BD,
        ETH_ILLEGAL_LSO_HDR_LEN,
        ETH_INSUFFICIENT_PAYLOAD,
        ETH_EDPM_OUT_OF_SYNC,
        ETH_TUNN_IPV6_EXT_NBD_ERR,
        ETH_CONTROL_PACKET_VIOLATION,
        MAX_MALICIOUS_VF_ERROR_ID
};

struct mstorm_non_trigger_vf_zone {
        struct eth_mstorm_per_queue_stat eth_queue_stat;
        struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
};

/* Mstorm VF zone */
struct mstorm_vf_zone {
        struct mstorm_non_trigger_vf_zone non_trigger;

};

/* personality per PF */
enum personality_type {
        BAD_PERSONALITY_TYP,
        PERSONALITY_ISCSI,
        PERSONALITY_FCOE,
        PERSONALITY_RDMA_AND_ETH,
        PERSONALITY_RESERVED3,
        PERSONALITY_CORE,
        PERSONALITY_ETH,
        PERSONALITY_RESERVED4,
        MAX_PERSONALITY_TYPE
};

/* tunnel configuration */
struct pf_start_tunnel_config {
        u8 set_vxlan_udp_port_flg;
        u8 set_geneve_udp_port_flg;
        u8 tx_enable_vxlan;
        u8 tx_enable_l2geneve;
        u8 tx_enable_ipgeneve;
        u8 tx_enable_l2gre;
        u8 tx_enable_ipgre;
        u8 tunnel_clss_vxlan;
        u8 tunnel_clss_l2geneve;
        u8 tunnel_clss_ipgeneve;
        u8 tunnel_clss_l2gre;
        u8 tunnel_clss_ipgre;
        __le16 vxlan_udp_port;
        __le16 geneve_udp_port;
};

/* Ramrod data for PF start ramrod */
struct pf_start_ramrod_data {
        struct regpair event_ring_pbl_addr;
        struct regpair consolid_q_pbl_addr;
        struct pf_start_tunnel_config tunnel_config;
        __le16 event_ring_sb_id;
        u8 base_vf_id;
        u8 num_vfs;
        u8 event_ring_num_pages;
        u8 event_ring_sb_index;
        u8 path_id;
        u8 warning_as_error;
        u8 dont_log_ramrods;
        u8 personality;
        __le16 log_type_mask;
        u8 mf_mode;
        u8 integ_phase;
        u8 allow_npar_tx_switching;
        u8 inner_to_outer_pri_map[8];
        u8 pri_map_valid;
        __le32 outer_tag;
        struct hsi_fp_ver_struct hsi_fp_ver;

};

struct protocol_dcb_data {
        u8 dcb_enable_flag;
        u8 reserved_a;
        u8 dcb_priority;
        u8 dcb_tc;
        u8 reserved_b;
        u8 reserved0;

};

struct pf_update_tunnel_config {
        u8 update_rx_pf_clss;
        u8 update_rx_def_ucast_clss;
        u8 update_rx_def_non_ucast_clss;
        u8 update_tx_pf_clss;
        u8 set_vxlan_udp_port_flg;
        u8 set_geneve_udp_port_flg;
        u8 tx_enable_vxlan;
        u8 tx_enable_l2geneve;
        u8 tx_enable_ipgeneve;
        u8 tx_enable_l2gre;
        u8 tx_enable_ipgre;
        u8 tunnel_clss_vxlan;
        u8 tunnel_clss_l2geneve;
        u8 tunnel_clss_ipgeneve;
        u8 tunnel_clss_l2gre;
        u8 tunnel_clss_ipgre;
        __le16 vxlan_udp_port;
        __le16 geneve_udp_port;
        __le16 reserved[2];
};

struct pf_update_ramrod_data {
        u8 pf_id;
        u8 update_eth_dcb_data_flag;
        u8 update_fcoe_dcb_data_flag;
        u8 update_iscsi_dcb_data_flag;
        u8 update_roce_dcb_data_flag;
        u8 update_rroce_dcb_data_flag;
        u8 update_iwarp_dcb_data_flag;
        u8 update_mf_vlan_flag;
        struct protocol_dcb_data eth_dcb_data;
        struct protocol_dcb_data fcoe_dcb_data;
        struct protocol_dcb_data iscsi_dcb_data;
        struct protocol_dcb_data roce_dcb_data;
        struct protocol_dcb_data rroce_dcb_data;
        struct protocol_dcb_data iwarp_dcb_data;
        __le16 mf_vlan;
        __le16 reserved;
        struct pf_update_tunnel_config tunnel_config;
};

/* Ports mode */
enum ports_mode {
        ENGX2_PORTX1,
        ENGX2_PORTX2,
        ENGX1_PORTX1,
        ENGX1_PORTX2,
        ENGX1_PORTX4,
        MAX_PORTS_MODE
};

/* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
enum protocol_version_array_key {
        ETH_VER_KEY = 0,
        ROCE_VER_KEY,
        MAX_PROTOCOL_VERSION_ARRAY_KEY
};

struct rdma_sent_stats {
        struct regpair sent_bytes;
        struct regpair sent_pkts;
};

struct pstorm_non_trigger_vf_zone {
        struct eth_pstorm_per_queue_stat eth_queue_stat;
        struct rdma_sent_stats rdma_stats;
};

/* Pstorm VF zone */
struct pstorm_vf_zone {
        struct pstorm_non_trigger_vf_zone non_trigger;
        struct regpair reserved[7];
};

/* Ramrod Header of SPQE */
struct ramrod_header {
        __le32 cid;
        u8 cmd_id;
        u8 protocol_id;
        __le16 echo;
};

struct rdma_rcv_stats {
        struct regpair rcv_bytes;
        struct regpair rcv_pkts;
};

struct slow_path_element {
        struct ramrod_header hdr;
        struct regpair data_ptr;
};

/* Tstorm non-triggering VF zone */
struct tstorm_non_trigger_vf_zone {
        struct rdma_rcv_stats rdma_stats;
};

struct tstorm_per_port_stat {
        struct regpair trunc_error_discard;
        struct regpair mac_error_discard;
        struct regpair mftag_filter_discard;
        struct regpair eth_mac_filter_discard;
        struct regpair ll2_mac_filter_discard;
        struct regpair ll2_conn_disabled_discard;
        struct regpair iscsi_irregular_pkt;
        struct regpair reserved;
        struct regpair roce_irregular_pkt;
        struct regpair eth_irregular_pkt;
        struct regpair reserved1;
        struct regpair preroce_irregular_pkt;
        struct regpair eth_gre_tunn_filter_discard;
        struct regpair eth_vxlan_tunn_filter_discard;
        struct regpair eth_geneve_tunn_filter_discard;
};

/* Tstorm VF zone */
struct tstorm_vf_zone {
        struct tstorm_non_trigger_vf_zone non_trigger;
};

/* Tunnel classification scheme */
enum tunnel_clss {
        TUNNEL_CLSS_MAC_VLAN = 0,
        TUNNEL_CLSS_MAC_VNI,
        TUNNEL_CLSS_INNER_MAC_VLAN,
        TUNNEL_CLSS_INNER_MAC_VNI,
        TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
        MAX_TUNNEL_CLSS
};

/* Ustorm non-triggering VF zone */
struct ustorm_non_trigger_vf_zone {
        struct eth_ustorm_per_queue_stat eth_queue_stat;
        struct regpair vf_pf_msg_addr;
};

/* Ustorm triggering VF zone */
struct ustorm_trigger_vf_zone {
        u8 vf_pf_msg_valid;
        u8 reserved[7];
};

/* Ustorm VF zone */
struct ustorm_vf_zone {
        struct ustorm_non_trigger_vf_zone non_trigger;
        struct ustorm_trigger_vf_zone trigger;
};

/* VF-PF channel data */
struct vf_pf_channel_data {
        __le32 ready;
        u8 valid;
        u8 reserved0;
        __le16 reserved1;
};

/* Ramrod data for VF start ramrod */
struct vf_start_ramrod_data {
        u8 vf_id;
        u8 enable_flr_ack;
        __le16 opaque_fid;
        u8 personality;
        u8 reserved[7];
        struct hsi_fp_ver_struct hsi_fp_ver;

};

/* Ramrod data for VF start ramrod */
struct vf_stop_ramrod_data {
        u8 vf_id;
        u8 reserved0;
        __le16 reserved1;
        __le32 reserved2;
};

enum vf_zone_size_mode {
        VF_ZONE_SIZE_MODE_DEFAULT,
        VF_ZONE_SIZE_MODE_DOUBLE,
        VF_ZONE_SIZE_MODE_QUAD,
        MAX_VF_ZONE_SIZE_MODE
};

struct atten_status_block {
        __le32 atten_bits;
        __le32 atten_ack;
        __le16 reserved0;
        __le16 sb_index;
        __le32 reserved1;
};

enum command_type_bit {
        IGU_COMMAND_TYPE_NOP = 0,
        IGU_COMMAND_TYPE_SET = 1,
        MAX_COMMAND_TYPE_BIT
};

/* DMAE command */
struct dmae_cmd {
        __le32 opcode;
#define DMAE_CMD_SRC_MASK               0x1
#define DMAE_CMD_SRC_SHIFT              0
#define DMAE_CMD_DST_MASK               0x3
#define DMAE_CMD_DST_SHIFT              1
#define DMAE_CMD_C_DST_MASK             0x1
#define DMAE_CMD_C_DST_SHIFT            3
#define DMAE_CMD_CRC_RESET_MASK         0x1
#define DMAE_CMD_CRC_RESET_SHIFT        4
#define DMAE_CMD_SRC_ADDR_RESET_MASK    0x1
#define DMAE_CMD_SRC_ADDR_RESET_SHIFT   5
#define DMAE_CMD_DST_ADDR_RESET_MASK    0x1
#define DMAE_CMD_DST_ADDR_RESET_SHIFT   6
#define DMAE_CMD_COMP_FUNC_MASK         0x1
#define DMAE_CMD_COMP_FUNC_SHIFT        7
#define DMAE_CMD_COMP_WORD_EN_MASK      0x1
#define DMAE_CMD_COMP_WORD_EN_SHIFT     8
#define DMAE_CMD_COMP_CRC_EN_MASK       0x1
#define DMAE_CMD_COMP_CRC_EN_SHIFT      9
#define DMAE_CMD_COMP_CRC_OFFSET_MASK   0x7
#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
#define DMAE_CMD_RESERVED1_MASK         0x1
#define DMAE_CMD_RESERVED1_SHIFT        13
#define DMAE_CMD_ENDIANITY_MODE_MASK    0x3
#define DMAE_CMD_ENDIANITY_MODE_SHIFT   14
#define DMAE_CMD_ERR_HANDLING_MASK      0x3
#define DMAE_CMD_ERR_HANDLING_SHIFT     16
#define DMAE_CMD_PORT_ID_MASK           0x3
#define DMAE_CMD_PORT_ID_SHIFT          18
#define DMAE_CMD_SRC_PF_ID_MASK         0xF
#define DMAE_CMD_SRC_PF_ID_SHIFT        20
#define DMAE_CMD_DST_PF_ID_MASK         0xF
#define DMAE_CMD_DST_PF_ID_SHIFT        24
#define DMAE_CMD_SRC_VF_ID_VALID_MASK   0x1
#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
#define DMAE_CMD_DST_VF_ID_VALID_MASK   0x1
#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
#define DMAE_CMD_RESERVED2_MASK         0x3
#define DMAE_CMD_RESERVED2_SHIFT        30
        __le32 src_addr_lo;
        __le32 src_addr_hi;
        __le32 dst_addr_lo;
        __le32 dst_addr_hi;
        __le16 length_dw;
        __le16 opcode_b;
#define DMAE_CMD_SRC_VF_ID_MASK         0xFF
#define DMAE_CMD_SRC_VF_ID_SHIFT        0
#define DMAE_CMD_DST_VF_ID_MASK         0xFF
#define DMAE_CMD_DST_VF_ID_SHIFT        8
        __le32 comp_addr_lo;
        __le32 comp_addr_hi;
        __le32 comp_val;
        __le32 crc32;
        __le32 crc_32_c;
        __le16 crc16;
        __le16 crc16_c;
        __le16 crc10;
        __le16 reserved;
        __le16 xsum16;
        __le16 xsum8;
};

enum dmae_cmd_comp_crc_en_enum {
        dmae_cmd_comp_crc_disabled,
        dmae_cmd_comp_crc_enabled,
        MAX_DMAE_CMD_COMP_CRC_EN_ENUM
};

enum dmae_cmd_comp_func_enum {
        dmae_cmd_comp_func_to_src,
        dmae_cmd_comp_func_to_dst,
        MAX_DMAE_CMD_COMP_FUNC_ENUM
};

enum dmae_cmd_comp_word_en_enum {
        dmae_cmd_comp_word_disabled,
        dmae_cmd_comp_word_enabled,
        MAX_DMAE_CMD_COMP_WORD_EN_ENUM
};

enum dmae_cmd_c_dst_enum {
        dmae_cmd_c_dst_pcie,
        dmae_cmd_c_dst_grc,
        MAX_DMAE_CMD_C_DST_ENUM
};

enum dmae_cmd_dst_enum {
        dmae_cmd_dst_none_0,
        dmae_cmd_dst_pcie,
        dmae_cmd_dst_grc,
        dmae_cmd_dst_none_3,
        MAX_DMAE_CMD_DST_ENUM
};

enum dmae_cmd_error_handling_enum {
        dmae_cmd_error_handling_send_regular_comp,
        dmae_cmd_error_handling_send_comp_with_err,
        dmae_cmd_error_handling_dont_send_comp,
        MAX_DMAE_CMD_ERROR_HANDLING_ENUM
};

enum dmae_cmd_src_enum {
        dmae_cmd_src_pcie,
        dmae_cmd_src_grc,
        MAX_DMAE_CMD_SRC_ENUM
};

/* IGU cleanup command */
struct igu_cleanup {
        __le32 sb_id_and_flags;
#define IGU_CLEANUP_RESERVED0_MASK      0x7FFFFFF
#define IGU_CLEANUP_RESERVED0_SHIFT     0
#define IGU_CLEANUP_CLEANUP_SET_MASK    0x1
#define IGU_CLEANUP_CLEANUP_SET_SHIFT   27
#define IGU_CLEANUP_CLEANUP_TYPE_MASK   0x7
#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT  28
#define IGU_CLEANUP_COMMAND_TYPE_MASK   0x1
#define IGU_CLEANUP_COMMAND_TYPE_SHIFT  31
        __le32 reserved1;
};

/* IGU firmware driver command */
union igu_command {
        struct igu_prod_cons_update prod_cons_update;
        struct igu_cleanup cleanup;
};

/* IGU firmware driver command */
struct igu_command_reg_ctrl {
        __le16 opaque_fid;
        __le16 igu_command_reg_ctrl_fields;
#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK  0xFFF
#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
#define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
};

/* IGU mapping line structure */
struct igu_mapping_line {
        __le32 igu_mapping_line_fields;
#define IGU_MAPPING_LINE_VALID_MASK             0x1
#define IGU_MAPPING_LINE_VALID_SHIFT            0
#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK     0xFF
#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT    1
#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK   0xFF
#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT  9
#define IGU_MAPPING_LINE_PF_VALID_MASK          0x1
#define IGU_MAPPING_LINE_PF_VALID_SHIFT         17
#define IGU_MAPPING_LINE_IPS_GROUP_MASK         0x3F
#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT        18
#define IGU_MAPPING_LINE_RESERVED_MASK          0xFF
#define IGU_MAPPING_LINE_RESERVED_SHIFT         24
};

/* IGU MSIX line structure */
struct igu_msix_vector {
        struct regpair address;
        __le32 data;
        __le32 msix_vector_fields;
#define IGU_MSIX_VECTOR_MASK_BIT_MASK           0x1
#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT          0
#define IGU_MSIX_VECTOR_RESERVED0_MASK          0x7FFF
#define IGU_MSIX_VECTOR_RESERVED0_SHIFT         1
#define IGU_MSIX_VECTOR_STEERING_TAG_MASK       0xFF
#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT      16
#define IGU_MSIX_VECTOR_RESERVED1_MASK          0xFF
#define IGU_MSIX_VECTOR_RESERVED1_SHIFT         24
};

struct mstorm_core_conn_ag_ctx {
        u8 byte0;
        u8 byte1;
        u8 flags0;
#define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK       0x1
#define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT      0
#define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK       0x1
#define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT      1
#define MSTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
#define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT       2
#define MSTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
#define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT       4
#define MSTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
#define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT       6
        u8 flags1;
#define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK      0x1
#define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT     0
#define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK      0x1
#define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT     1
#define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
#define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     2
#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK    0x1
#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT   3
#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK    0x1
#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT   4
#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK    0x1
#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT   5
#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK    0x1
#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT   6
#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK    0x1
#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT   7
        __le16 word0;
        __le16 word1;
        __le32 reg0;
        __le32 reg1;
};

/* per encapsulation type enabling flags */
struct prs_reg_encapsulation_type_en {
        u8 flags;
#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK          0x1
#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT         0
#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK           0x1
#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT          1
#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK                 0x1
#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT                2
#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK                 0x1
#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT                3
#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK       0x1
#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT      4
#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK        0x1
#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT       5
#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                     0x3
#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT                    6
};

enum pxp_tph_st_hint {
        TPH_ST_HINT_BIDIR,
        TPH_ST_HINT_REQUESTER,
        TPH_ST_HINT_TARGET,
        TPH_ST_HINT_TARGET_PRIO,
        MAX_PXP_TPH_ST_HINT
};

/* QM hardware structure of enable bypass credit mask */
struct qm_rf_bypass_mask {
        u8 flags;
#define QM_RF_BYPASS_MASK_LINEVOQ_MASK          0x1
#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT         0
#define QM_RF_BYPASS_MASK_RESERVED0_MASK        0x1
#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT       1
#define QM_RF_BYPASS_MASK_PFWFQ_MASK            0x1
#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT           2
#define QM_RF_BYPASS_MASK_VPWFQ_MASK            0x1
#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT           3
#define QM_RF_BYPASS_MASK_PFRL_MASK             0x1
#define QM_RF_BYPASS_MASK_PFRL_SHIFT            4
#define QM_RF_BYPASS_MASK_VPQCNRL_MASK          0x1
#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT         5
#define QM_RF_BYPASS_MASK_FWPAUSE_MASK          0x1
#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT         6
#define QM_RF_BYPASS_MASK_RESERVED1_MASK        0x1
#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT       7
};

/* QM hardware structure of opportunistic credit mask */
struct qm_rf_opportunistic_mask {
        __le16 flags;
#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK           0x1
#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT          0
#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK           0x1
#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT          1
#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK             0x1
#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT            2
#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK             0x1
#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT            3
#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK              0x1
#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT             4
#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK           0x1
#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT          5
#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK           0x1
#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT          6
#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK         0x1
#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT        7
#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK        0x1
#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT       8
#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK         0x7F
#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT        9
};

/* QM hardware structure of QM map memory */
struct qm_rf_pq_map {
        __le32 reg;
#define QM_RF_PQ_MAP_PQ_VALID_MASK              0x1
#define QM_RF_PQ_MAP_PQ_VALID_SHIFT             0
#define QM_RF_PQ_MAP_RL_ID_MASK                 0xFF
#define QM_RF_PQ_MAP_RL_ID_SHIFT                1
#define QM_RF_PQ_MAP_VP_PQ_ID_MASK              0x1FF
#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT             9
#define QM_RF_PQ_MAP_VOQ_MASK                   0x1F
#define QM_RF_PQ_MAP_VOQ_SHIFT                  18
#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK      0x3
#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT     23
#define QM_RF_PQ_MAP_RL_VALID_MASK              0x1
#define QM_RF_PQ_MAP_RL_VALID_SHIFT             25
#define QM_RF_PQ_MAP_RESERVED_MASK              0x3F
#define QM_RF_PQ_MAP_RESERVED_SHIFT             26
};

/* Completion params for aggregated interrupt completion */
struct sdm_agg_int_comp_params {
        __le16 params;
#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK      0x3F
#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT     0
#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK  0x1
#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK     0x1FF
#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT    7
};

/* SDM operation gen command (generate aggregative interrupt) */
struct sdm_op_gen {
        __le32 command;
#define SDM_OP_GEN_COMP_PARAM_MASK      0xFFFF
#define SDM_OP_GEN_COMP_PARAM_SHIFT     0
#define SDM_OP_GEN_COMP_TYPE_MASK       0xF
#define SDM_OP_GEN_COMP_TYPE_SHIFT      16
#define SDM_OP_GEN_RESERVED_MASK        0xFFF
#define SDM_OP_GEN_RESERVED_SHIFT       20
};

struct ystorm_core_conn_ag_ctx {
        u8 byte0;
        u8 byte1;
        u8 flags0;
#define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK       0x1
#define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT      0
#define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK       0x1
#define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT      1
#define YSTORM_CORE_CONN_AG_CTX_CF0_MASK        0x3
#define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT       2
#define YSTORM_CORE_CONN_AG_CTX_CF1_MASK        0x3
#define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT       4
#define YSTORM_CORE_CONN_AG_CTX_CF2_MASK        0x3
#define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT       6
        u8 flags1;
#define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK      0x1
#define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT     0
#define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK      0x1
#define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT     1
#define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK      0x1
#define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT     2
#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK    0x1
#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT   3
#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK    0x1
#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT   4
#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK    0x1
#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT   5
#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK    0x1
#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT   6
#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK    0x1
#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT   7
        u8 byte2;
        u8 byte3;
        __le16 word0;
        __le32 reg0;
        __le32 reg1;
        __le16 word1;
        __le16 word2;
        __le16 word3;
        __le16 word4;
        __le32 reg2;
        __le32 reg3;
};

/****************************************/
/* Debug Tools HSI constants and macros */
/****************************************/

enum block_addr {
        GRCBASE_GRC = 0x50000,
        GRCBASE_MISCS = 0x9000,
        GRCBASE_MISC = 0x8000,
        GRCBASE_DBU = 0xa000,
        GRCBASE_PGLUE_B = 0x2a8000,
        GRCBASE_CNIG = 0x218000,
        GRCBASE_CPMU = 0x30000,
        GRCBASE_NCSI = 0x40000,
        GRCBASE_OPTE = 0x53000,
        GRCBASE_BMB = 0x540000,
        GRCBASE_PCIE = 0x54000,
        GRCBASE_MCP = 0xe00000,
        GRCBASE_MCP2 = 0x52000,
        GRCBASE_PSWHST = 0x2a0000,
        GRCBASE_PSWHST2 = 0x29e000,
        GRCBASE_PSWRD = 0x29c000,
        GRCBASE_PSWRD2 = 0x29d000,
        GRCBASE_PSWWR = 0x29a000,
        GRCBASE_PSWWR2 = 0x29b000,
        GRCBASE_PSWRQ = 0x280000,
        GRCBASE_PSWRQ2 = 0x240000,
        GRCBASE_PGLCS = 0x0,
        GRCBASE_DMAE = 0xc000,
        GRCBASE_PTU = 0x560000,
        GRCBASE_TCM = 0x1180000,
        GRCBASE_MCM = 0x1200000,
        GRCBASE_UCM = 0x1280000,
        GRCBASE_XCM = 0x1000000,
        GRCBASE_YCM = 0x1080000,
        GRCBASE_PCM = 0x1100000,
        GRCBASE_QM = 0x2f0000,
        GRCBASE_TM = 0x2c0000,
        GRCBASE_DORQ = 0x100000,
        GRCBASE_BRB = 0x340000,
        GRCBASE_SRC = 0x238000,
        GRCBASE_PRS = 0x1f0000,
        GRCBASE_TSDM = 0xfb0000,
        GRCBASE_MSDM = 0xfc0000,
        GRCBASE_USDM = 0xfd0000,
        GRCBASE_XSDM = 0xf80000,
        GRCBASE_YSDM = 0xf90000,
        GRCBASE_PSDM = 0xfa0000,
        GRCBASE_TSEM = 0x1700000,
        GRCBASE_MSEM = 0x1800000,
        GRCBASE_USEM = 0x1900000,
        GRCBASE_XSEM = 0x1400000,
        GRCBASE_YSEM = 0x1500000,
        GRCBASE_PSEM = 0x1600000,
        GRCBASE_RSS = 0x238800,
        GRCBASE_TMLD = 0x4d0000,
        GRCBASE_MULD = 0x4e0000,
        GRCBASE_YULD = 0x4c8000,
        GRCBASE_XYLD = 0x4c0000,
        GRCBASE_PRM = 0x230000,
        GRCBASE_PBF_PB1 = 0xda0000,
        GRCBASE_PBF_PB2 = 0xda4000,
        GRCBASE_RPB = 0x23c000,
        GRCBASE_BTB = 0xdb0000,
        GRCBASE_PBF = 0xd80000,
        GRCBASE_RDIF = 0x300000,
        GRCBASE_TDIF = 0x310000,
        GRCBASE_CDU = 0x580000,
        GRCBASE_CCFC = 0x2e0000,
        GRCBASE_TCFC = 0x2d0000,
        GRCBASE_IGU = 0x180000,
        GRCBASE_CAU = 0x1c0000,
        GRCBASE_UMAC = 0x51000,
        GRCBASE_XMAC = 0x210000,
        GRCBASE_DBG = 0x10000,
        GRCBASE_NIG = 0x500000,
        GRCBASE_WOL = 0x600000,
        GRCBASE_BMBN = 0x610000,
        GRCBASE_IPC = 0x20000,
        GRCBASE_NWM = 0x800000,
        GRCBASE_NWS = 0x700000,
        GRCBASE_MS = 0x6a0000,
        GRCBASE_PHY_PCIE = 0x620000,
        GRCBASE_LED = 0x6b8000,
        GRCBASE_MISC_AEU = 0x8000,
        GRCBASE_BAR0_MAP = 0x1c00000,
        MAX_BLOCK_ADDR
};

enum block_id {
        BLOCK_GRC,
        BLOCK_MISCS,
        BLOCK_MISC,
        BLOCK_DBU,
        BLOCK_PGLUE_B,
        BLOCK_CNIG,
        BLOCK_CPMU,
        BLOCK_NCSI,
        BLOCK_OPTE,
        BLOCK_BMB,
        BLOCK_PCIE,
        BLOCK_MCP,
        BLOCK_MCP2,
        BLOCK_PSWHST,
        BLOCK_PSWHST2,
        BLOCK_PSWRD,
        BLOCK_PSWRD2,
        BLOCK_PSWWR,
        BLOCK_PSWWR2,
        BLOCK_PSWRQ,
        BLOCK_PSWRQ2,
        BLOCK_PGLCS,
        BLOCK_DMAE,
        BLOCK_PTU,
        BLOCK_TCM,
        BLOCK_MCM,
        BLOCK_UCM,
        BLOCK_XCM,
        BLOCK_YCM,
        BLOCK_PCM,
        BLOCK_QM,
        BLOCK_TM,
        BLOCK_DORQ,
        BLOCK_BRB,
        BLOCK_SRC,
        BLOCK_PRS,
        BLOCK_TSDM,
        BLOCK_MSDM,
        BLOCK_USDM,
        BLOCK_XSDM,
        BLOCK_YSDM,
        BLOCK_PSDM,
        BLOCK_TSEM,
        BLOCK_MSEM,
        BLOCK_USEM,
        BLOCK_XSEM,
        BLOCK_YSEM,
        BLOCK_PSEM,
        BLOCK_RSS,
        BLOCK_TMLD,
        BLOCK_MULD,
        BLOCK_YULD,
        BLOCK_XYLD,
        BLOCK_PRM,
        BLOCK_PBF_PB1,
        BLOCK_PBF_PB2,
        BLOCK_RPB,
        BLOCK_BTB,
        BLOCK_PBF,
        BLOCK_RDIF,
        BLOCK_TDIF,
        BLOCK_CDU,
        BLOCK_CCFC,
        BLOCK_TCFC,
        BLOCK_IGU,
        BLOCK_CAU,
        BLOCK_UMAC,
        BLOCK_XMAC,
        BLOCK_DBG,
        BLOCK_NIG,
        BLOCK_WOL,
        BLOCK_BMBN,
        BLOCK_IPC,
        BLOCK_NWM,
        BLOCK_NWS,
        BLOCK_MS,
        BLOCK_PHY_PCIE,
        BLOCK_LED,
        BLOCK_MISC_AEU,
        BLOCK_BAR0_MAP,
        MAX_BLOCK_ID
};

/* binary debug buffer types */
enum bin_dbg_buffer_type {
        BIN_BUF_DBG_MODE_TREE,
        BIN_BUF_DBG_DUMP_REG,
        BIN_BUF_DBG_DUMP_MEM,
        BIN_BUF_DBG_IDLE_CHK_REGS,
        BIN_BUF_DBG_IDLE_CHK_IMMS,
        BIN_BUF_DBG_IDLE_CHK_RULES,
        BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
        BIN_BUF_DBG_ATTN_BLOCKS,
        BIN_BUF_DBG_ATTN_REGS,
        BIN_BUF_DBG_ATTN_INDEXES,
        BIN_BUF_DBG_ATTN_NAME_OFFSETS,
        BIN_BUF_DBG_PARSING_STRINGS,
        MAX_BIN_DBG_BUFFER_TYPE
};


/* Attention bit mapping */
struct dbg_attn_bit_mapping {
        __le16 data;
#define DBG_ATTN_BIT_MAPPING_VAL_MASK                   0x7FFF
#define DBG_ATTN_BIT_MAPPING_VAL_SHIFT                  0
#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK     0x1
#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT    15
};

/* Attention block per-type data */
struct dbg_attn_block_type_data {
        __le16 names_offset;
        __le16 reserved1;
        u8 num_regs;
        u8 reserved2;
        __le16 regs_offset;
};

/* Block attentions */
struct dbg_attn_block {
        struct dbg_attn_block_type_data per_type_data[2];
};

/* Attention register result */
struct dbg_attn_reg_result {
        __le32 data;
#define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK    0xFFFFFF
#define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT   0
#define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_MASK   0xFF
#define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_SHIFT  24
        __le16 attn_idx_offset;
        __le16 reserved;
        __le32 sts_val;
        __le32 mask_val;
};

/* Attention block result */
struct dbg_attn_block_result {
        u8 block_id;
        u8 data;
#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK    0x3
#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT   0
#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK     0x3F
#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT    2
        __le16 names_offset;
        struct dbg_attn_reg_result reg_results[15];
};

/* mode header */
struct dbg_mode_hdr {
        __le16 data;
#define DBG_MODE_HDR_EVAL_MODE_MASK             0x1
#define DBG_MODE_HDR_EVAL_MODE_SHIFT            0
#define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK      0x7FFF
#define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT     1
};

/* Attention register */
struct dbg_attn_reg {
        struct dbg_mode_hdr mode;
        __le16 attn_idx_offset;
        __le32 data;
#define DBG_ATTN_REG_STS_ADDRESS_MASK   0xFFFFFF
#define DBG_ATTN_REG_STS_ADDRESS_SHIFT  0
#define DBG_ATTN_REG_NUM_ATTN_IDX_MASK  0xFF
#define DBG_ATTN_REG_NUM_ATTN_IDX_SHIFT 24
        __le32 sts_clr_address;
        __le32 mask_address;
};

/* attention types */
enum dbg_attn_type {
        ATTN_TYPE_INTERRUPT,
        ATTN_TYPE_PARITY,
        MAX_DBG_ATTN_TYPE
};

/* condition header for registers dump */
struct dbg_dump_cond_hdr {
        struct dbg_mode_hdr mode; /* Mode header */
        u8 block_id; /* block ID */
        u8 data_size; /* size in dwords of the data following this header */
};

/* memory data for registers dump */
struct dbg_dump_mem {
        __le32 dword0;
#define DBG_DUMP_MEM_ADDRESS_MASK       0xFFFFFF
#define DBG_DUMP_MEM_ADDRESS_SHIFT      0
#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK  0xFF
#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
        __le32 dword1;
#define DBG_DUMP_MEM_LENGTH_MASK        0xFFFFFF
#define DBG_DUMP_MEM_LENGTH_SHIFT       0
#define DBG_DUMP_MEM_RESERVED_MASK      0xFF
#define DBG_DUMP_MEM_RESERVED_SHIFT     24
};

/* register data for registers dump */
struct dbg_dump_reg {
        __le32 data;
#define DBG_DUMP_REG_ADDRESS_MASK  0xFFFFFF /* register address (in dwords) */
#define DBG_DUMP_REG_ADDRESS_SHIFT 0
#define DBG_DUMP_REG_LENGTH_MASK   0xFF /* register size (in dwords) */
#define DBG_DUMP_REG_LENGTH_SHIFT  24
};

/* split header for registers dump */
struct dbg_dump_split_hdr {
        __le32 hdr;
#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK      0xFFFFFF
#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT     0
#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK  0xFF
#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
};

/* condition header for idle check */
struct dbg_idle_chk_cond_hdr {
        struct dbg_mode_hdr mode; /* Mode header */
        __le16 data_size; /* size in dwords of the data following this header */
};

/* Idle Check condition register */
struct dbg_idle_chk_cond_reg {
        __le32 data;
#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK   0xFFFFFF
#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT  0
#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK  0xFF
#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
        __le16 num_entries; /* number of registers entries to check */
        u8 entry_size; /* size of registers entry (in dwords) */
        u8 start_entry; /* index of the first entry to check */
};

/* Idle Check info register */
struct dbg_idle_chk_info_reg {
        __le32 data;
#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK   0xFFFFFF
#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT  0
#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK  0xFF
#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
        __le16 size; /* register size in dwords */
        struct dbg_mode_hdr mode; /* Mode header */
};

/* Idle Check register */
union dbg_idle_chk_reg {
        struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
        struct dbg_idle_chk_info_reg info_reg; /* info register */
};

/* Idle Check result header */
struct dbg_idle_chk_result_hdr {
        __le16 rule_id; /* Failing rule index */
        __le16 mem_entry_id; /* Failing memory entry index */
        u8 num_dumped_cond_regs; /* number of dumped condition registers */
        u8 num_dumped_info_regs; /* number of dumped condition registers */
        u8 severity; /* from dbg_idle_chk_severity_types enum */
        u8 reserved;
};

/* Idle Check result register header */
struct dbg_idle_chk_result_reg_hdr {
        u8 data;
#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1
#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F
#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
        u8 start_entry; /* index of the first checked entry */
        __le16 size; /* register size in dwords */
};

/* Idle Check rule */
struct dbg_idle_chk_rule {
        __le16 rule_id; /* Idle Check rule ID */
        u8 severity; /* value from dbg_idle_chk_severity_types enum */
        u8 cond_id; /* Condition ID */
        u8 num_cond_regs; /* number of condition registers */
        u8 num_info_regs; /* number of info registers */
        u8 num_imms; /* number of immediates in the condition */
        u8 reserved1;
        __le16 reg_offset; /* offset of this rules registers in the idle check
                            * register array (in dbg_idle_chk_reg units).
                            */
        __le16 imm_offset; /* offset of this rules immediate values in the
                            * immediate values array (in dwords).
                            */
};

/* Idle Check rule parsing data */
struct dbg_idle_chk_rule_parsing_data {
        __le32 data;
#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK  0x1
#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK  0x7FFFFFFF
#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
};

/* idle check severity types */
enum dbg_idle_chk_severity_types {
        /* idle check failure should cause an error */
        IDLE_CHK_SEVERITY_ERROR,
        /* idle check failure should cause an error only if theres no traffic */
        IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
        /* idle check failure should cause a warning */
        IDLE_CHK_SEVERITY_WARNING,
        MAX_DBG_IDLE_CHK_SEVERITY_TYPES
};

/* Debug Bus block data */
struct dbg_bus_block_data {
        u8 enabled; /* Indicates if the block is enabled for recording (0/1) */
        u8 hw_id; /* HW ID associated with the block */
        u8 line_num; /* Debug line number to select */
        u8 right_shift; /* Number of units to  right the debug data (0-3) */
        u8 cycle_en; /* 4-bit value: bit i set -> unit i is enabled. */
        u8 force_valid; /* 4-bit value: bit i set -> unit i is forced valid. */
        u8 force_frame; /* 4-bit value: bit i set -> unit i frame bit is forced.
                         */
        u8 reserved;
};

/* Debug Bus Clients */
enum dbg_bus_clients {
        DBG_BUS_CLIENT_RBCN,
        DBG_BUS_CLIENT_RBCP,
        DBG_BUS_CLIENT_RBCR,
        DBG_BUS_CLIENT_RBCT,
        DBG_BUS_CLIENT_RBCU,
        DBG_BUS_CLIENT_RBCF,
        DBG_BUS_CLIENT_RBCX,
        DBG_BUS_CLIENT_RBCS,
        DBG_BUS_CLIENT_RBCH,
        DBG_BUS_CLIENT_RBCZ,
        DBG_BUS_CLIENT_OTHER_ENGINE,
        DBG_BUS_CLIENT_TIMESTAMP,
        DBG_BUS_CLIENT_CPU,
        DBG_BUS_CLIENT_RBCY,
        DBG_BUS_CLIENT_RBCQ,
        DBG_BUS_CLIENT_RBCM,
        DBG_BUS_CLIENT_RBCB,
        DBG_BUS_CLIENT_RBCW,
        DBG_BUS_CLIENT_RBCV,

        MAX_DBG_BUS_CLIENTS
};

/* Debug Bus memory address */
struct dbg_bus_mem_addr {
        __le32 lo;
        __le32 hi;
};

/* Debug Bus PCI buffer data */
struct dbg_bus_pci_buf_data {
        struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
        struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
        __le32 size; /* PCI buffer size in bytes */
};

/* Debug Bus Storm EID range filter params */
struct dbg_bus_storm_eid_range_params {
        u8 min; /* Minimal event ID to filter on */
        u8 max; /* Maximal event ID to filter on */
};

/* Debug Bus Storm EID mask filter params */
struct dbg_bus_storm_eid_mask_params {
        u8 val; /* Event ID value */
        u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
};

/* Debug Bus Storm EID filter params */
union dbg_bus_storm_eid_params {
        struct dbg_bus_storm_eid_range_params range;
        struct dbg_bus_storm_eid_mask_params mask;
};

/* Debug Bus Storm data */
struct dbg_bus_storm_data {
        u8 fast_enabled;
        u8 fast_mode;
        u8 slow_enabled;
        u8 slow_mode;
        u8 hw_id;
        u8 eid_filter_en;
        u8 eid_range_not_mask;
        u8 cid_filter_en;
        union dbg_bus_storm_eid_params eid_filter_params;
        __le16 reserved;
        __le32 cid;
};

/* Debug Bus data */
struct dbg_bus_data {
        __le32 app_version; /* The tools version number of the application */
        u8 state; /* The current debug bus state */
        u8 hw_dwords; /* HW dwords per cycle */
        u8 next_hw_id; /* Next HW ID to be associated with an input */
        u8 num_enabled_blocks; /* Number of blocks enabled for recording */
        u8 num_enabled_storms; /* Number of Storms enabled for recording */
        u8 target; /* Output target */
        u8 next_trigger_state; /* ID of next trigger state to be added */
        u8 next_constraint_id; /* ID of next filter/trigger constraint to be
                                * added.
                                */
        u8 one_shot_en; /* Indicates if one-shot mode is enabled (0/1) */
        u8 grc_input_en; /* Indicates if GRC recording is enabled (0/1) */
        u8 timestamp_input_en; /* Indicates if timestamp recording is enabled
                                * (0/1).
                                */
        u8 filter_en; /* Indicates if the recording filter is enabled (0/1) */
        u8 trigger_en; /* Indicates if the recording trigger is enabled (0/1) */
        u8 adding_filter; /* If true, the next added constraint belong to the
                           * filter. Otherwise, it belongs to the last added
                           * trigger state. Valid only if either filter or
                           * triggers are enabled.
                           */
        u8 filter_pre_trigger; /* Indicates if the recording filter should be
                                * applied before the trigger. Valid only if both
                                * filter and trigger are enabled (0/1).
                                */
        u8 filter_post_trigger; /* Indicates if the recording filter should be
                                 * applied after the trigger. Valid only if both
                                 * filter and trigger are enabled (0/1).
                                 */
        u8 unify_inputs; /* If true, all inputs are associated with HW ID 0.
                          * Otherwise, each input is assigned a different HW ID
                          * (0/1).
                          */
        u8 rcv_from_other_engine; /* Indicates if the other engine sends it NW
                                   * recording to this engine (0/1).
                                   */
        struct dbg_bus_pci_buf_data pci_buf; /* Debug Bus PCI buffer data. Valid
                                              * only when the target is
                                              * DBG_BUS_TARGET_ID_PCI.
                                              */
        __le16 reserved;
        struct dbg_bus_block_data blocks[80];/* Debug Bus data for each block */
        struct dbg_bus_storm_data storms[6]; /* Debug Bus data for each block */
};

/* Debug bus frame modes */
enum dbg_bus_frame_modes {
        DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
        DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
        DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
        MAX_DBG_BUS_FRAME_MODES
};

/* Debug bus states */
enum dbg_bus_states {
        DBG_BUS_STATE_IDLE, /* debug bus idle state (not recording) */
        DBG_BUS_STATE_READY, /* debug bus is ready for configuration and
                              * recording.
                              */
        DBG_BUS_STATE_RECORDING, /* debug bus is currently recording */
        DBG_BUS_STATE_STOPPED, /* debug bus recording has stopped */
        MAX_DBG_BUS_STATES
};

/* Debug bus target IDs */
enum dbg_bus_targets {
        /* records debug bus to DBG block internal buffer */
        DBG_BUS_TARGET_ID_INT_BUF,
        /* records debug bus to the NW */
        DBG_BUS_TARGET_ID_NIG,
        /* records debug bus to a PCI buffer */
        DBG_BUS_TARGET_ID_PCI,
        MAX_DBG_BUS_TARGETS
};

/* GRC Dump data */
struct dbg_grc_data {
        __le32 param_val[40]; /* Value of each GRC parameter. Array size must
                               * match the enum dbg_grc_params.
                               */
        u8 param_set_by_user[40]; /* Indicates for each GRC parameter if it was
                                   * set by the user (0/1). Array size must
                                   * match the enum dbg_grc_params.
                                   */
};

/* Debug GRC params */
enum dbg_grc_params {
        DBG_GRC_PARAM_DUMP_TSTORM, /* dump Tstorm memories (0/1) */
        DBG_GRC_PARAM_DUMP_MSTORM, /* dump Mstorm memories (0/1) */
        DBG_GRC_PARAM_DUMP_USTORM, /* dump Ustorm memories (0/1) */
        DBG_GRC_PARAM_DUMP_XSTORM, /* dump Xstorm memories (0/1) */
        DBG_GRC_PARAM_DUMP_YSTORM, /* dump Ystorm memories (0/1) */
        DBG_GRC_PARAM_DUMP_PSTORM, /* dump Pstorm memories (0/1) */
        DBG_GRC_PARAM_DUMP_REGS, /* dump non-memory registers (0/1) */
        DBG_GRC_PARAM_DUMP_RAM, /* dump Storm internal RAMs (0/1) */
        DBG_GRC_PARAM_DUMP_PBUF, /* dump Storm passive buffer (0/1) */
        DBG_GRC_PARAM_DUMP_IOR, /* dump Storm IORs (0/1) */
        DBG_GRC_PARAM_DUMP_VFC, /* dump VFC memories (0/1) */
        DBG_GRC_PARAM_DUMP_CM_CTX, /* dump CM contexts (0/1) */
        DBG_GRC_PARAM_DUMP_PXP, /* dump PXP memories (0/1) */
        DBG_GRC_PARAM_DUMP_RSS, /* dump RSS memories (0/1) */
        DBG_GRC_PARAM_DUMP_CAU, /* dump CAU memories (0/1) */
        DBG_GRC_PARAM_DUMP_QM, /* dump QM memories (0/1) */
        DBG_GRC_PARAM_DUMP_MCP, /* dump MCP memories (0/1) */
        DBG_GRC_PARAM_RESERVED, /* reserved */
        DBG_GRC_PARAM_DUMP_CFC, /* dump CFC memories (0/1) */
        DBG_GRC_PARAM_DUMP_IGU, /* dump IGU memories (0/1) */
        DBG_GRC_PARAM_DUMP_BRB, /* dump BRB memories (0/1) */
        DBG_GRC_PARAM_DUMP_BTB, /* dump BTB memories (0/1) */
        DBG_GRC_PARAM_DUMP_BMB, /* dump BMB memories (0/1) */
        DBG_GRC_PARAM_DUMP_NIG, /* dump NIG memories (0/1) */
        DBG_GRC_PARAM_DUMP_MULD, /* dump MULD memories (0/1) */
        DBG_GRC_PARAM_DUMP_PRS, /* dump PRS memories (0/1) */
        DBG_GRC_PARAM_DUMP_DMAE, /* dump PRS memories (0/1) */
        DBG_GRC_PARAM_DUMP_TM, /* dump TM (timers) memories (0/1) */
        DBG_GRC_PARAM_DUMP_SDM, /* dump SDM memories (0/1) */
        DBG_GRC_PARAM_DUMP_DIF, /* dump DIF memories (0/1) */
        DBG_GRC_PARAM_DUMP_STATIC, /* dump static debug data (0/1) */
        DBG_GRC_PARAM_UNSTALL, /* un-stall Storms after dump (0/1) */
        DBG_GRC_PARAM_NUM_LCIDS, /* number of LCIDs (0..320) */
        DBG_GRC_PARAM_NUM_LTIDS, /* number of LTIDs (0..320) */
        /* preset: exclude all memories from dump (1 only) */
        DBG_GRC_PARAM_EXCLUDE_ALL,
        /* preset: include memories for crash dump (1 only) */
        DBG_GRC_PARAM_CRASH,
        /* perform dump only if MFW is responding (0/1) */
        DBG_GRC_PARAM_PARITY_SAFE,
        DBG_GRC_PARAM_DUMP_CM, /* dump CM memories (0/1) */
        DBG_GRC_PARAM_DUMP_PHY, /* dump PHY memories (0/1) */
        MAX_DBG_GRC_PARAMS
};

/* Debug reset registers */
enum dbg_reset_regs {
        DBG_RESET_REG_MISCS_PL_UA,
        DBG_RESET_REG_MISCS_PL_HV,
        DBG_RESET_REG_MISCS_PL_HV_2,
        DBG_RESET_REG_MISC_PL_UA,
        DBG_RESET_REG_MISC_PL_HV,
        DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
        DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
        DBG_RESET_REG_MISC_PL_PDA_VAUX,
        MAX_DBG_RESET_REGS
};

/* Debug status codes */
enum dbg_status {
        DBG_STATUS_OK,
        DBG_STATUS_APP_VERSION_NOT_SET,
        DBG_STATUS_UNSUPPORTED_APP_VERSION,
        DBG_STATUS_DBG_BLOCK_NOT_RESET,
        DBG_STATUS_INVALID_ARGS,
        DBG_STATUS_OUTPUT_ALREADY_SET,
        DBG_STATUS_INVALID_PCI_BUF_SIZE,
        DBG_STATUS_PCI_BUF_ALLOC_FAILED,
        DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
        DBG_STATUS_TOO_MANY_INPUTS,
        DBG_STATUS_INPUT_OVERLAP,
        DBG_STATUS_HW_ONLY_RECORDING,
        DBG_STATUS_STORM_ALREADY_ENABLED,
        DBG_STATUS_STORM_NOT_ENABLED,
        DBG_STATUS_BLOCK_ALREADY_ENABLED,
        DBG_STATUS_BLOCK_NOT_ENABLED,
        DBG_STATUS_NO_INPUT_ENABLED,
        DBG_STATUS_NO_FILTER_TRIGGER_64B,
        DBG_STATUS_FILTER_ALREADY_ENABLED,
        DBG_STATUS_TRIGGER_ALREADY_ENABLED,
        DBG_STATUS_TRIGGER_NOT_ENABLED,
        DBG_STATUS_CANT_ADD_CONSTRAINT,
        DBG_STATUS_TOO_MANY_TRIGGER_STATES,
        DBG_STATUS_TOO_MANY_CONSTRAINTS,
        DBG_STATUS_RECORDING_NOT_STARTED,
        DBG_STATUS_DATA_DIDNT_TRIGGER,
        DBG_STATUS_NO_DATA_RECORDED,
        DBG_STATUS_DUMP_BUF_TOO_SMALL,
        DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
        DBG_STATUS_UNKNOWN_CHIP,
        DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
        DBG_STATUS_BLOCK_IN_RESET,
        DBG_STATUS_INVALID_TRACE_SIGNATURE,
        DBG_STATUS_INVALID_NVRAM_BUNDLE,
        DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
        DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
        DBG_STATUS_NVRAM_READ_FAILED,
        DBG_STATUS_IDLE_CHK_PARSE_FAILED,
        DBG_STATUS_MCP_TRACE_BAD_DATA,
        DBG_STATUS_MCP_TRACE_NO_META,
        DBG_STATUS_MCP_COULD_NOT_HALT,
        DBG_STATUS_MCP_COULD_NOT_RESUME,
        DBG_STATUS_DMAE_FAILED,
        DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
        DBG_STATUS_IGU_FIFO_BAD_DATA,
        DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
        DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
        DBG_STATUS_REG_FIFO_BAD_DATA,
        DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
        DBG_STATUS_DBG_ARRAY_NOT_SET,
        DBG_STATUS_MULTI_BLOCKS_WITH_FILTER,
        MAX_DBG_STATUS
};

/* Debug Storms IDs */
enum dbg_storms {
        DBG_TSTORM_ID,
        DBG_MSTORM_ID,
        DBG_USTORM_ID,
        DBG_XSTORM_ID,
        DBG_YSTORM_ID,
        DBG_PSTORM_ID,
        MAX_DBG_STORMS
};

/* Idle Check data */
struct idle_chk_data {
        __le32 buf_size; /* Idle check buffer size in dwords */
        u8 buf_size_set; /* Indicates if the idle check buffer size was set
                          * (0/1).
                          */
        u8 reserved1;
        __le16 reserved2;
};

/* Debug Tools data (per HW function) */
struct dbg_tools_data {
        struct dbg_grc_data grc; /* GRC Dump data */
        struct dbg_bus_data bus; /* Debug Bus data */
        struct idle_chk_data idle_chk; /* Idle Check data */
        u8 mode_enable[40]; /* Indicates if a mode is enabled (0/1) */
        u8 block_in_reset[80]; /* Indicates if a block is in reset state (0/1).
                                */
        u8 chip_id; /* Chip ID (from enum chip_ids) */
        u8 platform_id; /* Platform ID (from enum platform_ids) */
        u8 initialized; /* Indicates if the data was initialized */
        u8 reserved;
};

/********************************/
/* HSI Init Functions constants */
/********************************/

/* Number of VLAN priorities */
#define NUM_OF_VLAN_PRIORITIES  8

struct init_brb_ram_req {
        __le32 guranteed_per_tc;
        __le32 headroom_per_tc;
        __le32 min_pkt_size;
        __le32 max_ports_per_engine;
        u8 num_active_tcs[MAX_NUM_PORTS];
};

struct init_ets_tc_req {
        u8 use_sp;
        u8 use_wfq;
        __le16 weight;
};

struct init_ets_req {
        __le32 mtu;
        struct init_ets_tc_req tc_req[NUM_OF_TCS];
};

struct init_nig_lb_rl_req {
        __le16 lb_mac_rate;
        __le16 lb_rate;
        __le32 mtu;
        __le16 tc_rate[NUM_OF_PHYS_TCS];
};

struct init_nig_pri_tc_map_entry {
        u8 tc_id;
        u8 valid;
};

struct init_nig_pri_tc_map_req {
        struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
};

struct init_qm_port_params {
        u8 active;
        u8 active_phys_tcs;
        __le16 num_pbf_cmd_lines;
        __le16 num_btb_blocks;
        __le16 reserved;
};

/* QM per-PQ init parameters */
struct init_qm_pq_params {
        u8 vport_id;
        u8 tc_id;
        u8 wrr_group;
        u8 rl_valid;
};

/* QM per-vport init parameters */
struct init_qm_vport_params {
        __le32 vport_rl;
        __le16 vport_wfq;
        __le16 first_tx_pq_id[NUM_OF_TCS];
};

/**************************************/
/* Init Tool HSI constants and macros */
/**************************************/

/* Width of GRC address in bits (addresses are specified in dwords) */
#define GRC_ADDR_BITS   23
#define MAX_GRC_ADDR    (BIT(GRC_ADDR_BITS) - 1)

/* indicates an init that should be applied to any phase ID */
#define ANY_PHASE_ID    0xffff

/* Max size in dwords of a zipped array */
#define MAX_ZIPPED_SIZE 8192

struct fw_asserts_ram_section {
        __le16 section_ram_line_offset;
        __le16 section_ram_line_size;
        u8 list_dword_offset;
        u8 list_element_dword_size;
        u8 list_num_elements;
        u8 list_next_index_dword_offset;
};

struct fw_ver_num {
        u8 major; /* Firmware major version number */
        u8 minor; /* Firmware minor version number */
        u8 rev; /* Firmware revision version number */
        u8 eng; /* Firmware engineering version number (for bootleg versions) */
};

struct fw_ver_info {
        __le16 tools_ver; /* Tools version number */
        u8 image_id; /* FW image ID (e.g. main) */
        u8 reserved1;
        struct fw_ver_num num; /* FW version number */
        __le32 timestamp; /* FW Timestamp in unix time  (sec. since 1970) */
        __le32 reserved2;
};

struct fw_info {
        struct fw_ver_info ver;
        struct fw_asserts_ram_section fw_asserts_section;
};

struct fw_info_location {
        __le32 grc_addr;
        __le32 size;
};

enum init_modes {
        MODE_RESERVED,
        MODE_BB_B0,
        MODE_K2,
        MODE_ASIC,
        MODE_RESERVED2,
        MODE_RESERVED3,
        MODE_RESERVED4,
        MODE_RESERVED5,
        MODE_SF,
        MODE_MF_SD,
        MODE_MF_SI,
        MODE_PORTS_PER_ENG_1,
        MODE_PORTS_PER_ENG_2,
        MODE_PORTS_PER_ENG_4,
        MODE_100G,
        MODE_40G,
        MODE_RESERVED6,
        MAX_INIT_MODES
};

enum init_phases {
        PHASE_ENGINE,
        PHASE_PORT,
        PHASE_PF,
        PHASE_VF,
        PHASE_QM_PF,
        MAX_INIT_PHASES
};

enum init_split_types {
        SPLIT_TYPE_NONE,
        SPLIT_TYPE_PORT,
        SPLIT_TYPE_PF,
        SPLIT_TYPE_PORT_PF,
        SPLIT_TYPE_VF,
        MAX_INIT_SPLIT_TYPES
};

/* Binary buffer header */
struct bin_buffer_hdr {
        __le32 offset;
        __le32 length;
};

/* binary init buffer types */
enum bin_init_buffer_type {
        BIN_BUF_INIT_FW_VER_INFO,
        BIN_BUF_INIT_CMD,
        BIN_BUF_INIT_VAL,
        BIN_BUF_INIT_MODE_TREE,
        BIN_BUF_INIT_IRO,
        MAX_BIN_INIT_BUFFER_TYPE
};

/* init array header: raw */
struct init_array_raw_hdr {
        __le32 data;
#define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF
#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
#define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF
#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
};

/* init array header: standard */
struct init_array_standard_hdr {
        __le32 data;
#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK       0xF
#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT      0
#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK       0xFFFFFFF
#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT      4
};

/* init array header: zipped */
struct init_array_zipped_hdr {
        __le32 data;
#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF
#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF
#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
};

/* init array header: pattern */
struct init_array_pattern_hdr {
        __le32 data;
#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK                0xF
#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT               0
#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK        0xF
#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT       4
#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK         0xFFFFFF
#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT        8
};

/* init array header union */
union init_array_hdr {
        struct init_array_raw_hdr raw;
        struct init_array_standard_hdr standard;
        struct init_array_zipped_hdr zipped;
        struct init_array_pattern_hdr pattern;
};

/* init array types */
enum init_array_types {
        INIT_ARR_STANDARD,
        INIT_ARR_ZIPPED,
        INIT_ARR_PATTERN,
        MAX_INIT_ARRAY_TYPES
};

/* init operation: callback */
struct init_callback_op {
        __le32 op_data;
#define INIT_CALLBACK_OP_OP_MASK        0xF
#define INIT_CALLBACK_OP_OP_SHIFT       0
#define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
        __le16 callback_id;
        __le16 block_id;
};

/* init operation: delay */
struct init_delay_op {
        __le32 op_data;
#define INIT_DELAY_OP_OP_MASK           0xF
#define INIT_DELAY_OP_OP_SHIFT          0
#define INIT_DELAY_OP_RESERVED_MASK     0xFFFFFFF
#define INIT_DELAY_OP_RESERVED_SHIFT    4
        __le32 delay;
};

/* init operation: if_mode */
struct init_if_mode_op {
        __le32 op_data;
#define INIT_IF_MODE_OP_OP_MASK                 0xF
#define INIT_IF_MODE_OP_OP_SHIFT                0
#define INIT_IF_MODE_OP_RESERVED1_MASK          0xFFF
#define INIT_IF_MODE_OP_RESERVED1_SHIFT         4
#define INIT_IF_MODE_OP_CMD_OFFSET_MASK         0xFFFF
#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT        16
        __le16 reserved2;
        __le16 modes_buf_offset;
};

/* init operation: if_phase */
struct init_if_phase_op {
        __le32 op_data;
#define INIT_IF_PHASE_OP_OP_MASK                0xF
#define INIT_IF_PHASE_OP_OP_SHIFT               0
#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK       0x1
#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT      4
#define INIT_IF_PHASE_OP_RESERVED1_MASK         0x7FF
#define INIT_IF_PHASE_OP_RESERVED1_SHIFT        5
#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK        0xFFFF
#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT       16
        __le32 phase_data;
#define INIT_IF_PHASE_OP_PHASE_MASK             0xFF
#define INIT_IF_PHASE_OP_PHASE_SHIFT            0
#define INIT_IF_PHASE_OP_RESERVED2_MASK         0xFF
#define INIT_IF_PHASE_OP_RESERVED2_SHIFT        8
#define INIT_IF_PHASE_OP_PHASE_ID_MASK          0xFFFF
#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT         16
};

/* init mode operators */
enum init_mode_ops {
        INIT_MODE_OP_NOT,
        INIT_MODE_OP_OR,
        INIT_MODE_OP_AND,
        MAX_INIT_MODE_OPS
};

/* init operation: raw */
struct init_raw_op {
        __le32 op_data;
#define INIT_RAW_OP_OP_MASK             0xF
#define INIT_RAW_OP_OP_SHIFT            0
#define INIT_RAW_OP_PARAM1_MASK         0xFFFFFFF
#define INIT_RAW_OP_PARAM1_SHIFT        4
        __le32 param2;
};

/* init array params */
struct init_op_array_params {
        __le16 size;
        __le16 offset;
};

/* Write init operation arguments */
union init_write_args {
        __le32 inline_val;
        __le32 zeros_count;
        __le32 array_offset;
        struct init_op_array_params runtime;
};

/* init operation: write */
struct init_write_op {
        __le32 data;
#define INIT_WRITE_OP_OP_MASK           0xF
#define INIT_WRITE_OP_OP_SHIFT          0
#define INIT_WRITE_OP_SOURCE_MASK       0x7
#define INIT_WRITE_OP_SOURCE_SHIFT      4
#define INIT_WRITE_OP_RESERVED_MASK     0x1
#define INIT_WRITE_OP_RESERVED_SHIFT    7
#define INIT_WRITE_OP_WIDE_BUS_MASK     0x1
#define INIT_WRITE_OP_WIDE_BUS_SHIFT    8
#define INIT_WRITE_OP_ADDRESS_MASK      0x7FFFFF
#define INIT_WRITE_OP_ADDRESS_SHIFT     9
        union init_write_args args;
};

/* init operation: read */
struct init_read_op {
        __le32 op_data;
#define INIT_READ_OP_OP_MASK            0xF
#define INIT_READ_OP_OP_SHIFT           0
#define INIT_READ_OP_POLL_TYPE_MASK     0xF
#define INIT_READ_OP_POLL_TYPE_SHIFT    4
#define INIT_READ_OP_RESERVED_MASK      0x1
#define INIT_READ_OP_RESERVED_SHIFT     8
#define INIT_READ_OP_ADDRESS_MASK       0x7FFFFF
#define INIT_READ_OP_ADDRESS_SHIFT      9
        __le32 expected_val;

};

/* Init operations union */
union init_op {
        struct init_raw_op raw;
        struct init_write_op write;
        struct init_read_op read;
        struct init_if_mode_op if_mode;
        struct init_if_phase_op if_phase;
        struct init_callback_op callback;
        struct init_delay_op delay;
};

/* Init command operation types */
enum init_op_types {
        INIT_OP_READ,
        INIT_OP_WRITE,
        INIT_OP_IF_MODE,
        INIT_OP_IF_PHASE,
        INIT_OP_DELAY,
        INIT_OP_CALLBACK,
        MAX_INIT_OP_TYPES
};

/* init polling types */
enum init_poll_types {
        INIT_POLL_NONE,
        INIT_POLL_EQ,
        INIT_POLL_OR,
        INIT_POLL_AND,
        MAX_INIT_POLL_TYPES
};

/* init source types */
enum init_source_types {
        INIT_SRC_INLINE,
        INIT_SRC_ZEROS,
        INIT_SRC_ARRAY,
        INIT_SRC_RUNTIME,
        MAX_INIT_SOURCE_TYPES
};

/* Internal RAM Offsets macro data */
struct iro {
        __le32 base;
        __le16 m1;
        __le16 m2;
        __le16 m3;
        __le16 size;
};

/***************************** Public Functions *******************************/
/**
 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
 *      arrays.
 *
 * @param bin_ptr - a pointer to the binary data with debug arrays.
 */
enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
/**
 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
 *      GRC Dump.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
 *      data.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
                                              struct qed_ptt *p_ptt,
                                              u32 *buf_size);
/**
 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param dump_buf - Pointer to write the collected GRC data into.
 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
 * @param num_dumped_dwords - OUT: number of dumped dwords.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 *      - the specified dump buffer is too small
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
                                 struct qed_ptt *p_ptt,
                                 u32 *dump_buf,
                                 u32 buf_size_in_dwords,
                                 u32 *num_dumped_dwords);
/**
 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
 *      for idle check results.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
 *      data.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
                                                   struct qed_ptt *p_ptt,
                                                   u32 *buf_size);
/**
 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
 *      into the specified buffer.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param dump_buf - Pointer to write the idle check data into.
 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
 * @param num_dumped_dwords - OUT: number of dumped dwords.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 *      - the specified buffer is too small
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
                                      struct qed_ptt *p_ptt,
                                      u32 *dump_buf,
                                      u32 buf_size_in_dwords,
                                      u32 *num_dumped_dwords);
/**
 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
 *      for mcp trace results.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 *      - the trace data in MCP scratchpad contain an invalid signature
 *      - the bundle ID in NVRAM is invalid
 *      - the trace meta data cannot be found (in NVRAM or image file)
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
                                                    struct qed_ptt *p_ptt,
                                                    u32 *buf_size);
/**
 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
 *      into the specified buffer.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param dump_buf - Pointer to write the mcp trace data into.
 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
 * @param num_dumped_dwords - OUT: number of dumped dwords.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 *      - the specified buffer is too small
 *      - the trace data in MCP scratchpad contain an invalid signature
 *      - the bundle ID in NVRAM is invalid
 *      - the trace meta data cannot be found (in NVRAM or image file)
 *      - the trace meta data cannot be read (from NVRAM or image file)
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
                                       struct qed_ptt *p_ptt,
                                       u32 *dump_buf,
                                       u32 buf_size_in_dwords,
                                       u32 *num_dumped_dwords);
/**
 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
 *      for grc trace fifo results.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
                                                   struct qed_ptt *p_ptt,
                                                   u32 *buf_size);
/**
 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
 *      the specified buffer.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param dump_buf - Pointer to write the reg fifo data into.
 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
 * @param num_dumped_dwords - OUT: number of dumped dwords.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 *      - the specified buffer is too small
 *      - DMAE transaction failed
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
                                      struct qed_ptt *p_ptt,
                                      u32 *dump_buf,
                                      u32 buf_size_in_dwords,
                                      u32 *num_dumped_dwords);
/**
 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
 *      for the IGU fifo results.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
 *      data.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
                                                   struct qed_ptt *p_ptt,
                                                   u32 *buf_size);
/**
 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
 *      the specified buffer.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param dump_buf - Pointer to write the IGU fifo data into.
 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
 * @param num_dumped_dwords - OUT: number of dumped dwords.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 *      - the specified buffer is too small
 *      - DMAE transaction failed
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
                                      struct qed_ptt *p_ptt,
                                      u32 *dump_buf,
                                      u32 buf_size_in_dwords,
                                      u32 *num_dumped_dwords);
/**
 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
 *      buffer size for protection override window results.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param buf_size - OUT: required buffer size (in dwords) for protection
 *      override data.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 * Otherwise, returns ok.
 */
enum dbg_status
qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
                                              struct qed_ptt *p_ptt,
                                              u32 *buf_size);
/**
 * @brief qed_dbg_protection_override_dump - Reads protection override window
 *      entries and writes the results into the specified buffer.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param dump_buf - Pointer to write the protection override data into.
 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
 * @param num_dumped_dwords - OUT: number of dumped dwords.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 *      - the specified buffer is too small
 *      - DMAE transaction failed
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
                                                 struct qed_ptt *p_ptt,
                                                 u32 *dump_buf,
                                                 u32 buf_size_in_dwords,
                                                 u32 *num_dumped_dwords);
/**
 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
 *      size for FW Asserts results.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
                                                     struct qed_ptt *p_ptt,
                                                     u32 *buf_size);
/**
 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
 *      into the specified buffer.
 *
 * @param p_hwfn - HW device data
 * @param p_ptt - Ptt window used for writing the registers.
 * @param dump_buf - Pointer to write the FW Asserts data into.
 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
 * @param num_dumped_dwords - OUT: number of dumped dwords.
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 *      - the specified buffer is too small
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
                                        struct qed_ptt *p_ptt,
                                        u32 *dump_buf,
                                        u32 buf_size_in_dwords,
                                        u32 *num_dumped_dwords);
/**
 * @brief qed_dbg_print_attn - Prints attention registers values in the
 *      specified results struct.
 *
 * @param p_hwfn
 * @param results - Pointer to the attention read results
 *
 * @return error if one of the following holds:
 *      - the version wasn't set
 * Otherwise, returns ok.
 */
enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
                                   struct dbg_attn_block_result *results);

/******************************** Constants **********************************/

#define MAX_NAME_LEN    16

/***************************** Public Functions *******************************/
/**
 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
 *      debug arrays.
 *
 * @param bin_ptr - a pointer to the binary data with debug arrays.
 */
enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
/**
 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
 *
 * @param status - a debug status code.
 *
 * @return a string for the specified status
 */
const char *qed_dbg_get_status_str(enum dbg_status status);
/**
 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
 *      for idle check results (in bytes).
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - idle check dump buffer.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
 *      results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
                                                  u32 *dump_buf,
                                                  u32  num_dumped_dwords,
                                                  u32 *results_buf_size);
/**
 * @brief qed_print_idle_chk_results - Prints idle check results
 *
 * @param p_hwfn - HW device data

 * @param dump_buf - idle check dump buffer.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf - buffer for printing the idle check results.
 * @param num_errors - OUT: number of errors found in idle check.
 * @param num_warnings - OUT: number of warnings found in idle check.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
                                           u32 *dump_buf,
                                           u32 num_dumped_dwords,
                                           char *results_buf,
                                           u32 *num_errors,
                                           u32 *num_warnings);
/**
 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
 *      for MCP Trace results (in bytes).
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - MCP Trace dump buffer.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
 *      results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
                                                   u32 *dump_buf,
                                                   u32 num_dumped_dwords,
                                                   u32 *results_buf_size);
/**
 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - mcp trace dump buffer, starting from the header.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf - buffer for printing the mcp trace results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
                                            u32 *dump_buf,
                                            u32 num_dumped_dwords,
                                            char *results_buf);
/**
 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
 *      for reg_fifo results (in bytes).
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - reg fifo dump buffer.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
 *      results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
                                                  u32 *dump_buf,
                                                  u32 num_dumped_dwords,
                                                  u32 *results_buf_size);
/**
 * @brief qed_print_reg_fifo_results - Prints reg fifo results
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - reg fifo dump buffer, starting from the header.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf - buffer for printing the reg fifo results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
                                           u32 *dump_buf,
                                           u32 num_dumped_dwords,
                                           char *results_buf);
/**
 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
 *      for igu_fifo results (in bytes).
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - IGU fifo dump buffer.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
 *      results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
                                                  u32 *dump_buf,
                                                  u32 num_dumped_dwords,
                                                  u32 *results_buf_size);
/**
 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - IGU fifo dump buffer, starting from the header.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf - buffer for printing the IGU fifo results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
                                           u32 *dump_buf,
                                           u32 num_dumped_dwords,
                                           char *results_buf);
/**
 * @brief qed_get_protection_override_results_buf_size - Returns the required
 *      buffer size for protection override results (in bytes).
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - protection override dump buffer.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
 *      results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status
qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
                                             u32 *dump_buf,
                                             u32 num_dumped_dwords,
                                             u32 *results_buf_size);
/**
 * @brief qed_print_protection_override_results - Prints protection override
 *      results.
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - protection override dump buffer, starting from the header.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf - buffer for printing the reg fifo results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
                                                      u32 *dump_buf,
                                                      u32 num_dumped_dwords,
                                                      char *results_buf);
/**
 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
 *      for FW Asserts results (in bytes).
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - FW Asserts dump buffer.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
 *      results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
                                                    u32 *dump_buf,
                                                    u32 num_dumped_dwords,
                                                    u32 *results_buf_size);
/**
 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
 *
 * @param p_hwfn - HW device data
 * @param dump_buf - FW Asserts dump buffer, starting from the header.
 * @param num_dumped_dwords - number of dwords that were dumped.
 * @param results_buf - buffer for printing the FW Asserts results.
 *
 * @return error if the parsing fails, ok otherwise.
 */
enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
                                             u32 *dump_buf,
                                             u32 num_dumped_dwords,
                                             char *results_buf);
/* Win 2 */
#define GTT_BAR0_MAP_REG_IGU_CMD        0x00f000UL

/* Win 3 */
#define GTT_BAR0_MAP_REG_TSDM_RAM       0x010000UL

/* Win 4 */
#define GTT_BAR0_MAP_REG_MSDM_RAM       0x011000UL

/* Win 5 */
#define GTT_BAR0_MAP_REG_MSDM_RAM_1024  0x012000UL

/* Win 6 */
#define GTT_BAR0_MAP_REG_USDM_RAM       0x013000UL

/* Win 7 */
#define GTT_BAR0_MAP_REG_USDM_RAM_1024  0x014000UL

/* Win 8 */
#define GTT_BAR0_MAP_REG_USDM_RAM_2048  0x015000UL

/* Win 9 */
#define GTT_BAR0_MAP_REG_XSDM_RAM       0x016000UL

/* Win 10 */
#define GTT_BAR0_MAP_REG_YSDM_RAM       0x017000UL

/* Win 11 */
#define GTT_BAR0_MAP_REG_PSDM_RAM       0x018000UL

/**
 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
 *
 * Returns the required host memory size in 4KB units.
 * Must be called before all QM init HSI functions.
 *
 * @param pf_id - physical function ID
 * @param num_pf_cids - number of connections used by this PF
 * @param num_vf_cids - number of connections used by VFs of this PF
 * @param num_tids - number of tasks used by this PF
 * @param num_pf_pqs - number of PQs used by this PF
 * @param num_vf_pqs - number of PQs used by VFs of this PF
 *
 * @return The required host memory size in 4KB units.
 */
u32 qed_qm_pf_mem_size(u8 pf_id,
                       u32 num_pf_cids,
                       u32 num_vf_cids,
                       u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);

struct qed_qm_common_rt_init_params {
        u8 max_ports_per_engine;
        u8 max_phys_tcs_per_port;
        bool pf_rl_en;
        bool pf_wfq_en;
        bool vport_rl_en;
        bool vport_wfq_en;
        struct init_qm_port_params *port_params;
};

int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
                          struct qed_qm_common_rt_init_params *p_params);

struct qed_qm_pf_rt_init_params {
        u8 port_id;
        u8 pf_id;
        u8 max_phys_tcs_per_port;
        bool is_first_pf;
        u32 num_pf_cids;
        u32 num_vf_cids;
        u32 num_tids;
        u16 start_pq;
        u16 num_pf_pqs;
        u16 num_vf_pqs;
        u8 start_vport;
        u8 num_vports;
        u16 pf_wfq;
        u32 pf_rl;
        struct init_qm_pq_params *pq_params;
        struct init_qm_vport_params *vport_params;
};

int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
        struct qed_ptt *p_ptt,
        struct qed_qm_pf_rt_init_params *p_params);

/**
 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
 *
 * @param p_hwfn
 * @param p_ptt - ptt window used for writing the registers
 * @param pf_id - PF ID
 * @param pf_wfq - WFQ weight. Must be non-zero.
 *
 * @return 0 on success, -1 on error.
 */
int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
                    struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);

/**
 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
 *
 * @param p_hwfn
 * @param p_ptt - ptt window used for writing the registers
 * @param pf_id - PF ID
 * @param pf_rl - rate limit in Mb/sec units
 *
 * @return 0 on success, -1 on error.
 */
int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
                   struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);

/**
 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
 *
 * @param p_hwfn
 * @param p_ptt - ptt window used for writing the registers
 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
 *        with the VPORT for each TC. This array is filled by
 *        qed_qm_pf_rt_init
 * @param vport_wfq - WFQ weight. Must be non-zero.
 *
 * @return 0 on success, -1 on error.
 */
int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
                       struct qed_ptt *p_ptt,
                       u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);

/**
 * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
 *
 * @param p_hwfn
 * @param p_ptt - ptt window used for writing the registers
 * @param vport_id - VPORT ID
 * @param vport_rl - rate limit in Mb/sec units
 *
 * @return 0 on success, -1 on error.
 */
int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
                      struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl);
/**
 * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
 *
 * @param p_hwfn
 * @param p_ptt
 * @param is_release_cmd - true for release, false for stop.
 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
 * @param start_pq - first PQ ID to stop
 * @param num_pqs - Number of PQs to stop, starting from start_pq.
 *
 * @return bool, true if successful, false if timeout occured while waiting for QM command done.
 */
bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
                          struct qed_ptt *p_ptt,
                          bool is_release_cmd,
                          bool is_tx_pq, u16 start_pq, u16 num_pqs);

/**
 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
 *
 * @param p_ptt - ptt window used for writing the registers.
 * @param dest_port - vxlan destination udp port.
 */
void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
                             struct qed_ptt *p_ptt, u16 dest_port);

/**
 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
 *
 * @param p_ptt - ptt window used for writing the registers.
 * @param vxlan_enable - vxlan enable flag.
 */
void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
                          struct qed_ptt *p_ptt, bool vxlan_enable);

/**
 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
 *
 * @param p_ptt - ptt window used for writing the registers.
 * @param eth_gre_enable - eth GRE enable enable flag.
 * @param ip_gre_enable - IP GRE enable enable flag.
 */
void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
                        struct qed_ptt *p_ptt,
                        bool eth_gre_enable, bool ip_gre_enable);

/**
 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
 *
 * @param p_ptt - ptt window used for writing the registers.
 * @param dest_port - geneve destination udp port.
 */
void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
                              struct qed_ptt *p_ptt, u16 dest_port);

/**
 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
 *
 * @param p_ptt - ptt window used for writing the registers.
 * @param eth_geneve_enable - eth GENEVE enable enable flag.
 * @param ip_geneve_enable - IP GENEVE enable enable flag.
 */
void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
                           struct qed_ptt *p_ptt,
                           bool eth_geneve_enable, bool ip_geneve_enable);

#define YSTORM_FLOW_CONTROL_MODE_OFFSET                 (IRO[0].base)
#define YSTORM_FLOW_CONTROL_MODE_SIZE                   (IRO[0].size)
#define TSTORM_PORT_STAT_OFFSET(port_id) \
        (IRO[1].base + ((port_id) * IRO[1].m1))
#define TSTORM_PORT_STAT_SIZE                           (IRO[1].size)
#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
        (IRO[2].base + ((port_id) * IRO[2].m1))
#define TSTORM_LL2_PORT_STAT_SIZE                       (IRO[2].size)
#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
        (IRO[3].base + ((vf_id) * IRO[3].m1))
#define USTORM_VF_PF_CHANNEL_READY_SIZE                 (IRO[3].size)
#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
        (IRO[4].base + (pf_id) * IRO[4].m1)
#define USTORM_FLR_FINAL_ACK_SIZE                       (IRO[4].size)
#define USTORM_EQE_CONS_OFFSET(pf_id) \
        (IRO[5].base + ((pf_id) * IRO[5].m1))
#define USTORM_EQE_CONS_SIZE                            (IRO[5].size)
#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
        (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
#define USTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[6].size)
#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
        (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
#define USTORM_COMMON_QUEUE_CONS_SIZE                   (IRO[7].size)
#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
        (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
#define TSTORM_LL2_RX_PRODS_SIZE                        (IRO[14].size)
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
        (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE             (IRO[15].size)
#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
        (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE             (IRO[16].size)
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
        (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE     (IRO[17].       size)
#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
        (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
#define MSTORM_QUEUE_STAT_SIZE                          (IRO[18].size)
#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
        (IRO[19].base + ((queue_id) * IRO[19].m1))
#define MSTORM_ETH_PF_PRODS_SIZE                        (IRO[19].size)
#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
        (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
#define MSTORM_ETH_VF_PRODS_SIZE                        (IRO[20].size)
#define MSTORM_TPA_TIMEOUT_US_OFFSET                    (IRO[21].base)
#define MSTORM_TPA_TIMEOUT_US_SIZE                      (IRO[21].size)
#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
        (IRO[22].base + ((pf_id) * IRO[22].m1))
#define MSTORM_ETH_PF_STAT_SIZE                         (IRO[21].size)
#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
        (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
#define USTORM_QUEUE_STAT_SIZE                          (IRO[23].size)
#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
        (IRO[24].base + ((pf_id) * IRO[24].m1))
#define USTORM_ETH_PF_STAT_SIZE                         (IRO[24].size)
#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
        (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
#define PSTORM_QUEUE_STAT_SIZE                          (IRO[25].size)
#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
        (IRO[26].base + ((pf_id) * IRO[26].m1))
#define PSTORM_ETH_PF_STAT_SIZE                         (IRO[26].size)
#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \
        (IRO[27].base + ((ethtype) * IRO[27].m1))
#define PSTORM_CTL_FRAME_ETHTYPE_SIZE                   (IRO[27].size)
#define TSTORM_ETH_PRS_INPUT_OFFSET                     (IRO[28].base)
#define TSTORM_ETH_PRS_INPUT_SIZE                       (IRO[28].size)
#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
        (IRO[29].base + ((pf_id) * IRO[29].m1))
#define ETH_RX_RATE_LIMIT_SIZE                          (IRO[29].size)
#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
        (IRO[30].base + ((queue_id) * IRO[30].m1))
#define XSTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[30].size)
#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
        (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
#define TSTORM_SCSI_CMDQ_CONS_SIZE                              (IRO[34].size)
#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
        (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE                           (IRO[35].size)
#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
        (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE                           (IRO[36].size)
#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
        (IRO[37].base + ((pf_id) * IRO[37].m1))
#define TSTORM_ISCSI_RX_STATS_SIZE                              (IRO[37].size)
#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
        (IRO[38].base + ((pf_id) * IRO[38].m1))
#define MSTORM_ISCSI_RX_STATS_SIZE                              (IRO[38].size)
#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
        (IRO[39].base + ((pf_id) * IRO[39].m1))
#define USTORM_ISCSI_RX_STATS_SIZE                              (IRO[39].size)
#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
        (IRO[40].base + ((pf_id) * IRO[40].m1))
#define XSTORM_ISCSI_TX_STATS_SIZE                              (IRO[40].size)
#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
        (IRO[41].base + ((pf_id) * IRO[41].m1))
#define YSTORM_ISCSI_TX_STATS_SIZE                              (IRO[41].size)
#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
        (IRO[42].base + ((pf_id) * IRO[42].m1))
#define PSTORM_ISCSI_TX_STATS_SIZE                              (IRO[42].size)
#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
        (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
#define PSTORM_RDMA_QUEUE_STAT_SIZE                             (IRO[45].size)
#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
        (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
#define TSTORM_RDMA_QUEUE_STAT_SIZE                             (IRO[46].size)
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
        (IRO[43].base + ((pf_id) * IRO[43].m1))
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
        (IRO[44].base + ((pf_id) * IRO[44].m1))

static const struct iro iro_arr[47] = {
        {0x0, 0x0, 0x0, 0x0, 0x8},
        {0x4cb0, 0x78, 0x0, 0x0, 0x78},
        {0x6318, 0x20, 0x0, 0x0, 0x20},
        {0xb00, 0x8, 0x0, 0x0, 0x4},
        {0xa80, 0x8, 0x0, 0x0, 0x4},
        {0x0, 0x8, 0x0, 0x0, 0x2},
        {0x80, 0x8, 0x0, 0x0, 0x4},
        {0x84, 0x8, 0x0, 0x0, 0x2},
        {0x4bc0, 0x0, 0x0, 0x0, 0x78},
        {0x3df0, 0x0, 0x0, 0x0, 0x78},
        {0x29b0, 0x0, 0x0, 0x0, 0x78},
        {0x4c38, 0x0, 0x0, 0x0, 0x78},
        {0x4990, 0x0, 0x0, 0x0, 0x78},
        {0x7e48, 0x0, 0x0, 0x0, 0x78},
        {0xa28, 0x8, 0x0, 0x0, 0x8},
        {0x60f8, 0x10, 0x0, 0x0, 0x10},
        {0xb820, 0x30, 0x0, 0x0, 0x30},
        {0x95b8, 0x30, 0x0, 0x0, 0x30},
        {0x4b60, 0x80, 0x0, 0x0, 0x40},
        {0x1f8, 0x4, 0x0, 0x0, 0x4},
        {0x53a0, 0x80, 0x4, 0x0, 0x4},
        {0xc8f0, 0x0, 0x0, 0x0, 0x4},
        {0x4ba0, 0x80, 0x0, 0x0, 0x20},
        {0x8050, 0x40, 0x0, 0x0, 0x30},
        {0xe770, 0x60, 0x0, 0x0, 0x60},
        {0x2b48, 0x80, 0x0, 0x0, 0x38},
        {0xf188, 0x78, 0x0, 0x0, 0x78},
        {0x1f8, 0x4, 0x0, 0x0, 0x4},
        {0xacf0, 0x0, 0x0, 0x0, 0xf0},
        {0xade0, 0x8, 0x0, 0x0, 0x8},
        {0x1f8, 0x8, 0x0, 0x0, 0x8},
        {0xac0, 0x8, 0x0, 0x0, 0x8},
        {0x2578, 0x8, 0x0, 0x0, 0x8},
        {0x24f8, 0x8, 0x0, 0x0, 0x8},
        {0x0, 0x8, 0x0, 0x0, 0x8},
        {0x200, 0x10, 0x8, 0x0, 0x8},
        {0xb78, 0x10, 0x8, 0x0, 0x2},
        {0xd888, 0x38, 0x0, 0x0, 0x24},
        {0x12c38, 0x10, 0x0, 0x0, 0x8},
        {0x11aa0, 0x38, 0x0, 0x0, 0x18},
        {0xa8c0, 0x30, 0x0, 0x0, 0x10},
        {0x86f8, 0x28, 0x0, 0x0, 0x18},
        {0x101f8, 0x10, 0x0, 0x0, 0x10},
        {0xdd08, 0x48, 0x0, 0x0, 0x38},
        {0x10660, 0x20, 0x0, 0x0, 0x20},
        {0x2b80, 0x80, 0x0, 0x0, 0x10},
        {0x5000, 0x10, 0x0, 0x0, 0x10},
};

/* Runtime array offsets */
#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET        0
#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET        1
#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET        2
#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET        3
#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET        4
#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET        5
#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET        6
#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET        7
#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET        8
#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET        9
#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET        10
#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET        11
#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET        12
#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET        13
#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET        14
#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET        15
#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET  16
#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET       17
#define IGU_REG_PF_CONFIGURATION_RT_OFFSET      18
#define IGU_REG_VF_CONFIGURATION_RT_OFFSET      19
#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET       20
#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET       21
#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET    22
#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET   23
#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET     24
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE   736
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE   736
#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET        1497
#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE  736
#define CAU_REG_PI_MEMORY_RT_OFFSET     2233
#define CAU_REG_PI_MEMORY_RT_SIZE       4416
#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET    6649
#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET      6650
#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET      6651
#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
#define PRS_REG_SEARCH_TCP_RT_OFFSET    6654
#define PRS_REG_SEARCH_FCOE_RT_OFFSET   6655
#define PRS_REG_SEARCH_ROCE_RT_OFFSET   6656
#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET   6657
#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET   6658
#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET       6659
#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET     6660
#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET   6661
#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET      6662
#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET       6663
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
#define SRC_REG_FIRSTFREE_RT_OFFSET     6665
#define SRC_REG_FIRSTFREE_RT_SIZE       2
#define SRC_REG_LASTFREE_RT_OFFSET      6667
#define SRC_REG_LASTFREE_RT_SIZE        2
#define SRC_REG_COUNTFREE_RT_OFFSET     6669
#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET      6670
#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET        6671
#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET        6672
#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET  6673
#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET  6674
#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET        6676
#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET       6677
#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET        6678
#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET       6679
#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET        6680
#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET      6681
#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET       6682
#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET     6683
#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET      6684
#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET     6685
#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET      6686
#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET     6687
#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET      6688
#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET     6689
#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET   6690
#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET   6691
#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET       6692
#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET     6693
#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET     6694
#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET   6695
#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
#define PSWRQ2_REG_VF_BASE_RT_OFFSET    6698
#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET        6699
#define PSWRQ2_REG_WR_MBS0_RT_OFFSET    6700
#define PSWRQ2_REG_RD_MBS0_RT_OFFSET    6701
#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET      6702
#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET      6703
#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE   22000
#define PGLUE_REG_B_VF_BASE_RT_OFFSET   28704
#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET        28705
#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET   28706
#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET   28707
#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET      28708
#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET      28709
#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET      28710
#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28711
#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28712
#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28713
#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET     28714
#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET     28715
#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET        28716
#define TM_REG_CONFIG_CONN_MEM_RT_SIZE  416
#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET        29132
#define TM_REG_CONFIG_TASK_MEM_RT_SIZE  512
#define QM_REG_MAXPQSIZE_0_RT_OFFSET    29644
#define QM_REG_MAXPQSIZE_1_RT_OFFSET    29645
#define QM_REG_MAXPQSIZE_2_RT_OFFSET    29646
#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET       29647
#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET       29648
#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET       29649
#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET       29650
#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET       29651
#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET       29652
#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET       29653
#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET       29654
#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET       29655
#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET       29656
#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET      29657
#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET      29658
#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET      29659
#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET      29660
#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET      29661
#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET      29662
#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET      29663
#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET      29664
#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET      29665
#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET      29666
#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET      29667
#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET      29668
#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET      29669
#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET      29670
#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET      29671
#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET      29672
#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET      29673
#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET      29674
#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET      29675
#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET      29676
#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET      29677
#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET      29678
#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET      29679
#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET      29680
#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET      29681
#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET      29682
#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET      29683
#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET      29684
#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET      29685
#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET      29686
#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET      29687
#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET      29688
#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET      29689
#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET      29690
#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET      29691
#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET      29692
#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET      29693
#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET      29694
#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET      29695
#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET      29696
#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET      29697
#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET      29698
#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET      29699
#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET      29700
#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET      29701
#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET      29702
#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET      29703
#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET      29704
#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET      29705
#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET      29706
#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET      29707
#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET      29708
#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET      29709
#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET      29710
#define QM_REG_BASEADDROTHERPQ_RT_OFFSET        29711
#define QM_REG_BASEADDROTHERPQ_RT_SIZE  128
#define QM_REG_VOQCRDLINE_RT_OFFSET     29839
#define QM_REG_VOQCRDLINE_RT_SIZE       20
#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29859
#define QM_REG_VOQINITCRDLINE_RT_SIZE   20
#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET     29879
#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET     29880
#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET      29881
#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET    29882
#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET   29883
#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET        29884
#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET        29885
#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET        29886
#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET        29887
#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET        29888
#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET        29889
#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET        29890
#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET        29891
#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET        29892
#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET        29893
#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET       29894
#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET       29895
#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET       29896
#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET       29897
#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET       29898
#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET       29899
#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET    29900
#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET    29901
#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET    29902
#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET    29903
#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET       29904
#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET       29905
#define QM_REG_PQTX2PF_0_RT_OFFSET      29906
#define QM_REG_PQTX2PF_1_RT_OFFSET      29907
#define QM_REG_PQTX2PF_2_RT_OFFSET      29908
#define QM_REG_PQTX2PF_3_RT_OFFSET      29909
#define QM_REG_PQTX2PF_4_RT_OFFSET      29910
#define QM_REG_PQTX2PF_5_RT_OFFSET      29911
#define QM_REG_PQTX2PF_6_RT_OFFSET      29912
#define QM_REG_PQTX2PF_7_RT_OFFSET      29913
#define QM_REG_PQTX2PF_8_RT_OFFSET      29914
#define QM_REG_PQTX2PF_9_RT_OFFSET      29915
#define QM_REG_PQTX2PF_10_RT_OFFSET     29916
#define QM_REG_PQTX2PF_11_RT_OFFSET     29917
#define QM_REG_PQTX2PF_12_RT_OFFSET     29918
#define QM_REG_PQTX2PF_13_RT_OFFSET     29919
#define QM_REG_PQTX2PF_14_RT_OFFSET     29920
#define QM_REG_PQTX2PF_15_RT_OFFSET     29921
#define QM_REG_PQTX2PF_16_RT_OFFSET     29922
#define QM_REG_PQTX2PF_17_RT_OFFSET     29923
#define QM_REG_PQTX2PF_18_RT_OFFSET     29924
#define QM_REG_PQTX2PF_19_RT_OFFSET     29925
#define QM_REG_PQTX2PF_20_RT_OFFSET     29926
#define QM_REG_PQTX2PF_21_RT_OFFSET     29927
#define QM_REG_PQTX2PF_22_RT_OFFSET     29928
#define QM_REG_PQTX2PF_23_RT_OFFSET     29929
#define QM_REG_PQTX2PF_24_RT_OFFSET     29930
#define QM_REG_PQTX2PF_25_RT_OFFSET     29931
#define QM_REG_PQTX2PF_26_RT_OFFSET     29932
#define QM_REG_PQTX2PF_27_RT_OFFSET     29933
#define QM_REG_PQTX2PF_28_RT_OFFSET     29934
#define QM_REG_PQTX2PF_29_RT_OFFSET     29935
#define QM_REG_PQTX2PF_30_RT_OFFSET     29936
#define QM_REG_PQTX2PF_31_RT_OFFSET     29937
#define QM_REG_PQTX2PF_32_RT_OFFSET     29938
#define QM_REG_PQTX2PF_33_RT_OFFSET     29939
#define QM_REG_PQTX2PF_34_RT_OFFSET     29940
#define QM_REG_PQTX2PF_35_RT_OFFSET     29941
#define QM_REG_PQTX2PF_36_RT_OFFSET     29942
#define QM_REG_PQTX2PF_37_RT_OFFSET     29943
#define QM_REG_PQTX2PF_38_RT_OFFSET     29944
#define QM_REG_PQTX2PF_39_RT_OFFSET     29945
#define QM_REG_PQTX2PF_40_RT_OFFSET     29946
#define QM_REG_PQTX2PF_41_RT_OFFSET     29947
#define QM_REG_PQTX2PF_42_RT_OFFSET     29948
#define QM_REG_PQTX2PF_43_RT_OFFSET     29949
#define QM_REG_PQTX2PF_44_RT_OFFSET     29950
#define QM_REG_PQTX2PF_45_RT_OFFSET     29951
#define QM_REG_PQTX2PF_46_RT_OFFSET     29952
#define QM_REG_PQTX2PF_47_RT_OFFSET     29953
#define QM_REG_PQTX2PF_48_RT_OFFSET     29954
#define QM_REG_PQTX2PF_49_RT_OFFSET     29955
#define QM_REG_PQTX2PF_50_RT_OFFSET     29956
#define QM_REG_PQTX2PF_51_RT_OFFSET     29957
#define QM_REG_PQTX2PF_52_RT_OFFSET     29958
#define QM_REG_PQTX2PF_53_RT_OFFSET     29959
#define QM_REG_PQTX2PF_54_RT_OFFSET     29960
#define QM_REG_PQTX2PF_55_RT_OFFSET     29961
#define QM_REG_PQTX2PF_56_RT_OFFSET     29962
#define QM_REG_PQTX2PF_57_RT_OFFSET     29963
#define QM_REG_PQTX2PF_58_RT_OFFSET     29964
#define QM_REG_PQTX2PF_59_RT_OFFSET     29965
#define QM_REG_PQTX2PF_60_RT_OFFSET     29966
#define QM_REG_PQTX2PF_61_RT_OFFSET     29967
#define QM_REG_PQTX2PF_62_RT_OFFSET     29968
#define QM_REG_PQTX2PF_63_RT_OFFSET     29969
#define QM_REG_PQOTHER2PF_0_RT_OFFSET   29970
#define QM_REG_PQOTHER2PF_1_RT_OFFSET   29971
#define QM_REG_PQOTHER2PF_2_RT_OFFSET   29972
#define QM_REG_PQOTHER2PF_3_RT_OFFSET   29973
#define QM_REG_PQOTHER2PF_4_RT_OFFSET   29974
#define QM_REG_PQOTHER2PF_5_RT_OFFSET   29975
#define QM_REG_PQOTHER2PF_6_RT_OFFSET   29976
#define QM_REG_PQOTHER2PF_7_RT_OFFSET   29977
#define QM_REG_PQOTHER2PF_8_RT_OFFSET   29978
#define QM_REG_PQOTHER2PF_9_RT_OFFSET   29979
#define QM_REG_PQOTHER2PF_10_RT_OFFSET  29980
#define QM_REG_PQOTHER2PF_11_RT_OFFSET  29981
#define QM_REG_PQOTHER2PF_12_RT_OFFSET  29982
#define QM_REG_PQOTHER2PF_13_RT_OFFSET  29983
#define QM_REG_PQOTHER2PF_14_RT_OFFSET  29984
#define QM_REG_PQOTHER2PF_15_RT_OFFSET  29985
#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29986
#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29987
#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET    29988
#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET    29989
#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET      29990
#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET      29991
#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET      29992
#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET      29993
#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET      29994
#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET      29995
#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET      29996
#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET      29997
#define QM_REG_RLGLBLINCVAL_RT_OFFSET   29998
#define QM_REG_RLGLBLINCVAL_RT_SIZE     256
#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET       30254
#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
#define QM_REG_RLGLBLCRD_RT_OFFSET      30510
#define QM_REG_RLGLBLCRD_RT_SIZE        256
#define QM_REG_RLGLBLENABLE_RT_OFFSET   30766
#define QM_REG_RLPFPERIOD_RT_OFFSET     30767
#define QM_REG_RLPFPERIODTIMER_RT_OFFSET        30768
#define QM_REG_RLPFINCVAL_RT_OFFSET     30769
#define QM_REG_RLPFINCVAL_RT_SIZE       16
#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30785
#define QM_REG_RLPFUPPERBOUND_RT_SIZE   16
#define QM_REG_RLPFCRD_RT_OFFSET        30801
#define QM_REG_RLPFCRD_RT_SIZE  16
#define QM_REG_RLPFENABLE_RT_OFFSET     30817
#define QM_REG_RLPFVOQENABLE_RT_OFFSET  30818
#define QM_REG_WFQPFWEIGHT_RT_OFFSET    30819
#define QM_REG_WFQPFWEIGHT_RT_SIZE      16
#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET        30835
#define QM_REG_WFQPFUPPERBOUND_RT_SIZE  16
#define QM_REG_WFQPFCRD_RT_OFFSET       30851
#define QM_REG_WFQPFCRD_RT_SIZE 160
#define QM_REG_WFQPFENABLE_RT_OFFSET    31011
#define QM_REG_WFQVPENABLE_RT_OFFSET    31012
#define QM_REG_BASEADDRTXPQ_RT_OFFSET   31013
#define QM_REG_BASEADDRTXPQ_RT_SIZE     512
#define QM_REG_TXPQMAP_RT_OFFSET        31525
#define QM_REG_TXPQMAP_RT_SIZE  512
#define QM_REG_WFQVPWEIGHT_RT_OFFSET    32037
#define QM_REG_WFQVPWEIGHT_RT_SIZE      512
#define QM_REG_WFQVPCRD_RT_OFFSET       32549
#define QM_REG_WFQVPCRD_RT_SIZE 512
#define QM_REG_WFQVPMAP_RT_OFFSET       33061
#define QM_REG_WFQVPMAP_RT_SIZE 512
#define QM_REG_WFQPFCRD_MSB_RT_OFFSET   33573
#define QM_REG_WFQPFCRD_MSB_RT_SIZE     160
#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET       33733
#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33734
#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33735
#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33736
#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33737
#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET  33738
#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET      33739
#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET       33740
#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET  33744
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE    4
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET    33748
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE      4
#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET       33752
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33753
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE   32
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET    33785
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE      16
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET  33801
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE    16
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33817
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE   16
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET       33833
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET  33849
#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET        33850
#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET       33851
#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET       33852
#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET       33853
#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET   33854
#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET   33855
#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET   33856
#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET   33857
#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET        33858
#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET        33859
#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET        33860
#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET        33861
#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET    33862
#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33863
#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET       33864
#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET  33865
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET        33866
#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET   33867
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET    33868
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET        33869
#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET   33870
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET    33871
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET        33872
#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET   33873
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET    33874
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET        33875
#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET   33876
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET    33877
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET        33878
#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET   33879
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET    33880
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET        33881
#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET   33882
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET    33883
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET        33884
#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET   33885
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET    33886
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET        33887
#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET   33888
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET    33889
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET        33890
#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET   33891
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET    33892
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET        33893
#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET   33894
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET    33895
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET       33896
#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET  33897
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET   33898
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET       33899
#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET  33900
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET   33901
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET       33902
#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET  33903
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET   33904
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET       33905
#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET  33906
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET   33907
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET       33908
#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET  33909
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET   33910
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET       33911
#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET  33912
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET   33913
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET       33914
#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET  33915
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET   33916
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET       33917
#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET  33918
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET   33919
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET       33920
#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET  33921
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET   33922
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET       33923
#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET  33924
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET   33925
#define XCM_REG_CON_PHY_Q3_RT_OFFSET    33926

#define RUNTIME_ARRAY_SIZE 33927

/* The eth storm context for the Tstorm */
struct tstorm_eth_conn_st_ctx {
        __le32 reserved[4];
};

/* The eth storm context for the Pstorm */
struct pstorm_eth_conn_st_ctx {
        __le32 reserved[8];
};

/* The eth storm context for the Xstorm */
struct xstorm_eth_conn_st_ctx {
        __le32 reserved[60];
};

struct xstorm_eth_conn_ag_ctx {
        u8 reserved0;
        u8 eth_state;
        u8 flags0;
#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1
#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK           0x1
#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT          1
#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK           0x1
#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT          2
#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK        0x1
#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT       3