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19#ifndef __SH_ETH_H__
20#define __SH_ETH_H__
21
22#define CARDNAME "sh-eth"
23#define TX_TIMEOUT (5*HZ)
24#define TX_RING_SIZE 64
25#define RX_RING_SIZE 64
26#define TX_RING_MIN 64
27#define RX_RING_MIN 64
28#define TX_RING_MAX 1024
29#define RX_RING_MAX 1024
30#define PKT_BUF_SZ 1538
31#define SH_ETH_TSU_TIMEOUT_MS 500
32#define SH_ETH_TSU_CAM_ENTRIES 32
33
34enum {
35
36
37
38
39
40 EDSR = 0,
41 EDMR,
42 EDTRR,
43 EDRRR,
44 EESR,
45 EESIPR,
46 TDLAR,
47 TDFAR,
48 TDFXR,
49 TDFFR,
50 RDLAR,
51 RDFAR,
52 RDFXR,
53 RDFFR,
54 TRSCER,
55 RMFCR,
56 TFTR,
57 FDR,
58 RMCR,
59 EDOCR,
60 TFUCR,
61 RFOCR,
62 RMIIMODE,
63 FCFTR,
64 RPADIR,
65 TRIMD,
66 RBWAR,
67 TBRAR,
68
69
70 ECMR,
71 ECSR,
72 ECSIPR,
73 PIR,
74 PSR,
75 RDMLR,
76 PIPR,
77 RFLR,
78 IPGR,
79 APR,
80 MPR,
81 PFTCR,
82 PFRCR,
83 RFCR,
84 RFCF,
85 TPAUSER,
86 TPAUSECR,
87 BCFR,
88 BCFRR,
89 GECMR,
90 BCULR,
91 MAHR,
92 MALR,
93 TROCR,
94 CDCR,
95 LCCR,
96 CNDCR,
97 CEFCR,
98 FRECR,
99 TSFRCR,
100 TLFRCR,
101 CERCR,
102 CEECR,
103 MAFCR,
104 RTRATE,
105 CSMR,
106 RMII_MII,
107
108
109 ARSTR,
110 TSU_CTRST,
111 TSU_FWEN0,
112 TSU_FWEN1,
113 TSU_FCM,
114 TSU_BSYSL0,
115 TSU_BSYSL1,
116 TSU_PRISL0,
117 TSU_PRISL1,
118 TSU_FWSL0,
119 TSU_FWSL1,
120 TSU_FWSLC,
121 TSU_QTAG0,
122 TSU_QTAG1,
123 TSU_QTAGM0,
124 TSU_QTAGM1,
125 TSU_FWSR,
126 TSU_FWINMK,
127 TSU_ADQT0,
128 TSU_ADQT1,
129 TSU_VTAG0,
130 TSU_VTAG1,
131 TSU_ADSBSY,
132 TSU_TEN,
133 TSU_POST1,
134 TSU_POST2,
135 TSU_POST3,
136 TSU_POST4,
137 TSU_ADRH0,
138
139
140 TXNLCR0,
141 TXALCR0,
142 RXNLCR0,
143 RXALCR0,
144 FWNLCR0,
145 FWALCR0,
146 TXNLCR1,
147 TXALCR1,
148 RXNLCR1,
149 RXALCR1,
150 FWNLCR1,
151 FWALCR1,
152
153
154 SH_ETH_MAX_REGISTER_OFFSET,
155};
156
157enum {
158 SH_ETH_REG_GIGABIT,
159 SH_ETH_REG_FAST_RZ,
160 SH_ETH_REG_FAST_RCAR,
161 SH_ETH_REG_FAST_SH4,
162 SH_ETH_REG_FAST_SH3_SH2
163};
164
165
166#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
167#define SH_ETH_RX_ALIGN 32
168#else
169#define SH_ETH_RX_ALIGN 2
170#endif
171
172
173
174
175enum EDSR_BIT {
176 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
177};
178#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
179
180
181enum GECMR_BIT {
182 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
183};
184
185
186enum DMAC_M_BIT {
187 EDMR_EL = 0x40,
188 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
189 EDMR_SRST_GETHER = 0x03,
190 EDMR_SRST_ETHER = 0x01,
191};
192
193
194enum DMAC_T_BIT {
195 EDTRR_TRNS_GETHER = 0x03,
196 EDTRR_TRNS_ETHER = 0x01,
197};
198
199
200enum EDRRR_R_BIT {
201 EDRRR_R = 0x01,
202};
203
204
205enum TPAUSER_BIT {
206 TPAUSER_TPAUSE = 0x0000ffff,
207 TPAUSER_UNLIMITED = 0,
208};
209
210
211enum BCFR_BIT {
212 BCFR_RPAUSE = 0x0000ffff,
213 BCFR_UNLIMITED = 0,
214};
215
216
217enum PIR_BIT {
218 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
219};
220
221
222enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
223
224
225enum EESR_BIT {
226 EESR_TWB1 = 0x80000000,
227 EESR_TWB = 0x40000000,
228 EESR_TC1 = 0x20000000,
229 EESR_TUC = 0x10000000,
230 EESR_ROC = 0x08000000,
231 EESR_TABT = 0x04000000,
232 EESR_RABT = 0x02000000,
233 EESR_RFRMER = 0x01000000,
234 EESR_ADE = 0x00800000,
235 EESR_ECI = 0x00400000,
236 EESR_FTC = 0x00200000,
237 EESR_TDE = 0x00100000,
238 EESR_TFE = 0x00080000,
239 EESR_FRC = 0x00040000,
240 EESR_RDE = 0x00020000,
241 EESR_RFE = 0x00010000,
242 EESR_CND = 0x00000800,
243 EESR_DLC = 0x00000400,
244 EESR_CD = 0x00000200,
245 EESR_RTO = 0x00000100,
246 EESR_RMAF = 0x00000080,
247 EESR_CEEF = 0x00000040,
248 EESR_CELF = 0x00000020,
249 EESR_RRF = 0x00000010,
250 EESR_RTLF = 0x00000008,
251 EESR_RTSF = 0x00000004,
252 EESR_PRE = 0x00000002,
253 EESR_CERF = 0x00000001,
254};
255
256#define EESR_RX_CHECK (EESR_FRC | \
257 EESR_RMAF | \
258 EESR_RRF | \
259 EESR_RTLF | \
260 EESR_RTSF | \
261 EESR_PRE | \
262 EESR_CERF)
263
264#define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
265 EESR_RTO)
266#define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
267 EESR_RDE | EESR_RFRMER | EESR_ADE | \
268 EESR_TFE | EESR_TDE)
269
270
271enum EESIPR_BIT {
272 EESIPR_TWB1IP = 0x80000000,
273 EESIPR_TWBIP = 0x40000000,
274 EESIPR_TC1IP = 0x20000000,
275 EESIPR_TUCIP = 0x10000000,
276 EESIPR_ROCIP = 0x08000000,
277 EESIPR_TABTIP = 0x04000000,
278 EESIPR_RABTIP = 0x02000000,
279 EESIPR_RFCOFIP = 0x01000000,
280 EESIPR_ADEIP = 0x00800000,
281 EESIPR_ECIIP = 0x00400000,
282 EESIPR_FTCIP = 0x00200000,
283 EESIPR_TDEIP = 0x00100000,
284 EESIPR_TFUFIP = 0x00080000,
285 EESIPR_FRIP = 0x00040000,
286 EESIPR_RDEIP = 0x00020000,
287 EESIPR_RFOFIP = 0x00010000,
288 EESIPR_CNDIP = 0x00000800,
289 EESIPR_DLCIP = 0x00000400,
290 EESIPR_CDIP = 0x00000200,
291 EESIPR_TROIP = 0x00000100,
292 EESIPR_RMAFIP = 0x00000080,
293 EESIPR_CEEFIP = 0x00000040,
294 EESIPR_CELFIP = 0x00000020,
295 EESIPR_RRFIP = 0x00000010,
296 EESIPR_RTLFIP = 0x00000008,
297 EESIPR_RTSFIP = 0x00000004,
298 EESIPR_PREIP = 0x00000002,
299 EESIPR_CERFIP = 0x00000001,
300};
301
302
303enum RD_STS_BIT {
304 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
305 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
306 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
307 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
308 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
309 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
310 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
311 RD_RFS1 = 0x00000001,
312};
313#define RDF1ST RD_RFP1
314#define RDFEND RD_RFP0
315#define RD_RFP (RD_RFP1|RD_RFP0)
316
317
318enum RD_LEN_BIT {
319 RD_RFL = 0x0000ffff,
320 RD_RBL = 0xffff0000,
321};
322
323
324enum FCFTR_BIT {
325 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
326 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
327 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
328};
329#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
330#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
331
332
333enum TD_STS_BIT {
334 TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
335 TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
336 TD_TFE = 0x08000000, TD_TWBI = 0x04000000,
337};
338#define TDF1ST TD_TFP1
339#define TDFEND TD_TFP0
340#define TD_TFP (TD_TFP1|TD_TFP0)
341
342
343enum TD_LEN_BIT {
344 TD_TBL = 0xffff0000,
345};
346
347
348enum RMCR_BIT {
349 RMCR_RNC = 0x00000001,
350};
351
352
353enum FELIC_MODE_BIT {
354 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
355 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
356 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
357 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
358 ECMR_MPDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
359 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
360 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
361};
362
363
364enum ECSR_STATUS_BIT {
365 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
366 ECSR_LCHNG = 0x04,
367 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
368};
369
370#define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
371 ECSR_ICD | ECSIPR_MPDIP)
372
373
374enum ECSIPR_STATUS_MASK_BIT {
375 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
376 ECSIPR_LCHNGIP = 0x04,
377 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
378};
379
380#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
381 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
382
383
384enum APR_BIT {
385 APR_AP = 0x00000001,
386};
387
388
389enum MPR_BIT {
390 MPR_MP = 0x00000001,
391};
392
393
394enum DESC_I_BIT {
395 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
396 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
397 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
398 DESC_I_RINT1 = 0x0001,
399};
400
401#define DEFAULT_TRSCER_ERR_MASK (DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2)
402
403
404enum RPADIR_BIT {
405 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
406 RPADIR_PADR = 0x0003f,
407};
408
409
410#define DEFAULT_FDR_INIT 0x00000707
411
412
413enum ARSTR_BIT { ARSTR_ARST = 0x00000001, };
414
415
416enum TSU_FWEN0_BIT {
417 TSU_FWEN0_0 = 0x00000001,
418};
419
420
421enum TSU_ADSBSY_BIT {
422 TSU_ADSBSY_0 = 0x00000001,
423};
424
425
426enum TSU_TEN_BIT {
427 TSU_TEN_0 = 0x80000000,
428};
429
430
431enum TSU_FWSL0_BIT {
432 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
433 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
434 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
435};
436
437
438enum TSU_FWSLC_BIT {
439 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
440 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
441 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
442 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
443 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
444};
445
446
447#define TSU_VTAG_ENABLE 0x80000000
448#define TSU_VTAG_VID_MASK 0x00000fff
449
450
451
452
453struct sh_eth_txdesc {
454 u32 status;
455 u32 len;
456 u32 addr;
457 u32 pad0;
458} __aligned(2) __packed;
459
460
461
462
463struct sh_eth_rxdesc {
464 u32 status;
465 u32 len;
466 u32 addr;
467 u32 pad0;
468} __aligned(2) __packed;
469
470
471struct sh_eth_cpu_data {
472
473 void (*chip_reset)(struct net_device *ndev);
474 void (*set_duplex)(struct net_device *ndev);
475 void (*set_rate)(struct net_device *ndev);
476
477
478 int register_type;
479 u32 eesipr_value;
480
481
482 u32 ecsr_value;
483 u32 ecsipr_value;
484 u32 fdr_value;
485 u32 fcftr_value;
486 u32 rpadir_value;
487
488
489 u32 tx_check;
490 u32 eesr_err_check;
491
492
493 u32 trscer_err_mask;
494
495
496 unsigned long irq_flags;
497 unsigned no_psr:1;
498 unsigned apr:1;
499 unsigned mpr:1;
500 unsigned tpauser:1;
501 unsigned bculr:1;
502 unsigned tsu:1;
503 unsigned hw_swap:1;
504 unsigned rpadir:1;
505 unsigned no_trimd:1;
506 unsigned no_ade:1;
507 unsigned hw_checksum:1;
508 unsigned select_mii:1;
509 unsigned rmiimode:1;
510 unsigned rtrate:1;
511 unsigned magic:1;
512};
513
514struct sh_eth_private {
515 struct platform_device *pdev;
516 struct sh_eth_cpu_data *cd;
517 const u16 *reg_offset;
518 void __iomem *addr;
519 void __iomem *tsu_addr;
520 struct clk *clk;
521 u32 num_rx_ring;
522 u32 num_tx_ring;
523 dma_addr_t rx_desc_dma;
524 dma_addr_t tx_desc_dma;
525 struct sh_eth_rxdesc *rx_ring;
526 struct sh_eth_txdesc *tx_ring;
527 struct sk_buff **rx_skbuff;
528 struct sk_buff **tx_skbuff;
529 spinlock_t lock;
530 u32 cur_rx, dirty_rx;
531 u32 cur_tx, dirty_tx;
532 u32 rx_buf_sz;
533 struct napi_struct napi;
534 bool irq_enabled;
535
536 u32 phy_id;
537 struct mii_bus *mii_bus;
538 int link;
539 phy_interface_t phy_interface;
540 int msg_enable;
541 int speed;
542 int duplex;
543 int port;
544 int vlan_num_ids;
545
546 unsigned no_ether_link:1;
547 unsigned ether_link_active_low:1;
548 unsigned is_opened:1;
549 unsigned wol_enabled:1;
550};
551
552static inline void sh_eth_soft_swap(char *src, int len)
553{
554#ifdef __LITTLE_ENDIAN__
555 u32 *p = (u32 *)src;
556 u32 *maxp;
557 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
558
559 for (; p < maxp; p++)
560 *p = swab32(*p);
561#endif
562}
563
564static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
565 int enum_index)
566{
567 return mdp->tsu_addr + mdp->reg_offset[enum_index];
568}
569
570static inline void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
571 int enum_index)
572{
573 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
574}
575
576static inline u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
577{
578 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
579}
580
581#endif
582