1#ifndef B43_H_
2#define B43_H_
3
4#include <linux/kernel.h>
5#include <linux/spinlock.h>
6#include <linux/interrupt.h>
7#include <linux/hw_random.h>
8#include <linux/bcma/bcma.h>
9#include <linux/ssb/ssb.h>
10#include <linux/completion.h>
11#include <net/mac80211.h>
12
13#include "debugfs.h"
14#include "leds.h"
15#include "rfkill.h"
16#include "bus.h"
17#include "lo.h"
18#include "phy_common.h"
19
20
21#ifdef CONFIG_B43_DEBUG
22# define B43_DEBUG 1
23#else
24# define B43_DEBUG 0
25#endif
26
27
28#define B43_MMIO_DMA0_REASON 0x20
29#define B43_MMIO_DMA0_IRQ_MASK 0x24
30#define B43_MMIO_DMA1_REASON 0x28
31#define B43_MMIO_DMA1_IRQ_MASK 0x2C
32#define B43_MMIO_DMA2_REASON 0x30
33#define B43_MMIO_DMA2_IRQ_MASK 0x34
34#define B43_MMIO_DMA3_REASON 0x38
35#define B43_MMIO_DMA3_IRQ_MASK 0x3C
36#define B43_MMIO_DMA4_REASON 0x40
37#define B43_MMIO_DMA4_IRQ_MASK 0x44
38#define B43_MMIO_DMA5_REASON 0x48
39#define B43_MMIO_DMA5_IRQ_MASK 0x4C
40#define B43_MMIO_MACCTL 0x120
41#define B43_MMIO_MACCMD 0x124
42#define B43_MMIO_GEN_IRQ_REASON 0x128
43#define B43_MMIO_GEN_IRQ_MASK 0x12C
44#define B43_MMIO_RAM_CONTROL 0x130
45#define B43_MMIO_RAM_DATA 0x134
46#define B43_MMIO_PS_STATUS 0x140
47#define B43_MMIO_RADIO_HWENABLED_HI 0x158
48#define B43_MMIO_MAC_HW_CAP 0x15C
49#define B43_MMIO_SHM_CONTROL 0x160
50#define B43_MMIO_SHM_DATA 0x164
51#define B43_MMIO_SHM_DATA_UNALIGNED 0x166
52#define B43_MMIO_XMITSTAT_0 0x170
53#define B43_MMIO_XMITSTAT_1 0x174
54#define B43_MMIO_REV3PLUS_TSF_LOW 0x180
55#define B43_MMIO_REV3PLUS_TSF_HIGH 0x184
56#define B43_MMIO_TSF_CFP_REP 0x188
57#define B43_MMIO_TSF_CFP_START 0x18C
58#define B43_MMIO_TSF_CFP_MAXDUR 0x190
59
60
61#define B43_MMIO_DMA32_BASE0 0x200
62#define B43_MMIO_DMA32_BASE1 0x220
63#define B43_MMIO_DMA32_BASE2 0x240
64#define B43_MMIO_DMA32_BASE3 0x260
65#define B43_MMIO_DMA32_BASE4 0x280
66#define B43_MMIO_DMA32_BASE5 0x2A0
67
68#define B43_MMIO_DMA64_BASE0 0x200
69#define B43_MMIO_DMA64_BASE1 0x240
70#define B43_MMIO_DMA64_BASE2 0x280
71#define B43_MMIO_DMA64_BASE3 0x2C0
72#define B43_MMIO_DMA64_BASE4 0x300
73#define B43_MMIO_DMA64_BASE5 0x340
74
75
76#define B43_MMIO_PIO_BASE0 0x300
77#define B43_MMIO_PIO_BASE1 0x310
78#define B43_MMIO_PIO_BASE2 0x320
79#define B43_MMIO_PIO_BASE3 0x330
80#define B43_MMIO_PIO_BASE4 0x340
81#define B43_MMIO_PIO_BASE5 0x350
82#define B43_MMIO_PIO_BASE6 0x360
83#define B43_MMIO_PIO_BASE7 0x370
84
85#define B43_MMIO_PIO11_BASE0 0x200
86#define B43_MMIO_PIO11_BASE1 0x240
87#define B43_MMIO_PIO11_BASE2 0x280
88#define B43_MMIO_PIO11_BASE3 0x2C0
89#define B43_MMIO_PIO11_BASE4 0x300
90#define B43_MMIO_PIO11_BASE5 0x340
91
92#define B43_MMIO_RADIO24_CONTROL 0x3D8
93#define B43_MMIO_RADIO24_DATA 0x3DA
94#define B43_MMIO_PHY_VER 0x3E0
95#define B43_MMIO_PHY_RADIO 0x3E2
96#define B43_MMIO_PHY0 0x3E6
97#define B43_MMIO_ANTENNA 0x3E8
98#define B43_MMIO_CHANNEL 0x3F0
99#define B43_MMIO_CHANNEL_EXT 0x3F4
100#define B43_MMIO_RADIO_CONTROL 0x3F6
101#define B43_MMIO_RADIO_DATA_HIGH 0x3F8
102#define B43_MMIO_RADIO_DATA_LOW 0x3FA
103#define B43_MMIO_PHY_CONTROL 0x3FC
104#define B43_MMIO_PHY_DATA 0x3FE
105#define B43_MMIO_MACFILTER_CONTROL 0x420
106#define B43_MMIO_MACFILTER_DATA 0x422
107#define B43_MMIO_RCMTA_COUNT 0x43C
108#define B43_MMIO_PSM_PHY_HDR 0x492
109#define B43_MMIO_RADIO_HWENABLED_LO 0x49A
110#define B43_MMIO_GPIO_CONTROL 0x49C
111#define B43_MMIO_GPIO_MASK 0x49E
112#define B43_MMIO_TXE0_CTL 0x500
113#define B43_MMIO_TXE0_AUX 0x502
114#define B43_MMIO_TXE0_TS_LOC 0x504
115#define B43_MMIO_TXE0_TIME_OUT 0x506
116#define B43_MMIO_TXE0_WM_0 0x508
117#define B43_MMIO_TXE0_WM_1 0x50A
118#define B43_MMIO_TXE0_PHYCTL 0x50C
119#define B43_MMIO_TXE0_STATUS 0x50E
120#define B43_MMIO_TXE0_MMPLCP0 0x510
121#define B43_MMIO_TXE0_MMPLCP1 0x512
122#define B43_MMIO_TXE0_PHYCTL1 0x514
123#define B43_MMIO_XMTFIFODEF 0x520
124#define B43_MMIO_XMTFIFO_FRAME_CNT 0x522
125#define B43_MMIO_XMTFIFO_BYTE_CNT 0x524
126#define B43_MMIO_XMTFIFO_HEAD 0x526
127#define B43_MMIO_XMTFIFO_RD_PTR 0x528
128#define B43_MMIO_XMTFIFO_WR_PTR 0x52A
129#define B43_MMIO_XMTFIFODEF1 0x52C
130#define B43_MMIO_XMTFIFOCMD 0x540
131#define B43_MMIO_XMTFIFOFLUSH 0x542
132#define B43_MMIO_XMTFIFOTHRESH 0x544
133#define B43_MMIO_XMTFIFORDY 0x546
134#define B43_MMIO_XMTFIFOPRIRDY 0x548
135#define B43_MMIO_XMTFIFORQPRI 0x54A
136#define B43_MMIO_XMTTPLATETXPTR 0x54C
137#define B43_MMIO_XMTTPLATEPTR 0x550
138#define B43_MMIO_SMPL_CLCT_STRPTR 0x552
139#define B43_MMIO_SMPL_CLCT_STPPTR 0x554
140#define B43_MMIO_SMPL_CLCT_CURPTR 0x556
141#define B43_MMIO_XMTTPLATEDATALO 0x560
142#define B43_MMIO_XMTTPLATEDATAHI 0x562
143#define B43_MMIO_XMTSEL 0x568
144#define B43_MMIO_XMTTXCNT 0x56A
145#define B43_MMIO_XMTTXSHMADDR 0x56C
146#define B43_MMIO_TSF_CFP_START_LOW 0x604
147#define B43_MMIO_TSF_CFP_START_HIGH 0x606
148#define B43_MMIO_TSF_CFP_PRETBTT 0x612
149#define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E
150#define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630
151#define B43_MMIO_TSF_0 0x632
152#define B43_MMIO_TSF_1 0x634
153#define B43_MMIO_TSF_2 0x636
154#define B43_MMIO_TSF_3 0x638
155#define B43_MMIO_RNG 0x65A
156#define B43_MMIO_IFSSLOT 0x684
157#define B43_MMIO_IFSCTL 0x688
158#define B43_MMIO_IFSSTAT 0x690
159#define B43_MMIO_IFSMEDBUSYCTL 0x692
160#define B43_MMIO_IFTXDUR 0x694
161#define B43_MMIO_IFSCTL_USE_EDCF 0x0004
162#define B43_MMIO_POWERUP_DELAY 0x6A8
163#define B43_MMIO_BTCOEX_CTL 0x6B4
164#define B43_MMIO_BTCOEX_STAT 0x6B6
165#define B43_MMIO_BTCOEX_TXCTL 0x6B8
166#define B43_MMIO_WEPCTL 0x7C0
167
168
169#define B43_BFL_BTCOEXIST 0x0001
170#define B43_BFL_PACTRL 0x0002
171#define B43_BFL_AIRLINEMODE 0x0004
172#define B43_BFL_RSSI 0x0008
173#define B43_BFL_ENETSPI 0x0010
174#define B43_BFL_XTAL_NOSLOW 0x0020
175#define B43_BFL_CCKHIPWR 0x0040
176#define B43_BFL_ENETADM 0x0080
177#define B43_BFL_ENETVLAN 0x0100
178#define B43_BFL_AFTERBURNER 0x0200
179#define B43_BFL_NOPCI 0x0400
180#define B43_BFL_FEM 0x0800
181#define B43_BFL_EXTLNA 0x1000
182#define B43_BFL_HGPA 0x2000
183#define B43_BFL_BTCMOD 0x4000
184#define B43_BFL_ALTIQ 0x8000
185
186
187#define B43_BFH_NOPA 0x0001
188#define B43_BFH_RSSIINV 0x0002
189#define B43_BFH_PAREF 0x0004
190#define B43_BFH_3TSWITCH 0x0008
191
192#define B43_BFH_PHASESHIFT 0x0010
193#define B43_BFH_BUCKBOOST 0x0020
194#define B43_BFH_FEM_BT 0x0040
195
196#define B43_BFH_NOCBUCK 0x0080
197#define B43_BFH_PALDO 0x0200
198#define B43_BFH_EXTLNA_5GHZ 0x1000
199
200
201#define B43_BFL2_RXBB_INT_REG_DIS 0x0001
202#define B43_BFL2_APLL_WAR 0x0002
203#define B43_BFL2_TXPWRCTRL_EN 0x0004
204#define B43_BFL2_2X4_DIV 0x0008
205#define B43_BFL2_5G_PWRGAIN 0x0010
206#define B43_BFL2_PCIEWAR_OVR 0x0020
207#define B43_BFL2_CAESERS_BRD 0x0040
208#define B43_BFL2_BTC3WIRE 0x0080
209#define B43_BFL2_SKWRKFEM_BRD 0x0100
210#define B43_BFL2_SPUR_WAR 0x0200
211#define B43_BFL2_GPLL_WAR 0x0400
212#define B43_BFL2_SINGLEANT_CCK 0x1000
213#define B43_BFL2_2G_SPUR_WAR 0x2000
214
215
216#define B43_BFH2_GPLL_WAR2 0x0001
217#define B43_BFH2_IPALVLSHIFT_3P3 0x0002
218#define B43_BFH2_INTERNDET_TXIQCAL 0x0004
219#define B43_BFH2_XTALBUFOUTEN 0x0008
220
221
222#define B43_GPIO_CONTROL 0x6c
223
224
225enum {
226 B43_SHM_UCODE,
227 B43_SHM_SHARED,
228 B43_SHM_SCRATCH,
229 B43_SHM_HW,
230 B43_SHM_RCMTA,
231};
232
233#define B43_SHM_AUTOINC_R 0x0200
234#define B43_SHM_AUTOINC_W 0x0100
235#define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
236 B43_SHM_AUTOINC_W)
237
238
239#define B43_SHM_SH_WLCOREREV 0x0016
240#define B43_SHM_SH_PCTLWDPOS 0x0008
241#define B43_SHM_SH_RXPADOFF 0x0034
242#define B43_SHM_SH_FWCAPA 0x0042
243#define B43_SHM_SH_PHYVER 0x0050
244#define B43_SHM_SH_PHYTYPE 0x0052
245#define B43_SHM_SH_ANTSWAP 0x005C
246#define B43_SHM_SH_HOSTF1 0x005E
247#define B43_SHM_SH_HOSTF2 0x0060
248#define B43_SHM_SH_HOSTF3 0x0062
249#define B43_SHM_SH_RFATT 0x0064
250#define B43_SHM_SH_RADAR 0x0066
251#define B43_SHM_SH_PHYTXNOI 0x006E
252#define B43_SHM_SH_RFRXSP1 0x0072
253#define B43_SHM_SH_HOSTF4 0x0078
254#define B43_SHM_SH_CHAN 0x00A0
255#define B43_SHM_SH_CHAN_5GHZ 0x0100
256#define B43_SHM_SH_CHAN_40MHZ 0x0200
257#define B43_SHM_SH_MACHW_L 0x00C0
258#define B43_SHM_SH_MACHW_H 0x00C2
259#define B43_SHM_SH_HOSTF5 0x00D4
260#define B43_SHM_SH_BCMCFIFOID 0x0108
261
262#define B43_SHM_SH_TSSI_CCK 0x0058
263#define B43_SHM_SH_TSSI_OFDM_A 0x0068
264#define B43_SHM_SH_TSSI_OFDM_G 0x0070
265#define B43_TSSI_MAX 0x7F
266
267#define B43_SHM_SH_SIZE01 0x0098
268#define B43_SHM_SH_SIZE23 0x009A
269#define B43_SHM_SH_SIZE45 0x009C
270#define B43_SHM_SH_SIZE67 0x009E
271
272#define B43_SHM_SH_JSSI0 0x0088
273#define B43_SHM_SH_JSSI1 0x008A
274#define B43_SHM_SH_JSSIAUX 0x008C
275
276#define B43_SHM_SH_DEFAULTIV 0x003C
277#define B43_SHM_SH_NRRXTRANS 0x003E
278#define B43_SHM_SH_KTP 0x0056
279#define B43_SHM_SH_TKIPTSCTTAK 0x0318
280#define B43_SHM_SH_KEYIDXBLOCK 0x05D4
281#define B43_SHM_SH_PSM 0x05F4
282
283#define B43_SHM_SH_EDCFSTAT 0x000E
284#define B43_SHM_SH_TXFCUR 0x0030
285#define B43_SHM_SH_EDCFQ 0x0240
286
287#define B43_SHM_SH_SLOTT 0x0010
288#define B43_SHM_SH_DTIMPER 0x0012
289#define B43_SHM_SH_NOSLPZNATDTIM 0x004C
290
291#define B43_SHM_SH_BT_BASE0 0x0068
292#define B43_SHM_SH_BTL0 0x0018
293#define B43_SHM_SH_BT_BASE1 0x0468
294#define B43_SHM_SH_BTL1 0x001A
295#define B43_SHM_SH_BTSFOFF 0x001C
296#define B43_SHM_SH_TIMBPOS 0x001E
297#define B43_SHM_SH_DTIMP 0x0012
298#define B43_SHM_SH_MCASTCOOKIE 0x00A8
299#define B43_SHM_SH_SFFBLIM 0x0044
300#define B43_SHM_SH_LFFBLIM 0x0046
301#define B43_SHM_SH_BEACPHYCTL 0x0054
302#define B43_SHM_SH_EXTNPHYCTL 0x00B0
303#define B43_SHM_SH_BCN_LI 0x00B6
304
305#define B43_SHM_SH_ACKCTSPHYCTL 0x0022
306
307#define B43_SHM_SH_PRSSID 0x0160
308#define B43_SHM_SH_PRSSIDLEN 0x0048
309#define B43_SHM_SH_PRTLEN 0x004A
310#define B43_SHM_SH_PRMAXTIME 0x0074
311#define B43_SHM_SH_PRPHYCTL 0x0188
312
313#define B43_SHM_SH_OFDMDIRECT 0x01C0
314#define B43_SHM_SH_OFDMBASIC 0x01E0
315#define B43_SHM_SH_CCKDIRECT 0x0200
316#define B43_SHM_SH_CCKBASIC 0x0220
317
318#define B43_SHM_SH_UCODEREV 0x0000
319#define B43_SHM_SH_UCODEPATCH 0x0002
320#define B43_SHM_SH_UCODEDATE 0x0004
321#define B43_SHM_SH_UCODETIME 0x0006
322#define B43_SHM_SH_UCODESTAT 0x0040
323#define B43_SHM_SH_UCODESTAT_INVALID 0
324#define B43_SHM_SH_UCODESTAT_INIT 1
325#define B43_SHM_SH_UCODESTAT_ACTIVE 2
326#define B43_SHM_SH_UCODESTAT_SUSP 3
327#define B43_SHM_SH_UCODESTAT_SLEEP 4
328#define B43_SHM_SH_MAXBFRAMES 0x0080
329#define B43_SHM_SH_SPUWKUP 0x0094
330#define B43_SHM_SH_PRETBTT 0x0096
331
332#define B43_SHM_SH_NPHY_TXIQW0 0x0700
333#define B43_SHM_SH_NPHY_TXIQW1 0x0702
334#define B43_SHM_SH_NPHY_TXIQW2 0x0704
335#define B43_SHM_SH_NPHY_TXIQW3 0x0706
336
337#define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708
338#define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E
339
340
341#define B43_SHM_SC_MINCONT 0x0003
342#define B43_SHM_SC_MAXCONT 0x0004
343#define B43_SHM_SC_CURCONT 0x0005
344#define B43_SHM_SC_SRLIMIT 0x0006
345#define B43_SHM_SC_LRLIMIT 0x0007
346#define B43_SHM_SC_DTIMC 0x0008
347#define B43_SHM_SC_BTL0LEN 0x0015
348#define B43_SHM_SC_BTL1LEN 0x0016
349#define B43_SHM_SC_SCFB 0x0017
350#define B43_SHM_SC_LCFB 0x0018
351
352
353#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
354#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
355
356
357#define B43_HF_ANTDIVHELP 0x000000000001ULL
358#define B43_HF_SYMW 0x000000000002ULL
359#define B43_HF_RXPULLW 0x000000000004ULL
360#define B43_HF_CCKBOOST 0x000000000008ULL
361#define B43_HF_BTCOEX 0x000000000010ULL
362#define B43_HF_GDCW 0x000000000020ULL
363#define B43_HF_OFDMPABOOST 0x000000000040ULL
364#define B43_HF_ACPR 0x000000000080ULL
365#define B43_HF_EDCF 0x000000000100ULL
366#define B43_HF_TSSIRPSMW 0x000000000200ULL
367#define B43_HF_20IN40IQW 0x000000000200ULL
368#define B43_HF_DSCRQ 0x000000000400ULL
369#define B43_HF_ACIW 0x000000000800ULL
370#define B43_HF_2060W 0x000000001000ULL
371#define B43_HF_RADARW 0x000000002000ULL
372#define B43_HF_USEDEFKEYS 0x000000004000ULL
373#define B43_HF_AFTERBURNER 0x000000008000ULL
374#define B43_HF_BT4PRIOCOEX 0x000000010000ULL
375#define B43_HF_FWKUP 0x000000020000ULL
376#define B43_HF_VCORECALC 0x000000040000ULL
377#define B43_HF_PCISCW 0x000000080000ULL
378#define B43_HF_4318TSSI 0x000000200000ULL
379#define B43_HF_FBCMCFIFO 0x000000400000ULL
380#define B43_HF_HWPCTL 0x000000800000ULL
381#define B43_HF_BTCOEXALT 0x000001000000ULL
382#define B43_HF_TXBTCHECK 0x000002000000ULL
383#define B43_HF_SKCFPUP 0x000004000000ULL
384#define B43_HF_N40W 0x000008000000ULL
385#define B43_HF_ANTSEL 0x000020000000ULL
386#define B43_HF_BT3COEXT 0x000020000000ULL
387#define B43_HF_BTCANT 0x000040000000ULL
388#define B43_HF_ANTSELEN 0x000100000000ULL
389#define B43_HF_ANTSELMODE 0x000200000000ULL
390#define B43_HF_MLADVW 0x001000000000ULL
391#define B43_HF_PR45960W 0x080000000000ULL
392
393
394#define B43_FWCAPA_HWCRYPTO 0x0001
395#define B43_FWCAPA_QOS 0x0002
396
397
398#define B43_MACFILTER_SELF 0x0000
399#define B43_MACFILTER_BSSID 0x0003
400
401
402#define B43_PCTL_IN 0xB0
403#define B43_PCTL_OUT 0xB4
404#define B43_PCTL_OUTENABLE 0xB8
405#define B43_PCTL_XTAL_POWERUP 0x40
406#define B43_PCTL_PLL_POWERDOWN 0x80
407
408
409#define B43_PCTL_CLK_FAST 0x00
410#define B43_PCTL_CLK_SLOW 0x01
411#define B43_PCTL_CLK_DYNAMIC 0x02
412
413#define B43_PCTL_FORCE_SLOW 0x0800
414#define B43_PCTL_FORCE_PLL 0x1000
415#define B43_PCTL_DYN_XTAL 0x2000
416
417
418#define B43_PHYTYPE_A 0x00
419#define B43_PHYTYPE_B 0x01
420#define B43_PHYTYPE_G 0x02
421#define B43_PHYTYPE_N 0x04
422#define B43_PHYTYPE_LP 0x05
423#define B43_PHYTYPE_SSLPN 0x06
424#define B43_PHYTYPE_HT 0x07
425#define B43_PHYTYPE_LCN 0x08
426#define B43_PHYTYPE_LCNXN 0x09
427#define B43_PHYTYPE_LCN40 0x0a
428#define B43_PHYTYPE_AC 0x0b
429
430
431#define B43_PHY_ILT_A_CTRL 0x0072
432#define B43_PHY_ILT_A_DATA1 0x0073
433#define B43_PHY_ILT_A_DATA2 0x0074
434#define B43_PHY_G_LO_CONTROL 0x0810
435#define B43_PHY_ILT_G_CTRL 0x0472
436#define B43_PHY_ILT_G_DATA1 0x0473
437#define B43_PHY_ILT_G_DATA2 0x0474
438#define B43_PHY_A_PCTL 0x007B
439#define B43_PHY_G_PCTL 0x0029
440#define B43_PHY_A_CRS 0x0029
441#define B43_PHY_RADIO_BITFIELD 0x0401
442#define B43_PHY_G_CRS 0x0429
443#define B43_PHY_NRSSILT_CTRL 0x0803
444#define B43_PHY_NRSSILT_DATA 0x0804
445
446
447#define B43_RADIOCTL_ID 0x01
448
449
450#define B43_MACCTL_ENABLED 0x00000001
451#define B43_MACCTL_PSM_RUN 0x00000002
452#define B43_MACCTL_PSM_JMP0 0x00000004
453#define B43_MACCTL_SHM_ENABLED 0x00000100
454#define B43_MACCTL_SHM_UPPER 0x00000200
455#define B43_MACCTL_IHR_ENABLED 0x00000400
456#define B43_MACCTL_PSM_DBG 0x00002000
457#define B43_MACCTL_GPOUTSMSK 0x0000C000
458#define B43_MACCTL_BE 0x00010000
459#define B43_MACCTL_INFRA 0x00020000
460#define B43_MACCTL_AP 0x00040000
461#define B43_MACCTL_RADIOLOCK 0x00080000
462#define B43_MACCTL_BEACPROMISC 0x00100000
463#define B43_MACCTL_KEEP_BADPLCP 0x00200000
464#define B43_MACCTL_PHY_LOCK 0x00200000
465#define B43_MACCTL_KEEP_CTL 0x00400000
466#define B43_MACCTL_KEEP_BAD 0x00800000
467#define B43_MACCTL_PROMISC 0x01000000
468#define B43_MACCTL_HWPS 0x02000000
469#define B43_MACCTL_AWAKE 0x04000000
470#define B43_MACCTL_CLOSEDNET 0x08000000
471#define B43_MACCTL_TBTTHOLD 0x10000000
472#define B43_MACCTL_DISCTXSTAT 0x20000000
473#define B43_MACCTL_DISCPMQ 0x40000000
474#define B43_MACCTL_GMODE 0x80000000
475
476
477#define B43_MACCMD_BEACON0_VALID 0x00000001
478#define B43_MACCMD_BEACON1_VALID 0x00000002
479#define B43_MACCMD_DFQ_VALID 0x00000004
480#define B43_MACCMD_CCA 0x00000008
481#define B43_MACCMD_BGNOISE 0x00000010
482
483
484#define B43_PSM_HDR_MAC_PHY_RESET 0x00000001
485#define B43_PSM_HDR_MAC_PHY_CLOCK_EN 0x00000002
486#define B43_PSM_HDR_MAC_PHY_FORCE_CLK 0x00000004
487
488
489#define B43_BCMA_CLKCTLST_80211_PLL_REQ 0x00000100
490#define B43_BCMA_CLKCTLST_PHY_PLL_REQ 0x00000200
491#define B43_BCMA_CLKCTLST_80211_PLL_ST 0x01000000
492#define B43_BCMA_CLKCTLST_PHY_PLL_ST 0x02000000
493
494
495#define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004
496#define B43_BCMA_IOCTL_PHY_RESET 0x00000008
497#define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010
498#define B43_BCMA_IOCTL_PLLREFSEL 0x00000020
499#define B43_BCMA_IOCTL_PHY_BW 0x000000C0
500#define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000
501#define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040
502#define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080
503#define B43_BCMA_IOCTL_PHY_BW_80MHZ 0x000000C0
504#define B43_BCMA_IOCTL_DAC 0x00000300
505#define B43_BCMA_IOCTL_GMODE 0x00002000
506
507
508#define B43_BCMA_IOST_2G_PHY 0x00000001
509#define B43_BCMA_IOST_5G_PHY 0x00000002
510#define B43_BCMA_IOST_FASTCLKA 0x00000004
511#define B43_BCMA_IOST_DUALB_PHY 0x00000008
512
513
514#define B43_TMSLOW_GMODE 0x20000000
515#define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000
516#define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000
517#define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000
518#define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000
519#define B43_TMSLOW_PLLREFSEL 0x00200000
520#define B43_TMSLOW_MACPHYCLKEN 0x00100000
521#define B43_TMSLOW_PHYRESET 0x00080000
522#define B43_TMSLOW_PHYCLKEN 0x00040000
523
524
525#define B43_TMSHIGH_DUALBAND_PHY 0x00080000
526#define B43_TMSHIGH_FCLOCK 0x00040000
527#define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000
528#define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000
529
530
531#define B43_IRQ_MAC_SUSPENDED 0x00000001
532#define B43_IRQ_BEACON 0x00000002
533#define B43_IRQ_TBTT_INDI 0x00000004
534#define B43_IRQ_BEACON_TX_OK 0x00000008
535#define B43_IRQ_BEACON_CANCEL 0x00000010
536#define B43_IRQ_ATIM_END 0x00000020
537#define B43_IRQ_PMQ 0x00000040
538#define B43_IRQ_PIO_WORKAROUND 0x00000100
539#define B43_IRQ_MAC_TXERR 0x00000200
540#define B43_IRQ_PHY_TXERR 0x00000800
541#define B43_IRQ_PMEVENT 0x00001000
542#define B43_IRQ_TIMER0 0x00002000
543#define B43_IRQ_TIMER1 0x00004000
544#define B43_IRQ_DMA 0x00008000
545#define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
546#define B43_IRQ_CCA_MEASURE_OK 0x00020000
547#define B43_IRQ_NOISESAMPLE_OK 0x00040000
548#define B43_IRQ_UCODE_DEBUG 0x08000000
549#define B43_IRQ_RFKILL 0x10000000
550#define B43_IRQ_TX_OK 0x20000000
551#define B43_IRQ_PHY_G_CHANGED 0x40000000
552#define B43_IRQ_TIMEOUT 0x80000000
553
554#define B43_IRQ_ALL 0xFFFFFFFF
555#define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
556 B43_IRQ_ATIM_END | \
557 B43_IRQ_PMQ | \
558 B43_IRQ_MAC_TXERR | \
559 B43_IRQ_PHY_TXERR | \
560 B43_IRQ_DMA | \
561 B43_IRQ_TXFIFO_FLUSH_OK | \
562 B43_IRQ_NOISESAMPLE_OK | \
563 B43_IRQ_UCODE_DEBUG | \
564 B43_IRQ_RFKILL | \
565 B43_IRQ_TX_OK)
566
567
568#define B43_DEBUGIRQ_REASON_REG 63
569
570#define B43_DEBUGIRQ_PANIC 0
571#define B43_DEBUGIRQ_DUMP_SHM 1
572#define B43_DEBUGIRQ_DUMP_REGS 2
573#define B43_DEBUGIRQ_MARKER 3
574#define B43_DEBUGIRQ_ACK 0xFFFF
575
576
577#define B43_MARKER_ID_REG 2
578#define B43_MARKER_LINE_REG 3
579
580
581#define B43_FWPANIC_REASON_REG 3
582
583#define B43_FWPANIC_DIE 0
584#define B43_FWPANIC_RESTART 1
585
586
587#define B43_WATCHDOG_REG 1
588
589
590
591
592#define B43_CCK_RATE_1MB 0x02
593#define B43_CCK_RATE_2MB 0x04
594#define B43_CCK_RATE_5MB 0x0B
595#define B43_CCK_RATE_11MB 0x16
596#define B43_OFDM_RATE_6MB 0x0C
597#define B43_OFDM_RATE_9MB 0x12
598#define B43_OFDM_RATE_12MB 0x18
599#define B43_OFDM_RATE_18MB 0x24
600#define B43_OFDM_RATE_24MB 0x30
601#define B43_OFDM_RATE_36MB 0x48
602#define B43_OFDM_RATE_48MB 0x60
603#define B43_OFDM_RATE_54MB 0x6C
604
605#define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
606
607#define B43_DEFAULT_SHORT_RETRY_LIMIT 7
608#define B43_DEFAULT_LONG_RETRY_LIMIT 4
609
610#define B43_PHY_TX_BADNESS_LIMIT 1000
611
612
613#define B43_SEC_KEYSIZE 16
614
615#define B43_NR_GROUP_KEYS 4
616
617#define B43_NR_PAIRWISE_KEYS 50
618
619enum {
620 B43_SEC_ALGO_NONE = 0,
621 B43_SEC_ALGO_WEP40,
622 B43_SEC_ALGO_TKIP,
623 B43_SEC_ALGO_AES,
624 B43_SEC_ALGO_WEP104,
625 B43_SEC_ALGO_AES_LEGACY,
626};
627
628struct b43_dmaring;
629
630
631#define B43_FW_TYPE_UCODE 'u'
632#define B43_FW_TYPE_PCM 'p'
633#define B43_FW_TYPE_IV 'i'
634struct b43_fw_header {
635
636 u8 type;
637
638 u8 ver;
639 u8 __padding[2];
640
641
642 __be32 size;
643} __packed;
644
645
646#define B43_IV_OFFSET_MASK 0x7FFF
647#define B43_IV_32BIT 0x8000
648struct b43_iv {
649 __be16 offset_size;
650 union {
651 __be16 d16;
652 __be32 d32;
653 } data __packed;
654} __packed;
655
656
657
658struct b43_dma {
659 struct b43_dmaring *tx_ring_AC_BK;
660 struct b43_dmaring *tx_ring_AC_BE;
661 struct b43_dmaring *tx_ring_AC_VI;
662 struct b43_dmaring *tx_ring_AC_VO;
663 struct b43_dmaring *tx_ring_mcast;
664
665 struct b43_dmaring *rx_ring;
666
667 u32 translation;
668 bool translation_in_low;
669 bool parity;
670};
671
672struct b43_pio_txqueue;
673struct b43_pio_rxqueue;
674
675
676struct b43_pio {
677 struct b43_pio_txqueue *tx_queue_AC_BK;
678 struct b43_pio_txqueue *tx_queue_AC_BE;
679 struct b43_pio_txqueue *tx_queue_AC_VI;
680 struct b43_pio_txqueue *tx_queue_AC_VO;
681 struct b43_pio_txqueue *tx_queue_mcast;
682
683 struct b43_pio_rxqueue *rx_queue;
684};
685
686
687struct b43_noise_calculation {
688 bool calculation_running;
689 u8 nr_samples;
690 s8 samples[8][4];
691};
692
693struct b43_stats {
694 u8 link_noise;
695};
696
697struct b43_key {
698
699
700
701 struct ieee80211_key_conf *keyconf;
702 u8 algorithm;
703};
704
705
706#define B43_QOS_QUEUE_NUM 4
707#define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
708 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
709#define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
710#define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
711#define B43_QOS_VIDEO B43_QOS_PARAMS(2)
712#define B43_QOS_VOICE B43_QOS_PARAMS(3)
713
714
715#define B43_NR_QOSPARAMS 16
716enum {
717 B43_QOSPARAM_TXOP = 0,
718 B43_QOSPARAM_CWMIN,
719 B43_QOSPARAM_CWMAX,
720 B43_QOSPARAM_CWCUR,
721 B43_QOSPARAM_AIFS,
722 B43_QOSPARAM_BSLOTS,
723 B43_QOSPARAM_REGGAP,
724 B43_QOSPARAM_STATUS,
725};
726
727
728struct b43_qos_params {
729
730 struct ieee80211_tx_queue_params p;
731};
732
733struct b43_wl;
734
735
736enum b43_firmware_file_type {
737 B43_FWTYPE_PROPRIETARY,
738 B43_FWTYPE_OPENSOURCE,
739 B43_NR_FWTYPES,
740};
741
742
743struct b43_request_fw_context {
744
745 struct b43_wldev *dev;
746
747 const struct firmware *blob;
748
749 enum b43_firmware_file_type req_type;
750
751 char errors[B43_NR_FWTYPES][128];
752
753 char fwname[64];
754
755
756 int fatal_failure;
757};
758
759
760struct b43_firmware_file {
761 const char *filename;
762 const struct firmware *data;
763
764
765
766
767
768
769 enum b43_firmware_file_type type;
770};
771
772enum b43_firmware_hdr_format {
773 B43_FW_HDR_598,
774 B43_FW_HDR_410,
775 B43_FW_HDR_351,
776};
777
778
779struct b43_firmware {
780
781 struct b43_firmware_file ucode;
782
783 struct b43_firmware_file pcm;
784
785 struct b43_firmware_file initvals;
786
787 struct b43_firmware_file initvals_band;
788
789
790 u16 rev;
791
792 u16 patch;
793
794
795 enum b43_firmware_hdr_format hdr_format;
796
797
798
799 bool opensource;
800
801
802
803 bool pcm_request_failed;
804};
805
806enum b43_band {
807 B43_BAND_2G = 0,
808 B43_BAND_5G_LO = 1,
809 B43_BAND_5G_MI = 2,
810 B43_BAND_5G_HI = 3,
811};
812
813
814enum {
815 B43_STAT_UNINIT = 0,
816 B43_STAT_INITIALIZED = 1,
817 B43_STAT_STARTED = 2,
818};
819#define b43_status(wldev) atomic_read(&(wldev)->__init_status)
820#define b43_set_status(wldev, stat) do { \
821 atomic_set(&(wldev)->__init_status, (stat)); \
822 smp_wmb(); \
823 } while (0)
824
825
826struct b43_wldev {
827 struct b43_bus_dev *dev;
828 struct b43_wl *wl;
829
830 struct completion fw_load_complete;
831
832
833
834 atomic_t __init_status;
835
836 bool bad_frames_preempt;
837 bool dfq_valid;
838 bool radio_hw_enable;
839 bool qos_enabled;
840 bool hwcrypto_enabled;
841 bool use_pio;
842
843
844 struct b43_phy phy;
845
846 union {
847
848 struct b43_dma dma;
849
850 struct b43_pio pio;
851 };
852
853
854 bool __using_pio_transfers;
855
856
857 struct b43_stats stats;
858
859
860 u32 irq_reason;
861 u32 dma_reason[6];
862
863 u32 irq_mask;
864
865
866 struct b43_noise_calculation noisecalc;
867
868 int mac_suspended;
869
870
871 struct delayed_work periodic_work;
872 unsigned int periodic_state;
873
874 struct work_struct restart_work;
875
876
877 u16 ktp;
878 struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS];
879
880
881 struct b43_firmware fw;
882
883
884 struct list_head list;
885
886
887#ifdef CONFIG_B43_DEBUG
888 struct b43_dfsentry *dfsentry;
889 unsigned int irq_count;
890 unsigned int irq_bit_count[32];
891 unsigned int tx_count;
892 unsigned int rx_count;
893#endif
894};
895
896
897struct b43_wl {
898
899 struct b43_wldev *current_dev;
900
901 struct ieee80211_hw *hw;
902
903
904 struct mutex mutex;
905
906
907 spinlock_t hardirq_lock;
908
909
910
911 bool hw_registred;
912
913
914
915
916
917 struct ieee80211_vif *vif;
918
919 u8 mac_addr[ETH_ALEN];
920
921 u8 bssid[ETH_ALEN];
922
923 int if_type;
924
925 bool operating;
926
927 unsigned int filter_flags;
928
929 struct ieee80211_low_level_stats ieee_stats;
930
931#ifdef CONFIG_B43_HWRNG
932 struct hwrng rng;
933 bool rng_initialized;
934 char rng_name[30 + 1];
935#endif
936
937 bool radiotap_enabled;
938 bool radio_enabled;
939
940
941 struct sk_buff *current_beacon;
942 bool beacon0_uploaded;
943 bool beacon1_uploaded;
944 bool beacon_templates_virgin;
945 struct work_struct beacon_update_trigger;
946 spinlock_t beacon_lock;
947
948
949 struct b43_qos_params qos_params[B43_QOS_QUEUE_NUM];
950
951
952
953
954 struct work_struct txpower_adjust_work;
955
956
957 struct work_struct tx_work;
958
959
960 struct sk_buff_head tx_queue[B43_QOS_QUEUE_NUM];
961
962
963 bool tx_queue_stopped[B43_QOS_QUEUE_NUM];
964
965
966 struct work_struct firmware_load;
967
968
969 struct b43_leds leds;
970
971
972 u8 pio_scratchspace[118] __attribute__((__aligned__(8)));
973 u8 pio_tailspace[4] __attribute__((__aligned__(8)));
974};
975
976static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
977{
978 return hw->priv;
979}
980
981static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
982{
983 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
984 return ssb_get_drvdata(ssb_dev);
985}
986
987
988static inline int b43_is_mode(struct b43_wl *wl, int type)
989{
990 return (wl->operating && wl->if_type == type);
991}
992
993
994
995
996
997static inline enum nl80211_band b43_current_band(struct b43_wl *wl)
998{
999 return wl->hw->conf.chandef.chan->band;
1000}
1001
1002static inline int b43_bus_may_powerdown(struct b43_wldev *wldev)
1003{
1004 return wldev->dev->bus_may_powerdown(wldev->dev);
1005}
1006static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl)
1007{
1008 return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl);
1009}
1010static inline int b43_device_is_enabled(struct b43_wldev *wldev)
1011{
1012 return wldev->dev->device_is_enabled(wldev->dev);
1013}
1014static inline void b43_device_enable(struct b43_wldev *wldev,
1015 u32 core_specific_flags)
1016{
1017 wldev->dev->device_enable(wldev->dev, core_specific_flags);
1018}
1019static inline void b43_device_disable(struct b43_wldev *wldev,
1020 u32 core_specific_flags)
1021{
1022 wldev->dev->device_disable(wldev->dev, core_specific_flags);
1023}
1024
1025static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
1026{
1027 return dev->dev->read16(dev->dev, offset);
1028}
1029
1030static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
1031{
1032 dev->dev->write16(dev->dev, offset, value);
1033}
1034
1035
1036static inline void b43_write16f(struct b43_wldev *dev, u16 offset, u16 value)
1037{
1038 b43_write16(dev, offset, value);
1039#if defined(CONFIG_BCM47XX_BCMA)
1040 if (dev->dev->flush_writes)
1041 b43_read16(dev, offset);
1042#endif
1043}
1044
1045static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask,
1046 u16 set)
1047{
1048 b43_write16(dev, offset, (b43_read16(dev, offset) & mask) | set);
1049}
1050
1051static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
1052{
1053 return dev->dev->read32(dev->dev, offset);
1054}
1055
1056static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
1057{
1058 dev->dev->write32(dev->dev, offset, value);
1059}
1060
1061static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask,
1062 u32 set)
1063{
1064 b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set);
1065}
1066
1067static inline void b43_block_read(struct b43_wldev *dev, void *buffer,
1068 size_t count, u16 offset, u8 reg_width)
1069{
1070 dev->dev->block_read(dev->dev, buffer, count, offset, reg_width);
1071}
1072
1073static inline void b43_block_write(struct b43_wldev *dev, const void *buffer,
1074 size_t count, u16 offset, u8 reg_width)
1075{
1076 dev->dev->block_write(dev->dev, buffer, count, offset, reg_width);
1077}
1078
1079static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
1080{
1081 return dev->__using_pio_transfers;
1082}
1083
1084
1085__printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...);
1086__printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...);
1087__printf(2, 3) void b43warn(struct b43_wl *wl, const char *fmt, ...);
1088__printf(2, 3) void b43dbg(struct b43_wl *wl, const char *fmt, ...);
1089
1090
1091
1092
1093#if B43_DEBUG
1094# define B43_WARN_ON(x) WARN_ON(x)
1095#else
1096static inline bool __b43_warn_on_dummy(bool x) { return x; }
1097# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
1098#endif
1099
1100
1101#define INT_TO_Q52(i) ((i) << 2)
1102
1103#define Q52_TO_INT(q52) ((q52) >> 2)
1104
1105#define Q52_FMT "%u.%u"
1106#define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
1107
1108#endif
1109