LXR linux/drivers/pci/dwc/pci-keystone-dw.c

   1/*
   2 * Designware application register space functions for Keystone PCI controller
   3 *
   4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
   5 *              http://www.ti.com
   6 *
   7 * Author: Murali Karicheri <m-karicheri2@ti.com>
   8 *
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as
  12 * published by the Free Software Foundation.
  13 */
  14
  15#include <linux/irq.h>
  16#include <linux/irqdomain.h>
  17#include <linux/irqreturn.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/of_pci.h>
  21#include <linux/pci.h>
  22#include <linux/platform_device.h>
  23
  24#include "pcie-designware.h"
  25#include "pci-keystone.h"
  26
  27/* Application register defines */
  28#define LTSSM_EN_VAL                    1
  29#define LTSSM_STATE_MASK                0x1f
  30#define LTSSM_STATE_L0                  0x11
  31#define DBI_CS2_EN_VAL                  0x20
  32#define OB_XLAT_EN_VAL                  2
  33
  34/* Application registers */
  35#define CMD_STATUS                      0x004
  36#define CFG_SETUP                       0x008
  37#define OB_SIZE                         0x030
  38#define CFG_PCIM_WIN_SZ_IDX             3
  39#define CFG_PCIM_WIN_CNT                32
  40#define SPACE0_REMOTE_CFG_OFFSET        0x1000
  41#define OB_OFFSET_INDEX(n)              (0x200 + (8 * n))
  42#define OB_OFFSET_HI(n)                 (0x204 + (8 * n))
  43
  44/* IRQ register defines */
  45#define IRQ_EOI                         0x050
  46#define IRQ_STATUS                      0x184
  47#define IRQ_ENABLE_SET                  0x188
  48#define IRQ_ENABLE_CLR                  0x18c
  49
  50#define MSI_IRQ                         0x054
  51#define MSI0_IRQ_STATUS                 0x104
  52#define MSI0_IRQ_ENABLE_SET             0x108
  53#define MSI0_IRQ_ENABLE_CLR             0x10c
  54#define IRQ_STATUS                      0x184
  55#define MSI_IRQ_OFFSET                  4
  56
  57/* Error IRQ bits */
  58#define ERR_AER         BIT(5)  /* ECRC error */
  59#define ERR_AXI         BIT(4)  /* AXI tag lookup fatal error */
  60#define ERR_CORR        BIT(3)  /* Correctable error */
  61#define ERR_NONFATAL    BIT(2)  /* Non-fatal error */
  62#define ERR_FATAL       BIT(1)  /* Fatal error */
  63#define ERR_SYS         BIT(0)  /* System (fatal, non-fatal, or correctable) */
  64#define ERR_IRQ_ALL     (ERR_AER | ERR_AXI | ERR_CORR | \
  65                         ERR_NONFATAL | ERR_FATAL | ERR_SYS)
  66#define ERR_FATAL_IRQ   (ERR_FATAL | ERR_AXI)
  67#define ERR_IRQ_STATUS_RAW              0x1c0
  68#define ERR_IRQ_STATUS                  0x1c4
  69#define ERR_IRQ_ENABLE_SET              0x1c8
  70#define ERR_IRQ_ENABLE_CLR              0x1cc
  71
  72/* Config space registers */
  73#define DEBUG0                          0x728
  74
  75#define to_keystone_pcie(x)     dev_get_drvdata((x)->dev)
  76
  77static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
  78                                             u32 *bit_pos)
  79{
  80        *reg_offset = offset % 8;
  81        *bit_pos = offset >> 3;
  82}
  83
  84phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
  85{
  86        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  87        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  88
  89        return ks_pcie->app.start + MSI_IRQ;
  90}
  91
  92static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
  93{
  94        return readl(ks_pcie->va_app_base + offset);
  95}
  96
  97static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
  98{
  99        writel(val, ks_pcie->va_app_base + offset);
 100}
 101
 102void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
 103{
 104        struct dw_pcie *pci = ks_pcie->pci;
 105        struct pcie_port *pp = &pci->pp;
 106        struct device *dev = pci->dev;
 107        u32 pending, vector;
 108        int src, virq;
 109
 110        pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
 111
 112        /*
 113         * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
 114         * shows 1, 9, 17, 25 and so forth
 115         */
 116        for (src = 0; src < 4; src++) {
 117                if (BIT(src) & pending) {
 118                        vector = offset + (src << 3);
 119                        virq = irq_linear_revmap(pp->irq_domain, vector);
 120                        dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
 121                                src, vector, virq);
 122                        generic_handle_irq(virq);
 123                }
 124        }
 125}
 126
 127static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
 128{
 129        u32 offset, reg_offset, bit_pos;
 130        struct keystone_pcie *ks_pcie;
 131        struct msi_desc *msi;
 132        struct pcie_port *pp;
 133        struct dw_pcie *pci;
 134
 135        msi = irq_data_get_msi_desc(d);
 136        pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
 137        pci = to_dw_pcie_from_pp(pp);
 138        ks_pcie = to_keystone_pcie(pci);
 139        offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 140        update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
 141
 142        ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
 143                         BIT(bit_pos));
 144        ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
 145}
 146
 147void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
 148{
 149        u32 reg_offset, bit_pos;
 150        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 151        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 152
 153        update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
 154        ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
 155                         BIT(bit_pos));
 156}
 157
 158void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
 159{
 160        u32 reg_offset, bit_pos;
 161        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 162        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 163
 164        update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
 165        ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
 166                         BIT(bit_pos));
 167}
 168
 169static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
 170{
 171        struct keystone_pcie *ks_pcie;
 172        struct msi_desc *msi;
 173        struct pcie_port *pp;
 174        struct dw_pcie *pci;
 175        u32 offset;
 176
 177        msi = irq_data_get_msi_desc(d);
 178        pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
 179        pci = to_dw_pcie_from_pp(pp);
 180        ks_pcie = to_keystone_pcie(pci);
 181        offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 182
 183        /* Mask the end point if PVM implemented */
 184        if (IS_ENABLED(CONFIG_PCI_MSI)) {
 185                if (msi->msi_attrib.maskbit)
 186                        pci_msi_mask_irq(d);
 187        }
 188
 189        ks_dw_pcie_msi_clear_irq(pp, offset);
 190}
 191
 192static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
 193{
 194        struct keystone_pcie *ks_pcie;
 195        struct msi_desc *msi;
 196        struct pcie_port *pp;
 197        struct dw_pcie *pci;
 198        u32 offset;
 199
 200        msi = irq_data_get_msi_desc(d);
 201        pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
 202        pci = to_dw_pcie_from_pp(pp);
 203        ks_pcie = to_keystone_pcie(pci);
 204        offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
 205
 206        /* Mask the end point if PVM implemented */
 207        if (IS_ENABLED(CONFIG_PCI_MSI)) {
 208                if (msi->msi_attrib.maskbit)
 209                        pci_msi_unmask_irq(d);
 210        }
 211
 212        ks_dw_pcie_msi_set_irq(pp, offset);
 213}
 214
 215static struct irq_chip ks_dw_pcie_msi_irq_chip = {
 216        .name = "Keystone-PCIe-MSI-IRQ",
 217        .irq_ack = ks_dw_pcie_msi_irq_ack,
 218        .irq_mask = ks_dw_pcie_msi_irq_mask,
 219        .irq_unmask = ks_dw_pcie_msi_irq_unmask,
 220};
 221
 222static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
 223                              irq_hw_number_t hwirq)
 224{
 225        irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
 226                                 handle_level_irq);
 227        irq_set_chip_data(irq, domain->host_data);
 228
 229        return 0;
 230}
 231
 232static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
 233        .map = ks_dw_pcie_msi_map,
 234};
 235
 236int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
 237{
 238        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 239        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 240        struct device *dev = pci->dev;
 241        int i;
 242
 243        pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
 244                                        MAX_MSI_IRQS,
 245                                        &ks_dw_pcie_msi_domain_ops,
 246                                        chip);
 247        if (!pp->irq_domain) {
 248                dev_err(dev, "irq domain init failed\n");
 249                return -ENXIO;
 250        }
 251
 252        for (i = 0; i < MAX_MSI_IRQS; i++)
 253                irq_create_mapping(pp->irq_domain, i);
 254
 255        return 0;
 256}
 257
 258void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
 259{
 260        int i;
 261
 262        for (i = 0; i < MAX_LEGACY_IRQS; i++)
 263                ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
 264}
 265
 266void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
 267{
 268        struct dw_pcie *pci = ks_pcie->pci;
 269        struct device *dev = pci->dev;
 270        u32 pending;
 271        int virq;
 272
 273        pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
 274
 275        if (BIT(0) & pending) {
 276                virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
 277                dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
 278                generic_handle_irq(virq);
 279        }
 280
 281        /* EOI the INTx interrupt */
 282        ks_dw_app_writel(ks_pcie, IRQ_EOI, offset);
 283}
 284
 285void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
 286{
 287        ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
 288}
 289
 290irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
 291{
 292        u32 status;
 293
 294        status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
 295        if (!status)
 296                return IRQ_NONE;
 297
 298        if (status & ERR_FATAL_IRQ)
 299                dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
 300                        status);
 301
 302        /* Ack the IRQ; status bits are RW1C */
 303        ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
 304        return IRQ_HANDLED;
 305}
 306
 307static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
 308{
 309}
 310
 311static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
 312{
 313}
 314
 315static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
 316{
 317}
 318
 319static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
 320        .name = "Keystone-PCI-Legacy-IRQ",
 321        .irq_ack = ks_dw_pcie_ack_legacy_irq,
 322        .irq_mask = ks_dw_pcie_mask_legacy_irq,
 323        .irq_unmask = ks_dw_pcie_unmask_legacy_irq,
 324};
 325
 326static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
 327                                unsigned int irq, irq_hw_number_t hw_irq)
 328{
 329        irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
 330                                 handle_level_irq);
 331        irq_set_chip_data(irq, d->host_data);
 332
 333        return 0;
 334}
 335
 336static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
 337        .map = ks_dw_pcie_init_legacy_irq_map,
 338        .xlate = irq_domain_xlate_onetwocell,
 339};
 340
 341/**
 342 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
 343 * registers
 344 *
 345 * Since modification of dbi_cs2 involves different clock domain, read the
 346 * status back to ensure the transition is complete.
 347 */
 348static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
 349{
 350        u32 val;
 351
 352        val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 353        ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
 354
 355        do {
 356                val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 357        } while (!(val & DBI_CS2_EN_VAL));
 358}
 359
 360/**
 361 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
 362 *
 363 * Since modification of dbi_cs2 involves different clock domain, read the
 364 * status back to ensure the transition is complete.
 365 */
 366static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
 367{
 368        u32 val;
 369
 370        val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 371        ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
 372
 373        do {
 374                val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 375        } while (val & DBI_CS2_EN_VAL);
 376}
 377
 378void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
 379{
 380        struct dw_pcie *pci = ks_pcie->pci;
 381        struct pcie_port *pp = &pci->pp;
 382        u32 start = pp->mem->start, end = pp->mem->end;
 383        int i, tr_size;
 384        u32 val;
 385
 386        /* Disable BARs for inbound access */
 387        ks_dw_pcie_set_dbi_mode(ks_pcie);
 388        dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
 389        dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
 390        ks_dw_pcie_clear_dbi_mode(ks_pcie);
 391
 392        /* Set outbound translation size per window division */
 393        ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
 394
 395        tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
 396
 397        /* Using Direct 1:1 mapping of RC <-> PCI memory space */
 398        for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
 399                ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
 400                ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
 401                start += tr_size;
 402        }
 403
 404        /* Enable OB translation */
 405        val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 406        ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
 407}
 408
 409/**
 410 * ks_pcie_cfg_setup() - Set up configuration space address for a device
 411 *
 412 * @ks_pcie: ptr to keystone_pcie structure
 413 * @bus: Bus number the device is residing on
 414 * @devfn: device, function number info
 415 *
 416 * Forms and returns the address of configuration space mapped in PCIESS
 417 * address space 0.  Also configures CFG_SETUP for remote configuration space
 418 * access.
 419 *
 420 * The address space has two regions to access configuration - local and remote.
 421 * We access local region for bus 0 (as RC is attached on bus 0) and remote
 422 * region for others with TYPE 1 access when bus > 1.  As for device on bus = 1,
 423 * we will do TYPE 0 access as it will be on our secondary bus (logical).
 424 * CFG_SETUP is needed only for remote configuration access.
 425 */
 426static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
 427                                       unsigned int devfn)
 428{
 429        u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
 430        struct dw_pcie *pci = ks_pcie->pci;
 431        struct pcie_port *pp = &pci->pp;
 432        u32 regval;
 433
 434        if (bus == 0)
 435                return pci->dbi_base;
 436
 437        regval = (bus << 16) | (device << 8) | function;
 438
 439        /*
 440         * Since Bus#1 will be a virtual bus, we need to have TYPE0
 441         * access only.
 442         * TYPE 1
 443         */
 444        if (bus != 1)
 445                regval |= BIT(24);
 446
 447        ks_dw_app_writel(ks_pcie, CFG_SETUP, regval);
 448        return pp->va_cfg0_base;
 449}
 450
 451int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 452                             unsigned int devfn, int where, int size, u32 *val)
 453{
 454        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 455        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 456        u8 bus_num = bus->number;
 457        void __iomem *addr;
 458
 459        addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
 460
 461        return dw_pcie_read(addr + where, size, val);
 462}
 463
 464int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 465                             unsigned int devfn, int where, int size, u32 val)
 466{
 467        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 468        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 469        u8 bus_num = bus->number;
 470        void __iomem *addr;
 471
 472        addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
 473
 474        return dw_pcie_write(addr + where, size, val);
 475}
 476
 477/**
 478 * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
 479 *
 480 * This sets BAR0 to enable inbound access for MSI_IRQ register
 481 */
 482void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
 483{
 484        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 485        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 486
 487        /* Configure and set up BAR0 */
 488        ks_dw_pcie_set_dbi_mode(ks_pcie);
 489
 490        /* Enable BAR0 */
 491        dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
 492        dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
 493
 494        ks_dw_pcie_clear_dbi_mode(ks_pcie);
 495
 496         /*
 497          * For BAR0, just setting bus address for inbound writes (MSI) should
 498          * be sufficient.  Use physical address to avoid any conflicts.
 499          */
 500        dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
 501}
 502
 503/**
 504 * ks_dw_pcie_link_up() - Check if link up
 505 */
 506int ks_dw_pcie_link_up(struct dw_pcie *pci)
 507{
 508        u32 val;
 509
 510        val = dw_pcie_readl_dbi(pci, DEBUG0);
 511        return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
 512}
 513
 514void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
 515{
 516        u32 val;
 517
 518        /* Disable Link training */
 519        val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 520        val &= ~LTSSM_EN_VAL;
 521        ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
 522
 523        /* Initiate Link Training */
 524        val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
 525        ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
 526}
 527
 528/**
 529 * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
 530 *
 531 * Ioremap the register resources, initialize legacy irq domain
 532 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
 533 * PCI host controller.
 534 */
 535int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
 536                                struct device_node *msi_intc_np)
 537{
 538        struct dw_pcie *pci = ks_pcie->pci;
 539        struct pcie_port *pp = &pci->pp;
 540        struct device *dev = pci->dev;
 541        struct platform_device *pdev = to_platform_device(dev);
 542        struct resource *res;
 543
 544        /* Index 0 is the config reg. space address */
 545        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 546        pci->dbi_base = devm_ioremap_resource(dev, res);
 547        if (IS_ERR(pci->dbi_base))
 548                return PTR_ERR(pci->dbi_base);
 549
 550        /*
 551         * We set these same and is used in pcie rd/wr_other_conf
 552         * functions
 553         */
 554        pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
 555        pp->va_cfg1_base = pp->va_cfg0_base;
 556
 557        /* Index 1 is the application reg. space address */
 558        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 559        ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
 560        if (IS_ERR(ks_pcie->va_app_base))
 561                return PTR_ERR(ks_pcie->va_app_base);
 562
 563        ks_pcie->app = *res;
 564
 565        /* Create legacy IRQ domain */
 566        ks_pcie->legacy_irq_domain =
 567                        irq_domain_add_linear(ks_pcie->legacy_intc_np,
 568                                        MAX_LEGACY_IRQS,
 569                                        &ks_dw_pcie_legacy_irq_domain_ops,
 570                                        NULL);
 571        if (!ks_pcie->legacy_irq_domain) {
 572                dev_err(dev, "Failed to add irq domain for legacy irqs\n");
 573                return -EINVAL;
 574        }
 575
 576        return dw_pcie_host_init(pp);
 577}
 578