LXR linux/drivers/staging/comedi/drivers/daqboard2000.c

   1/*
   2 * comedi/drivers/daqboard2000.c
   3 * hardware driver for IOtech DAQboard/2000
   4 *
   5 * COMEDI - Linux Control and Measurement Device Interface
   6 * Copyright (C) 1999 Anders Blomdell <anders.blomdell@control.lth.se>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 */
  18/*
  19 * Driver: daqboard2000
  20 * Description: IOTech DAQBoard/2000
  21 * Author: Anders Blomdell <anders.blomdell@control.lth.se>
  22 * Status: works
  23 * Updated: Mon, 14 Apr 2008 15:28:52 +0100
  24 * Devices: [IOTech] DAQBoard/2000 (daqboard2000)
  25 *
  26 * Much of the functionality of this driver was determined from reading
  27 * the source code for the Windows driver.
  28 *
  29 * The FPGA on the board requires firmware, which is available from
  30 * http://www.comedi.org in the comedi_nonfree_firmware tarball.
  31 *
  32 * Configuration options: not applicable, uses PCI auto config
  33 */
  34/*
  35 * This card was obviously never intended to leave the Windows world,
  36 * since it lacked all kind of hardware documentation (except for cable
  37 * pinouts, plug and pray has something to catch up with yet).
  38 *
  39 * With some help from our swedish distributor, we got the Windows sourcecode
  40 * for the card, and here are the findings so far.
  41 *
  42 * 1. A good document that describes the PCI interface chip is 9080db-106.pdf
  43 *    available from http://www.plxtech.com/products/io/pci9080
  44 *
  45 * 2. The initialization done so far is:
  46 *      a. program the FPGA (windows code sans a lot of error messages)
  47 *      b.
  48 *
  49 * 3. Analog out seems to work OK with DAC's disabled, if DAC's are enabled,
  50 *    you have to output values to all enabled DAC's until result appears, I
  51 *    guess that it has something to do with pacer clocks, but the source
  52 *    gives me no clues. I'll keep it simple so far.
  53 *
  54 * 4. Analog in.
  55 *    Each channel in the scanlist seems to be controlled by four
  56 *    control words:
  57 *
  58 *      Word0:
  59 *        +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  60 *        ! | | | ! | | | ! | | | ! | | | !
  61 *        +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  62 *
  63 *      Word1:
  64 *        +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  65 *        ! | | | ! | | | ! | | | ! | | | !
  66 *        +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  67 *         |             |       | | | | |
  68 *         +------+------+       | | | | +-- Digital input (??)
  69 *                |              | | | +---- 10 us settling time
  70 *                |              | | +------ Suspend acquisition (last to scan)
  71 *                |              | +-------- Simultaneous sample and hold
  72 *                |              +---------- Signed data format
  73 *                +------------------------- Correction offset low
  74 *
  75 *      Word2:
  76 *        +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  77 *        ! | | | ! | | | ! | | | ! | | | !
  78 *        +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  79 *         |     | |     | | | | | |     |
  80 *         +-----+ +--+--+ +++ +++ +--+--+
  81 *            |       |     |   |     +----- Expansion channel
  82 *            |       |     |   +----------- Expansion gain
  83 *            |       |     +--------------- Channel (low)
  84 *            |       +--------------------- Correction offset high
  85 *            +----------------------------- Correction gain low
  86 *      Word3:
  87 *        +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  88 *        ! | | | ! | | | ! | | | ! | | | !
  89 *        +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  90 *         |             | | | |   | | | |
  91 *         +------+------+ | | +-+-+ | | +-- Low bank enable
  92 *                |        | |   |   | +---- High bank enable
  93 *                |        | |   |   +------ Hi/low select
  94 *                |        | |   +---------- Gain (1,?,2,4,8,16,32,64)
  95 *                |        | +-------------- differential/single ended
  96 *                |        +---------------- Unipolar
  97 *                +------------------------- Correction gain high
  98 *
  99 * 999. The card seems to have an incredible amount of capabilities, but
 100 *      trying to reverse engineer them from the Windows source is beyond my
 101 *      patience.
 102 *
 103 */
 104
 105#include <linux/module.h>
 106#include <linux/delay.h>
 107#include <linux/interrupt.h>
 108
 109#include "../comedi_pci.h"
 110
 111#include "8255.h"
 112#include "plx9080.h"
 113
 114#define DB2K_FIRMWARE           "daqboard2000_firmware.bin"
 115
 116static const struct comedi_lrange db2k_ai_range = {
 117        13, {
 118                BIP_RANGE(10),
 119                BIP_RANGE(5),
 120                BIP_RANGE(2.5),
 121                BIP_RANGE(1.25),
 122                BIP_RANGE(0.625),
 123                BIP_RANGE(0.3125),
 124                BIP_RANGE(0.156),
 125                UNI_RANGE(10),
 126                UNI_RANGE(5),
 127                UNI_RANGE(2.5),
 128                UNI_RANGE(1.25),
 129                UNI_RANGE(0.625),
 130                UNI_RANGE(0.3125)
 131        }
 132};
 133
 134/*
 135 * Register Memory Map
 136 */
 137#define DB2K_REG_ACQ_CONTROL                    0x00            /* u16 (w) */
 138#define DB2K_REG_ACQ_STATUS                     0x00            /* u16 (r) */
 139#define DB2K_REG_ACQ_SCAN_LIST_FIFO             0x02            /* u16 */
 140#define DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW        0x04            /* u32 */
 141#define DB2K_REG_ACQ_SCAN_COUNTER               0x08            /* u16 */
 142#define DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH       0x0a            /* u16 */
 143#define DB2K_REG_ACQ_TRIGGER_COUNT              0x0c            /* u16 */
 144#define DB2K_REG_ACQ_RESULTS_FIFO               0x10            /* u16 */
 145#define DB2K_REG_ACQ_RESULTS_SHADOW             0x14            /* u16 */
 146#define DB2K_REG_ACQ_ADC_RESULT                 0x18            /* u16 */
 147#define DB2K_REG_DAC_SCAN_COUNTER               0x1c            /* u16 */
 148#define DB2K_REG_DAC_CONTROL                    0x20            /* u16 (w) */
 149#define DB2K_REG_DAC_STATUS                     0x20            /* u16 (r) */
 150#define DB2K_REG_DAC_FIFO                       0x24            /* s16 */
 151#define DB2K_REG_DAC_PACER_CLOCK_DIV            0x2a            /* u16 */
 152#define DB2K_REG_REF_DACS                       0x2c            /* u16 */
 153#define DB2K_REG_DIO_CONTROL                    0x30            /* u16 */
 154#define DB2K_REG_P3_HSIO_DATA                   0x32            /* s16 */
 155#define DB2K_REG_P3_CONTROL                     0x34            /* u16 */
 156#define DB2K_REG_CAL_EEPROM_CONTROL             0x36            /* u16 */
 157#define DB2K_REG_DAC_SETTING(x)                 (0x38 + (x) * 2) /* s16 */
 158#define DB2K_REG_DIO_P2_EXP_IO_8_BIT            0x40            /* s16 */
 159#define DB2K_REG_COUNTER_TIMER_CONTROL          0x80            /* u16 */
 160#define DB2K_REG_COUNTER_INPUT(x)               (0x88 + (x) * 2) /* s16 */
 161#define DB2K_REG_TIMER_DIV(x)                   (0xa0 + (x) * 2) /* u16 */
 162#define DB2K_REG_DMA_CONTROL                    0xb0            /* u16 */
 163#define DB2K_REG_TRIG_CONTROL                   0xb2            /* u16 */
 164#define DB2K_REG_CAL_EEPROM                     0xb8            /* u16 */
 165#define DB2K_REG_ACQ_DIGITAL_MARK               0xba            /* u16 */
 166#define DB2K_REG_TRIG_DACS                      0xbc            /* u16 */
 167#define DB2K_REG_DIO_P2_EXP_IO_16_BIT(x)        (0xc0 + (x) * 2) /* s16 */
 168
 169/* CPLD registers */
 170#define DB2K_REG_CPLD_STATUS                    0x1000          /* u16 (r) */
 171#define DB2K_REG_CPLD_WDATA                     0x1000          /* u16 (w) */
 172
 173/* Scan Sequencer programming */
 174#define DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST            0x0011
 175#define DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST             0x0010
 176
 177/* Prepare for acquisition */
 178#define DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO           0x0004
 179#define DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO             0x0002
 180#define DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE              0x0001
 181
 182/* Pacer Clock Control */
 183#define DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL             0x0030
 184#define DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL             0x0032
 185#define DB2K_ACQ_CONTROL_ADC_PACER_ENABLE               0x0031
 186#define DB2K_ACQ_CONTROL_ADC_PACER_ENABLE_DAC_PACER     0x0034
 187#define DB2K_ACQ_CONTROL_ADC_PACER_DISABLE              0x0030
 188#define DB2K_ACQ_CONTROL_ADC_PACER_NORMAL_MODE          0x0060
 189#define DB2K_ACQ_CONTROL_ADC_PACER_COMPATIBILITY_MODE   0x0061
 190#define DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL_OUT_ENABLE  0x0008
 191#define DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL_RISING      0x0100
 192
 193/* Acquisition status bits */
 194#define DB2K_ACQ_STATUS_RESULTS_FIFO_MORE_1_SAMPLE      0x0001
 195#define DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA           0x0002
 196#define DB2K_ACQ_STATUS_RESULTS_FIFO_OVERRUN            0x0004
 197#define DB2K_ACQ_STATUS_LOGIC_SCANNING                  0x0008
 198#define DB2K_ACQ_STATUS_CONFIG_PIPE_FULL                0x0010
 199#define DB2K_ACQ_STATUS_SCAN_LIST_FIFO_EMPTY            0x0020
 200#define DB2K_ACQ_STATUS_ADC_NOT_READY                   0x0040
 201#define DB2K_ACQ_STATUS_ARBITRATION_FAILURE             0x0080
 202#define DB2K_ACQ_STATUS_ADC_PACER_OVERRUN               0x0100
 203#define DB2K_ACQ_STATUS_DAC_PACER_OVERRUN               0x0200
 204
 205/* DAC status */
 206#define DB2K_DAC_STATUS_DAC_FULL                        0x0001
 207#define DB2K_DAC_STATUS_REF_BUSY                        0x0002
 208#define DB2K_DAC_STATUS_TRIG_BUSY                       0x0004
 209#define DB2K_DAC_STATUS_CAL_BUSY                        0x0008
 210#define DB2K_DAC_STATUS_DAC_BUSY(x)                     (0x0010 << (x))
 211
 212/* DAC control */
 213#define DB2K_DAC_CONTROL_ENABLE_BIT                     0x0001
 214#define DB2K_DAC_CONTROL_DATA_IS_SIGNED                 0x0002
 215#define DB2K_DAC_CONTROL_RESET_FIFO                     0x0004
 216#define DB2K_DAC_CONTROL_DAC_DISABLE(x)                 (0x0020 + ((x) << 4))
 217#define DB2K_DAC_CONTROL_DAC_ENABLE(x)                  (0x0021 + ((x) << 4))
 218#define DB2K_DAC_CONTROL_PATTERN_DISABLE                0x0060
 219#define DB2K_DAC_CONTROL_PATTERN_ENABLE                 0x0061
 220
 221/* Trigger Control */
 222#define DB2K_TRIG_CONTROL_TYPE_ANALOG                   0x0000
 223#define DB2K_TRIG_CONTROL_TYPE_TTL                      0x0010
 224#define DB2K_TRIG_CONTROL_EDGE_HI_LO                    0x0004
 225#define DB2K_TRIG_CONTROL_EDGE_LO_HI                    0x0000
 226#define DB2K_TRIG_CONTROL_LEVEL_ABOVE                   0x0000
 227#define DB2K_TRIG_CONTROL_LEVEL_BELOW                   0x0004
 228#define DB2K_TRIG_CONTROL_SENSE_LEVEL                   0x0002
 229#define DB2K_TRIG_CONTROL_SENSE_EDGE                    0x0000
 230#define DB2K_TRIG_CONTROL_ENABLE                        0x0001
 231#define DB2K_TRIG_CONTROL_DISABLE                       0x0000
 232
 233/* Reference Dac Selection */
 234#define DB2K_REF_DACS_SET                               0x0080
 235#define DB2K_REF_DACS_SELECT_POS_REF                    0x0100
 236#define DB2K_REF_DACS_SELECT_NEG_REF                    0x0000
 237
 238/* CPLD status bits */
 239#define DB2K_CPLD_STATUS_INIT                           0x0002
 240#define DB2K_CPLD_STATUS_TXREADY                        0x0004
 241#define DB2K_CPLD_VERSION_MASK                          0xf000
 242/* "New CPLD" signature. */
 243#define DB2K_CPLD_VERSION_NEW                           0x5000
 244
 245enum db2k_boardid {
 246        BOARD_DAQBOARD2000,
 247        BOARD_DAQBOARD2001
 248};
 249
 250struct db2k_boardtype {
 251        const char *name;
 252        bool has_2_ao:1;        /* false: 4 AO chans; true: 2 AO chans */
 253};
 254
 255static const struct db2k_boardtype db2k_boardtypes[] = {
 256        [BOARD_DAQBOARD2000] = {
 257                .name           = "daqboard2000",
 258                .has_2_ao       = true,
 259        },
 260        [BOARD_DAQBOARD2001] = {
 261                .name           = "daqboard2001",
 262        },
 263};
 264
 265struct db2k_private {
 266        void __iomem *plx;
 267};
 268
 269static void db2k_write_acq_scan_list_entry(struct comedi_device *dev, u16 entry)
 270{
 271        writew(entry & 0x00ff, dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO);
 272        writew((entry >> 8) & 0x00ff,
 273               dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO);
 274}
 275
 276static void db2k_setup_sampling(struct comedi_device *dev, int chan, int gain)
 277{
 278        u16 word0, word1, word2, word3;
 279
 280        /* Channel 0-7 diff, channel 8-23 single ended */
 281        word0 = 0;
 282        word1 = 0x0004;         /* Last scan */
 283        word2 = (chan << 6) & 0x00c0;
 284        switch (chan / 4) {
 285        case 0:
 286                word3 = 0x0001;
 287                break;
 288        case 1:
 289                word3 = 0x0002;
 290                break;
 291        case 2:
 292                word3 = 0x0005;
 293                break;
 294        case 3:
 295                word3 = 0x0006;
 296                break;
 297        case 4:
 298                word3 = 0x0041;
 299                break;
 300        case 5:
 301                word3 = 0x0042;
 302                break;
 303        default:
 304                word3 = 0;
 305                break;
 306        }
 307        /* These should be read from EEPROM */
 308        word2 |= 0x0800;        /* offset */
 309        word3 |= 0xc000;        /* gain */
 310        db2k_write_acq_scan_list_entry(dev, word0);
 311        db2k_write_acq_scan_list_entry(dev, word1);
 312        db2k_write_acq_scan_list_entry(dev, word2);
 313        db2k_write_acq_scan_list_entry(dev, word3);
 314}
 315
 316static int db2k_ai_status(struct comedi_device *dev, struct comedi_subdevice *s,
 317                          struct comedi_insn *insn, unsigned long context)
 318{
 319        unsigned int status;
 320
 321        status = readw(dev->mmio + DB2K_REG_ACQ_STATUS);
 322        if (status & context)
 323                return 0;
 324        return -EBUSY;
 325}
 326
 327static int db2k_ai_insn_read(struct comedi_device *dev,
 328                             struct comedi_subdevice *s,
 329                             struct comedi_insn *insn, unsigned int *data)
 330{
 331        int gain, chan;
 332        int ret;
 333        int i;
 334
 335        writew(DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO |
 336               DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO |
 337               DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE,
 338               dev->mmio + DB2K_REG_ACQ_CONTROL);
 339
 340        /*
 341         * If pacer clock is not set to some high value (> 10 us), we
 342         * risk multiple samples to be put into the result FIFO.
 343         */
 344        /* 1 second, should be long enough */
 345        writel(1000000, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW);
 346        writew(0, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH);
 347
 348        gain = CR_RANGE(insn->chanspec);
 349        chan = CR_CHAN(insn->chanspec);
 350
 351        /*
 352         * This doesn't look efficient.  I decided to take the conservative
 353         * approach when I did the insn conversion.  Perhaps it would be
 354         * better to have broken it completely, then someone would have been
 355         * forced to fix it.  --ds
 356         */
 357        for (i = 0; i < insn->n; i++) {
 358                db2k_setup_sampling(dev, chan, gain);
 359                /* Enable reading from the scanlist FIFO */
 360                writew(DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST,
 361                       dev->mmio + DB2K_REG_ACQ_CONTROL);
 362
 363                ret = comedi_timeout(dev, s, insn, db2k_ai_status,
 364                                     DB2K_ACQ_STATUS_CONFIG_PIPE_FULL);
 365                if (ret)
 366                        return ret;
 367
 368                writew(DB2K_ACQ_CONTROL_ADC_PACER_ENABLE,
 369                       dev->mmio + DB2K_REG_ACQ_CONTROL);
 370
 371                ret = comedi_timeout(dev, s, insn, db2k_ai_status,
 372                                     DB2K_ACQ_STATUS_LOGIC_SCANNING);
 373                if (ret)
 374                        return ret;
 375
 376                ret =
 377                comedi_timeout(dev, s, insn, db2k_ai_status,
 378                               DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA);
 379                if (ret)
 380                        return ret;
 381
 382                data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO);
 383                writew(DB2K_ACQ_CONTROL_ADC_PACER_DISABLE,
 384                       dev->mmio + DB2K_REG_ACQ_CONTROL);
 385                writew(DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST,
 386                       dev->mmio + DB2K_REG_ACQ_CONTROL);
 387        }
 388
 389        return i;
 390}
 391
 392static int db2k_ao_eoc(struct comedi_device *dev, struct comedi_subdevice *s,
 393                       struct comedi_insn *insn, unsigned long context)
 394{
 395        unsigned int chan = CR_CHAN(insn->chanspec);
 396        unsigned int status;
 397
 398        status = readw(dev->mmio + DB2K_REG_DAC_STATUS);
 399        if ((status & DB2K_DAC_STATUS_DAC_BUSY(chan)) == 0)
 400                return 0;
 401        return -EBUSY;
 402}
 403
 404static int db2k_ao_insn_write(struct comedi_device *dev,
 405                              struct comedi_subdevice *s,
 406                              struct comedi_insn *insn, unsigned int *data)
 407{
 408        unsigned int chan = CR_CHAN(insn->chanspec);
 409        int i;
 410
 411        for (i = 0; i < insn->n; i++) {
 412                unsigned int val = data[i];
 413                int ret;
 414
 415                writew(val, dev->mmio + DB2K_REG_DAC_SETTING(chan));
 416
 417                ret = comedi_timeout(dev, s, insn, db2k_ao_eoc, 0);
 418                if (ret)
 419                        return ret;
 420
 421                s->readback[chan] = val;
 422        }
 423
 424        return insn->n;
 425}
 426
 427static void db2k_reset_local_bus(struct comedi_device *dev)
 428{
 429        struct db2k_private *devpriv = dev->private;
 430        u32 cntrl;
 431
 432        cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
 433        cntrl |= PLX_CNTRL_RESET;
 434        writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
 435        mdelay(10);
 436        cntrl &= ~PLX_CNTRL_RESET;
 437        writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
 438        mdelay(10);
 439}
 440
 441static void db2k_reload_plx(struct comedi_device *dev)
 442{
 443        struct db2k_private *devpriv = dev->private;
 444        u32 cntrl;
 445
 446        cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
 447        cntrl &= ~PLX_CNTRL_EERELOAD;
 448        writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
 449        mdelay(10);
 450        cntrl |= PLX_CNTRL_EERELOAD;
 451        writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
 452        mdelay(10);
 453        cntrl &= ~PLX_CNTRL_EERELOAD;
 454        writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
 455        mdelay(10);
 456}
 457
 458static void db2k_pulse_prog_pin(struct comedi_device *dev)
 459{
 460        struct db2k_private *devpriv = dev->private;
 461        u32 cntrl;
 462
 463        cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
 464        cntrl |= PLX_CNTRL_USERO;
 465        writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
 466        mdelay(10);
 467        cntrl &= ~PLX_CNTRL_USERO;
 468        writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
 469        mdelay(10);     /* Not in the original code, but I like symmetry... */
 470}
 471
 472static int db2k_wait_cpld_init(struct comedi_device *dev)
 473{
 474        int result = -ETIMEDOUT;
 475        int i;
 476        u16 cpld;
 477
 478        /* timeout after 50 tries -> 5ms */
 479        for (i = 0; i < 50; i++) {
 480                cpld = readw(dev->mmio + DB2K_REG_CPLD_STATUS);
 481                if (cpld & DB2K_CPLD_STATUS_INIT) {
 482                        result = 0;
 483                        break;
 484                }
 485                usleep_range(100, 1000);
 486        }
 487        udelay(5);
 488        return result;
 489}
 490
 491static int db2k_wait_cpld_txready(struct comedi_device *dev)
 492{
 493        int i;
 494
 495        for (i = 0; i < 100; i++) {
 496                if (readw(dev->mmio + DB2K_REG_CPLD_STATUS) &
 497                    DB2K_CPLD_STATUS_TXREADY) {
 498                        return 0;
 499                }
 500                udelay(1);
 501        }
 502        return -ETIMEDOUT;
 503}
 504
 505static int db2k_write_cpld(struct comedi_device *dev, u16 data, bool new_cpld)
 506{
 507        int result = 0;
 508
 509        if (new_cpld) {
 510                result = db2k_wait_cpld_txready(dev);
 511                if (result)
 512                        return result;
 513        } else {
 514                usleep_range(10, 20);
 515        }
 516        writew(data, dev->mmio + DB2K_REG_CPLD_WDATA);
 517        if (!(readw(dev->mmio + DB2K_REG_CPLD_STATUS) & DB2K_CPLD_STATUS_INIT))
 518                result = -EIO;
 519
 520        return result;
 521}
 522
 523static int db2k_wait_fpga_programmed(struct comedi_device *dev)
 524{
 525        struct db2k_private *devpriv = dev->private;
 526        int i;
 527
 528        /* Time out after 200 tries -> 20ms */
 529        for (i = 0; i < 200; i++) {
 530                u32 cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
 531                /* General Purpose Input (USERI) set on FPGA "DONE". */
 532                if (cntrl & PLX_CNTRL_USERI)
 533                        return 0;
 534
 535                usleep_range(100, 1000);
 536        }
 537        return -ETIMEDOUT;
 538}
 539
 540static int db2k_load_firmware(struct comedi_device *dev, const u8 *cpld_array,
 541                              size_t len, unsigned long context)
 542{
 543        struct db2k_private *devpriv = dev->private;
 544        int result = -EIO;
 545        u32 cntrl;
 546        int retry;
 547        size_t i;
 548        bool new_cpld;
 549
 550        /* Look for FPGA start sequence in firmware. */
 551        for (i = 0; i + 1 < len; i++) {
 552                if (cpld_array[i] == 0xff && cpld_array[i + 1] == 0x20)
 553                        break;
 554        }
 555        if (i + 1 >= len) {
 556                dev_err(dev->class_dev, "bad firmware - no start sequence\n");
 557                return -EINVAL;
 558        }
 559        /* Check length is even. */
 560        if ((len - i) & 1) {
 561                dev_err(dev->class_dev,
 562                        "bad firmware - odd length (%zu = %zu - %zu)\n",
 563                        len - i, len, i);
 564                return -EINVAL;
 565        }
 566        /* Strip firmware header. */
 567        cpld_array += i;
 568        len -= i;
 569
 570        /* Check to make sure the serial eeprom is present on the board */
 571        cntrl = readl(devpriv->plx + PLX_REG_CNTRL);
 572        if (!(cntrl & PLX_CNTRL_EEPRESENT))
 573                return -EIO;
 574
 575        for (retry = 0; retry < 3; retry++) {
 576                db2k_reset_local_bus(dev);
 577                db2k_reload_plx(dev);
 578                db2k_pulse_prog_pin(dev);
 579                result = db2k_wait_cpld_init(dev);
 580                if (result)
 581                        continue;
 582
 583                new_cpld = (readw(dev->mmio + DB2K_REG_CPLD_STATUS) &
 584                            DB2K_CPLD_VERSION_MASK) == DB2K_CPLD_VERSION_NEW;
 585                for (; i < len; i += 2) {
 586                        u16 data = (cpld_array[i] << 8) + cpld_array[i + 1];
 587
 588                        result = db2k_write_cpld(dev, data, new_cpld);
 589                        if (result)
 590                                break;
 591                }
 592                if (result == 0)
 593                        result = db2k_wait_fpga_programmed(dev);
 594                if (result == 0) {
 595                        db2k_reset_local_bus(dev);
 596                        db2k_reload_plx(dev);
 597                        break;
 598                }
 599        }
 600        return result;
 601}
 602
 603static void db2k_adc_stop_dma_transfer(struct comedi_device *dev)
 604{
 605}
 606
 607static void db2k_adc_disarm(struct comedi_device *dev)
 608{
 609        /* Disable hardware triggers */
 610        udelay(2);
 611        writew(DB2K_TRIG_CONTROL_TYPE_ANALOG | DB2K_TRIG_CONTROL_DISABLE,
 612               dev->mmio + DB2K_REG_TRIG_CONTROL);
 613        udelay(2);
 614        writew(DB2K_TRIG_CONTROL_TYPE_TTL | DB2K_TRIG_CONTROL_DISABLE,
 615               dev->mmio + DB2K_REG_TRIG_CONTROL);
 616
 617        /* Stop the scan list FIFO from loading the configuration pipe */
 618        udelay(2);
 619        writew(DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST,
 620               dev->mmio + DB2K_REG_ACQ_CONTROL);
 621
 622        /* Stop the pacer clock */
 623        udelay(2);
 624        writew(DB2K_ACQ_CONTROL_ADC_PACER_DISABLE,
 625               dev->mmio + DB2K_REG_ACQ_CONTROL);
 626
 627        /* Stop the input dma (abort channel 1) */
 628        db2k_adc_stop_dma_transfer(dev);
 629}
 630
 631static void db2k_activate_reference_dacs(struct comedi_device *dev)
 632{
 633        unsigned int val;
 634        int timeout;
 635
 636        /*  Set the + reference dac value in the FPGA */
 637        writew(DB2K_REF_DACS_SET | DB2K_REF_DACS_SELECT_POS_REF,
 638               dev->mmio + DB2K_REG_REF_DACS);
 639        for (timeout = 0; timeout < 20; timeout++) {
 640                val = readw(dev->mmio + DB2K_REG_DAC_STATUS);
 641                if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0)
 642                        break;
 643                udelay(2);
 644        }
 645
 646        /*  Set the - reference dac value in the FPGA */
 647        writew(DB2K_REF_DACS_SET | DB2K_REF_DACS_SELECT_NEG_REF,
 648               dev->mmio + DB2K_REG_REF_DACS);
 649        for (timeout = 0; timeout < 20; timeout++) {
 650                val = readw(dev->mmio + DB2K_REG_DAC_STATUS);
 651                if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0)
 652                        break;
 653                udelay(2);
 654        }
 655}
 656
 657static void db2k_initialize_ctrs(struct comedi_device *dev)
 658{
 659}
 660
 661static void db2k_initialize_tmrs(struct comedi_device *dev)
 662{
 663}
 664
 665static void db2k_dac_disarm(struct comedi_device *dev)
 666{
 667}
 668
 669static void db2k_initialize_adc(struct comedi_device *dev)
 670{
 671        db2k_adc_disarm(dev);
 672        db2k_activate_reference_dacs(dev);
 673        db2k_initialize_ctrs(dev);
 674        db2k_initialize_tmrs(dev);
 675}
 676
 677static void db2k_initialize_dac(struct comedi_device *dev)
 678{
 679        db2k_dac_disarm(dev);
 680}
 681
 682static int db2k_8255_cb(struct comedi_device *dev, int dir, int port, int data,
 683                        unsigned long iobase)
 684{
 685        if (dir) {
 686                writew(data, dev->mmio + iobase + port * 2);
 687                return 0;
 688        }
 689        return readw(dev->mmio + iobase + port * 2);
 690}
 691
 692static int db2k_auto_attach(struct comedi_device *dev, unsigned long context)
 693{
 694        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 695        const struct db2k_boardtype *board;
 696        struct db2k_private *devpriv;
 697        struct comedi_subdevice *s;
 698        int result;
 699
 700        if (context >= ARRAY_SIZE(db2k_boardtypes))
 701                return -ENODEV;
 702        board = &db2k_boardtypes[context];
 703        if (!board->name)
 704                return -ENODEV;
 705        dev->board_ptr = board;
 706        dev->board_name = board->name;
 707
 708        devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 709        if (!devpriv)
 710                return -ENOMEM;
 711
 712        result = comedi_pci_enable(dev);
 713        if (result)
 714                return result;
 715
 716        devpriv->plx = pci_ioremap_bar(pcidev, 0);
 717        dev->mmio = pci_ioremap_bar(pcidev, 2);
 718        if (!devpriv->plx || !dev->mmio)
 719                return -ENOMEM;
 720
 721        result = comedi_alloc_subdevices(dev, 3);
 722        if (result)
 723                return result;
 724
 725        result = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
 726                                      DB2K_FIRMWARE, db2k_load_firmware, 0);
 727        if (result < 0)
 728                return result;
 729
 730        db2k_initialize_adc(dev);
 731        db2k_initialize_dac(dev);
 732
 733        s = &dev->subdevices[0];
 734        /* ai subdevice */
 735        s->type = COMEDI_SUBD_AI;
 736        s->subdev_flags = SDF_READABLE | SDF_GROUND;
 737        s->n_chan = 24;
 738        s->maxdata = 0xffff;
 739        s->insn_read = db2k_ai_insn_read;
 740        s->range_table = &db2k_ai_range;
 741
 742        s = &dev->subdevices[1];
 743        /* ao subdevice */
 744        s->type = COMEDI_SUBD_AO;
 745        s->subdev_flags = SDF_WRITABLE;
 746        s->n_chan = board->has_2_ao ? 2 : 4;
 747        s->maxdata = 0xffff;
 748        s->insn_write = db2k_ao_insn_write;
 749        s->range_table = &range_bipolar10;
 750
 751        result = comedi_alloc_subdev_readback(s);
 752        if (result)
 753                return result;
 754
 755        s = &dev->subdevices[2];
 756        return subdev_8255_init(dev, s, db2k_8255_cb,
 757                                DB2K_REG_DIO_P2_EXP_IO_8_BIT);
 758}
 759
 760static void db2k_detach(struct comedi_device *dev)
 761{
 762        struct db2k_private *devpriv = dev->private;
 763
 764        if (devpriv && devpriv->plx)
 765                iounmap(devpriv->plx);
 766        comedi_pci_detach(dev);
 767}
 768
 769static struct comedi_driver db2k_driver = {
 770        .driver_name    = "daqboard2000",
 771        .module         = THIS_MODULE,
 772        .auto_attach    = db2k_auto_attach,
 773        .detach         = db2k_detach,
 774};
 775
 776static int db2k_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 777{
 778        return comedi_pci_auto_config(dev, &db2k_driver, id->driver_data);
 779}
 780
 781static const struct pci_device_id db2k_pci_table[] = {
 782        { PCI_DEVICE_SUB(PCI_VENDOR_ID_IOTECH, 0x0409, PCI_VENDOR_ID_IOTECH,
 783                         0x0002), .driver_data = BOARD_DAQBOARD2000, },
 784        { PCI_DEVICE_SUB(PCI_VENDOR_ID_IOTECH, 0x0409, PCI_VENDOR_ID_IOTECH,
 785                         0x0004), .driver_data = BOARD_DAQBOARD2001, },
 786        { 0 }
 787};
 788MODULE_DEVICE_TABLE(pci, db2k_pci_table);
 789
 790static struct pci_driver db2k_pci_driver = {
 791        .name           = "daqboard2000",
 792        .id_table       = db2k_pci_table,
 793        .probe          = db2k_pci_probe,
 794        .remove         = comedi_pci_auto_unconfig,
 795};
 796module_comedi_pci_driver(db2k_driver, db2k_pci_driver);
 797
 798MODULE_AUTHOR("Comedi http://www.comedi.org");
 799MODULE_DESCRIPTION("Comedi low-level driver");
 800MODULE_LICENSE("GPL");
 801MODULE_FIRMWARE(DB2K_FIRMWARE);
 802