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16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/interrupt.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/serial.h>
22#include <linux/serial_reg.h>
23
24#include "dgnc_driver.h"
25#include "dgnc_neo.h"
26#include "dgnc_tty.h"
27
28static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
29static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
30static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
31static inline void neo_clear_break(struct channel_t *ch, int force);
32static inline void neo_set_cts_flow_control(struct channel_t *ch);
33static inline void neo_set_rts_flow_control(struct channel_t *ch);
34static inline void neo_set_ixon_flow_control(struct channel_t *ch);
35static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
36static inline void neo_set_no_output_flow_control(struct channel_t *ch);
37static inline void neo_set_no_input_flow_control(struct channel_t *ch);
38static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
39static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
40static void neo_tasklet(unsigned long data);
41static void neo_vpd(struct dgnc_board *brd);
42static void neo_uart_init(struct channel_t *ch);
43static void neo_uart_off(struct channel_t *ch);
44static int neo_drain(struct tty_struct *tty, uint seconds);
45static void neo_param(struct tty_struct *tty);
46static void neo_assert_modem_signals(struct channel_t *ch);
47static void neo_flush_uart_write(struct channel_t *ch);
48static void neo_flush_uart_read(struct channel_t *ch);
49static void neo_disable_receiver(struct channel_t *ch);
50static void neo_enable_receiver(struct channel_t *ch);
51static void neo_send_break(struct channel_t *ch, int msecs);
52static void neo_send_start_character(struct channel_t *ch);
53static void neo_send_stop_character(struct channel_t *ch);
54static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
55static uint neo_get_uart_bytes_left(struct channel_t *ch);
56static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
57static irqreturn_t neo_intr(int irq, void *voidbrd);
58
59struct board_ops dgnc_neo_ops = {
60 .tasklet = neo_tasklet,
61 .intr = neo_intr,
62 .uart_init = neo_uart_init,
63 .uart_off = neo_uart_off,
64 .drain = neo_drain,
65 .param = neo_param,
66 .vpd = neo_vpd,
67 .assert_modem_signals = neo_assert_modem_signals,
68 .flush_uart_write = neo_flush_uart_write,
69 .flush_uart_read = neo_flush_uart_read,
70 .disable_receiver = neo_disable_receiver,
71 .enable_receiver = neo_enable_receiver,
72 .send_break = neo_send_break,
73 .send_start_character = neo_send_start_character,
74 .send_stop_character = neo_send_stop_character,
75 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
76 .get_uart_bytes_left = neo_get_uart_bytes_left,
77 .send_immediate_char = neo_send_immediate_char
78};
79
80
81
82
83
84
85
86
87
88static inline void neo_pci_posting_flush(struct dgnc_board *bd)
89{
90 readb(bd->re_map_membase + 0x8D);
91}
92
93static inline void neo_set_cts_flow_control(struct channel_t *ch)
94{
95 unsigned char ier = readb(&ch->ch_neo_uart->ier);
96 unsigned char efr = readb(&ch->ch_neo_uart->efr);
97
98
99#if 1
100 ier |= UART_17158_IER_CTSDSR;
101#else
102 ier &= ~(UART_17158_IER_CTSDSR);
103#endif
104
105 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
106
107
108 efr &= ~UART_17158_EFR_IXON;
109
110
111
112
113
114 writeb(0, &ch->ch_neo_uart->efr);
115
116
117 writeb(efr, &ch->ch_neo_uart->efr);
118
119
120 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
121 &ch->ch_neo_uart->fctr);
122
123
124 writeb(8, &ch->ch_neo_uart->tfifo);
125 ch->ch_t_tlevel = 8;
126
127 writeb(ier, &ch->ch_neo_uart->ier);
128
129 neo_pci_posting_flush(ch->ch_bd);
130}
131
132static inline void neo_set_rts_flow_control(struct channel_t *ch)
133{
134 unsigned char ier = readb(&ch->ch_neo_uart->ier);
135 unsigned char efr = readb(&ch->ch_neo_uart->efr);
136
137
138#if 1
139 ier |= UART_17158_IER_RTSDTR;
140#else
141 ier &= ~(UART_17158_IER_RTSDTR);
142#endif
143 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
144
145
146 ier &= ~UART_17158_IER_XOFF;
147 efr &= ~UART_17158_EFR_IXOFF;
148
149
150
151
152
153 writeb(0, &ch->ch_neo_uart->efr);
154
155
156 writeb(efr, &ch->ch_neo_uart->efr);
157
158 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
159 &ch->ch_neo_uart->fctr);
160 ch->ch_r_watermark = 4;
161
162 writeb(32, &ch->ch_neo_uart->rfifo);
163 ch->ch_r_tlevel = 32;
164
165 writeb(ier, &ch->ch_neo_uart->ier);
166
167
168
169
170
171
172
173 ch->ch_mostat |= UART_MCR_RTS;
174
175 neo_pci_posting_flush(ch->ch_bd);
176}
177
178static inline void neo_set_ixon_flow_control(struct channel_t *ch)
179{
180 unsigned char ier = readb(&ch->ch_neo_uart->ier);
181 unsigned char efr = readb(&ch->ch_neo_uart->efr);
182
183
184 ier &= ~UART_17158_IER_CTSDSR;
185 efr &= ~UART_17158_EFR_CTSDSR;
186
187
188 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
189
190
191
192
193
194 writeb(0, &ch->ch_neo_uart->efr);
195
196
197 writeb(efr, &ch->ch_neo_uart->efr);
198
199 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
200 &ch->ch_neo_uart->fctr);
201 ch->ch_r_watermark = 4;
202
203 writeb(32, &ch->ch_neo_uart->rfifo);
204 ch->ch_r_tlevel = 32;
205
206
207 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
208 writeb(0, &ch->ch_neo_uart->xonchar2);
209
210 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
211 writeb(0, &ch->ch_neo_uart->xoffchar2);
212
213 writeb(ier, &ch->ch_neo_uart->ier);
214
215 neo_pci_posting_flush(ch->ch_bd);
216}
217
218static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
219{
220 unsigned char ier = readb(&ch->ch_neo_uart->ier);
221 unsigned char efr = readb(&ch->ch_neo_uart->efr);
222
223
224 ier &= ~UART_17158_IER_RTSDTR;
225 efr &= ~UART_17158_EFR_RTSDTR;
226
227
228 ier |= UART_17158_IER_XOFF;
229 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
230
231
232
233
234
235 writeb(0, &ch->ch_neo_uart->efr);
236
237
238 writeb(efr, &ch->ch_neo_uart->efr);
239
240
241 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
242 &ch->ch_neo_uart->fctr);
243
244 writeb(8, &ch->ch_neo_uart->tfifo);
245 ch->ch_t_tlevel = 8;
246
247
248 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
249 writeb(0, &ch->ch_neo_uart->xonchar2);
250
251 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
252 writeb(0, &ch->ch_neo_uart->xoffchar2);
253
254 writeb(ier, &ch->ch_neo_uart->ier);
255
256 neo_pci_posting_flush(ch->ch_bd);
257}
258
259static inline void neo_set_no_input_flow_control(struct channel_t *ch)
260{
261 unsigned char ier = readb(&ch->ch_neo_uart->ier);
262 unsigned char efr = readb(&ch->ch_neo_uart->efr);
263
264
265 ier &= ~UART_17158_IER_RTSDTR;
266 efr &= ~UART_17158_EFR_RTSDTR;
267
268
269 ier &= ~UART_17158_IER_XOFF;
270 if (ch->ch_c_iflag & IXON)
271 efr &= ~(UART_17158_EFR_IXOFF);
272 else
273 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
274
275
276
277
278
279 writeb(0, &ch->ch_neo_uart->efr);
280
281
282 writeb(efr, &ch->ch_neo_uart->efr);
283
284
285 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
286 &ch->ch_neo_uart->fctr);
287
288 ch->ch_r_watermark = 0;
289
290 writeb(16, &ch->ch_neo_uart->tfifo);
291 ch->ch_t_tlevel = 16;
292
293 writeb(16, &ch->ch_neo_uart->rfifo);
294 ch->ch_r_tlevel = 16;
295
296 writeb(ier, &ch->ch_neo_uart->ier);
297
298 neo_pci_posting_flush(ch->ch_bd);
299}
300
301static inline void neo_set_no_output_flow_control(struct channel_t *ch)
302{
303 unsigned char ier = readb(&ch->ch_neo_uart->ier);
304 unsigned char efr = readb(&ch->ch_neo_uart->efr);
305
306
307 ier &= ~UART_17158_IER_CTSDSR;
308 efr &= ~UART_17158_EFR_CTSDSR;
309
310
311 if (ch->ch_c_iflag & IXOFF)
312 efr &= ~UART_17158_EFR_IXON;
313 else
314 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
315
316
317
318
319
320 writeb(0, &ch->ch_neo_uart->efr);
321
322
323 writeb(efr, &ch->ch_neo_uart->efr);
324
325
326 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
327 &ch->ch_neo_uart->fctr);
328
329 ch->ch_r_watermark = 0;
330
331 writeb(16, &ch->ch_neo_uart->tfifo);
332 ch->ch_t_tlevel = 16;
333
334 writeb(16, &ch->ch_neo_uart->rfifo);
335 ch->ch_r_tlevel = 16;
336
337 writeb(ier, &ch->ch_neo_uart->ier);
338
339 neo_pci_posting_flush(ch->ch_bd);
340}
341
342
343static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
344{
345
346 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) ||
347 ch->ch_c_cflag & CRTSCTS)
348 return;
349
350
351 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
352 writeb(0, &ch->ch_neo_uart->xonchar2);
353
354 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
355 writeb(0, &ch->ch_neo_uart->xoffchar2);
356
357 neo_pci_posting_flush(ch->ch_bd);
358}
359
360
361
362static inline void neo_clear_break(struct channel_t *ch, int force)
363{
364 unsigned long flags;
365
366 spin_lock_irqsave(&ch->ch_lock, flags);
367
368
369 if (!ch->ch_stop_sending_break) {
370 spin_unlock_irqrestore(&ch->ch_lock, flags);
371 return;
372 }
373
374
375 if (ch->ch_flags & CH_BREAK_SENDING) {
376 if (force ||
377 time_after_eq(jiffies, ch->ch_stop_sending_break)) {
378 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
379
380 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
381 neo_pci_posting_flush(ch->ch_bd);
382 ch->ch_flags &= ~(CH_BREAK_SENDING);
383 ch->ch_stop_sending_break = 0;
384 }
385 }
386 spin_unlock_irqrestore(&ch->ch_lock, flags);
387}
388
389
390
391static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
392{
393 struct channel_t *ch;
394 unsigned char isr;
395 unsigned char cause;
396 unsigned long flags;
397
398 ch = brd->channels[port];
399 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
400 return;
401
402
403 while (1) {
404 isr = readb(&ch->ch_neo_uart->isr_fcr);
405
406
407 if (isr & UART_IIR_NO_INT)
408 break;
409
410
411
412
413
414 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
415
416 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
417
418 neo_copy_data_from_uart_to_queue(ch);
419
420
421
422
423 spin_lock_irqsave(&ch->ch_lock, flags);
424 dgnc_check_queue_flow_control(ch);
425 spin_unlock_irqrestore(&ch->ch_lock, flags);
426 }
427
428 if (isr & UART_IIR_THRI) {
429
430 spin_lock_irqsave(&ch->ch_lock, flags);
431 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
432 spin_unlock_irqrestore(&ch->ch_lock, flags);
433 neo_copy_data_from_queue_to_uart(ch);
434 }
435
436 if (isr & UART_17158_IIR_XONXOFF) {
437 cause = readb(&ch->ch_neo_uart->xoffchar1);
438
439
440
441
442
443
444 if (cause == UART_17158_XON_DETECT) {
445
446
447
448
449 if (brd->channels[port]->ch_flags & CH_STOP) {
450 spin_lock_irqsave(&ch->ch_lock,
451 flags);
452 ch->ch_flags &= ~(CH_STOP);
453 spin_unlock_irqrestore(&ch->ch_lock,
454 flags);
455 }
456 } else if (cause == UART_17158_XOFF_DETECT) {
457 if (!(brd->channels[port]->ch_flags &
458 CH_STOP)) {
459 spin_lock_irqsave(&ch->ch_lock,
460 flags);
461 ch->ch_flags |= CH_STOP;
462 spin_unlock_irqrestore(&ch->ch_lock,
463 flags);
464 }
465 }
466 }
467
468 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
469
470
471
472
473
474 cause = readb(&ch->ch_neo_uart->mcr);
475
476 if ((cause & 0x4) == 0) {
477 if (cause & UART_MCR_RTS) {
478 spin_lock_irqsave(&ch->ch_lock,
479 flags);
480 ch->ch_mostat |= UART_MCR_RTS;
481 spin_unlock_irqrestore(&ch->ch_lock,
482 flags);
483 } else {
484 spin_lock_irqsave(&ch->ch_lock,
485 flags);
486 ch->ch_mostat &= ~(UART_MCR_RTS);
487 spin_unlock_irqrestore(&ch->ch_lock,
488 flags);
489 }
490 } else {
491 if (cause & UART_MCR_DTR) {
492 spin_lock_irqsave(&ch->ch_lock,
493 flags);
494 ch->ch_mostat |= UART_MCR_DTR;
495 spin_unlock_irqrestore(&ch->ch_lock,
496 flags);
497 } else {
498 spin_lock_irqsave(&ch->ch_lock,
499 flags);
500 ch->ch_mostat &= ~(UART_MCR_DTR);
501 spin_unlock_irqrestore(&ch->ch_lock,
502 flags);
503 }
504 }
505 }
506
507
508 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
509 }
510}
511
512static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
513{
514 struct channel_t *ch;
515 int linestatus;
516 unsigned long flags;
517
518
519
520
521
522 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
523 return;
524
525 if (port >= brd->maxports)
526 return;
527
528 ch = brd->channels[port];
529 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
530 return;
531
532 linestatus = readb(&ch->ch_neo_uart->lsr);
533
534 ch->ch_cached_lsr |= linestatus;
535
536 if (ch->ch_cached_lsr & UART_LSR_DR) {
537
538 neo_copy_data_from_uart_to_queue(ch);
539 spin_lock_irqsave(&ch->ch_lock, flags);
540 dgnc_check_queue_flow_control(ch);
541 spin_unlock_irqrestore(&ch->ch_lock, flags);
542 }
543
544
545
546
547
548
549 if (linestatus & UART_LSR_PE)
550 ch->ch_err_parity++;
551
552 if (linestatus & UART_LSR_FE)
553 ch->ch_err_frame++;
554
555 if (linestatus & UART_LSR_BI)
556 ch->ch_err_break++;
557
558 if (linestatus & UART_LSR_OE) {
559
560
561
562
563
564
565
566 ch->ch_err_overrun++;
567 }
568
569 if (linestatus & UART_LSR_THRE) {
570 spin_lock_irqsave(&ch->ch_lock, flags);
571 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
572 spin_unlock_irqrestore(&ch->ch_lock, flags);
573
574
575 neo_copy_data_from_queue_to_uart(ch);
576 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
577 spin_lock_irqsave(&ch->ch_lock, flags);
578 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
579 spin_unlock_irqrestore(&ch->ch_lock, flags);
580
581
582 neo_copy_data_from_queue_to_uart(ch);
583 }
584}
585
586
587
588
589
590static void neo_param(struct tty_struct *tty)
591{
592 unsigned char lcr = 0;
593 unsigned char uart_lcr = 0;
594 unsigned char ier = 0;
595 unsigned char uart_ier = 0;
596 uint baud = 9600;
597 int quot = 0;
598 struct dgnc_board *bd;
599 struct channel_t *ch;
600 struct un_t *un;
601
602 if (!tty || tty->magic != TTY_MAGIC)
603 return;
604
605 un = (struct un_t *)tty->driver_data;
606 if (!un || un->magic != DGNC_UNIT_MAGIC)
607 return;
608
609 ch = un->un_ch;
610 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
611 return;
612
613 bd = ch->ch_bd;
614 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
615 return;
616
617
618
619 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
620 ch->ch_r_head = 0;
621 ch->ch_r_tail = 0;
622 ch->ch_e_head = 0;
623 ch->ch_e_tail = 0;
624 ch->ch_w_head = 0;
625 ch->ch_w_tail = 0;
626
627 neo_flush_uart_write(ch);
628 neo_flush_uart_read(ch);
629
630
631 ch->ch_flags |= (CH_BAUD0);
632 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
633 neo_assert_modem_signals(ch);
634 ch->ch_old_baud = 0;
635 return;
636
637 } else if (ch->ch_custom_speed) {
638 baud = ch->ch_custom_speed;
639
640 if (ch->ch_flags & CH_BAUD0) {
641 ch->ch_flags &= ~(CH_BAUD0);
642
643
644
645
646
647 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
648 ch->ch_mostat |= (UART_MCR_RTS);
649 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
650 ch->ch_mostat |= (UART_MCR_DTR);
651 }
652 } else {
653 int iindex = 0;
654 int jindex = 0;
655
656 ulong bauds[4][16] = {
657 {
658 0, 50, 75, 110,
659 134, 150, 200, 300,
660 600, 1200, 1800, 2400,
661 4800, 9600, 19200, 38400 },
662 {
663 0, 57600, 115200, 230400,
664 460800, 150, 200, 921600,
665 600, 1200, 1800, 2400,
666 4800, 9600, 19200, 38400 },
667 {
668 0, 57600, 76800, 115200,
669 131657, 153600, 230400, 460800,
670 921600, 1200, 1800, 2400,
671 4800, 9600, 19200, 38400 },
672 {
673 0, 57600, 115200, 230400,
674 460800, 150, 200, 921600,
675 600, 1200, 1800, 2400,
676 4800, 9600, 19200, 38400 }
677 };
678
679
680
681
682
683 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
684 (un->un_type == DGNC_PRINT))
685 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
686 else
687 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
688
689 if (ch->ch_c_cflag & CBAUDEX)
690 iindex = 1;
691
692 if (ch->ch_digi.digi_flags & DIGI_FAST)
693 iindex += 2;
694
695 jindex = baud;
696
697 if ((iindex >= 0) && (iindex < 4) &&
698 (jindex >= 0) && (jindex < 16))
699 baud = bauds[iindex][jindex];
700 else
701 baud = 0;
702
703 if (baud == 0)
704 baud = 9600;
705
706
707 if (ch->ch_flags & CH_BAUD0) {
708 ch->ch_flags &= ~(CH_BAUD0);
709
710
711
712
713
714 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
715 ch->ch_mostat |= (UART_MCR_RTS);
716 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
717 ch->ch_mostat |= (UART_MCR_DTR);
718 }
719 }
720
721 if (ch->ch_c_cflag & PARENB)
722 lcr |= UART_LCR_PARITY;
723
724 if (!(ch->ch_c_cflag & PARODD))
725 lcr |= UART_LCR_EPAR;
726
727
728
729
730
731#ifdef CMSPAR
732 if (ch->ch_c_cflag & CMSPAR)
733 lcr |= UART_LCR_SPAR;
734#endif
735
736 if (ch->ch_c_cflag & CSTOPB)
737 lcr |= UART_LCR_STOP;
738
739 switch (ch->ch_c_cflag & CSIZE) {
740 case CS5:
741 lcr |= UART_LCR_WLEN5;
742 break;
743 case CS6:
744 lcr |= UART_LCR_WLEN6;
745 break;
746 case CS7:
747 lcr |= UART_LCR_WLEN7;
748 break;
749 case CS8:
750 default:
751 lcr |= UART_LCR_WLEN8;
752 break;
753 }
754
755 uart_ier = readb(&ch->ch_neo_uart->ier);
756 ier = uart_ier;
757
758 uart_lcr = readb(&ch->ch_neo_uart->lcr);
759
760 if (baud == 0)
761 baud = 9600;
762
763 quot = ch->ch_bd->bd_dividend / baud;
764
765 if (quot != 0 && ch->ch_old_baud != baud) {
766 ch->ch_old_baud = baud;
767 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
768 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
769 writeb((quot >> 8), &ch->ch_neo_uart->ier);
770 writeb(lcr, &ch->ch_neo_uart->lcr);
771 }
772
773 if (uart_lcr != lcr)
774 writeb(lcr, &ch->ch_neo_uart->lcr);
775
776 if (ch->ch_c_cflag & CREAD)
777 ier |= (UART_IER_RDI | UART_IER_RLSI);
778 else
779 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
780
781
782
783
784
785 if ((ch->ch_digi.digi_flags & CTSPACE) ||
786 (ch->ch_digi.digi_flags & RTSPACE) ||
787 (ch->ch_c_cflag & CRTSCTS) ||
788 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
789 !(ch->ch_c_cflag & CLOCAL))
790 ier |= UART_IER_MSI;
791 else
792 ier &= ~UART_IER_MSI;
793
794 ier |= UART_IER_THRI;
795
796 if (ier != uart_ier)
797 writeb(ier, &ch->ch_neo_uart->ier);
798
799
800 neo_set_new_start_stop_chars(ch);
801
802 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
803 neo_set_cts_flow_control(ch);
804 } else if (ch->ch_c_iflag & IXON) {
805
806
807
808
809 if ((ch->ch_startc == _POSIX_VDISABLE) ||
810 (ch->ch_stopc == _POSIX_VDISABLE))
811 neo_set_no_output_flow_control(ch);
812 else
813 neo_set_ixon_flow_control(ch);
814 } else {
815 neo_set_no_output_flow_control(ch);
816 }
817
818 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
819 neo_set_rts_flow_control(ch);
820 } else if (ch->ch_c_iflag & IXOFF) {
821
822
823
824
825 if ((ch->ch_startc == _POSIX_VDISABLE) ||
826 (ch->ch_stopc == _POSIX_VDISABLE))
827 neo_set_no_input_flow_control(ch);
828 else
829 neo_set_ixoff_flow_control(ch);
830 } else {
831 neo_set_no_input_flow_control(ch);
832 }
833
834
835
836
837
838
839 if (baud < 9600) {
840 writeb(1, &ch->ch_neo_uart->rfifo);
841 ch->ch_r_tlevel = 1;
842 }
843
844 neo_assert_modem_signals(ch);
845
846
847 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
848}
849
850
851
852static void neo_tasklet(unsigned long data)
853{
854 struct dgnc_board *bd = (struct dgnc_board *)data;
855 struct channel_t *ch;
856 unsigned long flags;
857 int i;
858 int state = 0;
859 int ports = 0;
860
861 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
862 return;
863
864
865 spin_lock_irqsave(&bd->bd_lock, flags);
866 state = bd->state;
867 ports = bd->nasync;
868 spin_unlock_irqrestore(&bd->bd_lock, flags);
869
870
871
872
873
874 spin_lock_irqsave(&bd->bd_intr_lock, flags);
875
876
877
878 if ((state == BOARD_READY) && (ports > 0)) {
879
880 for (i = 0; i < ports; i++) {
881 ch = bd->channels[i];
882
883
884 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
885 continue;
886
887
888
889
890
891
892
893
894
895
896 dgnc_input(ch);
897
898
899
900
901
902
903 neo_copy_data_from_queue_to_uart(ch);
904 dgnc_wakeup_writes(ch);
905
906
907
908
909
910 dgnc_carrier(ch);
911
912
913
914
915
916 if (ch->ch_stop_sending_break)
917 neo_clear_break(ch, 0);
918 }
919 }
920
921
922 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
923}
924
925
926
927
928
929
930static irqreturn_t neo_intr(int irq, void *voidbrd)
931{
932 struct dgnc_board *brd = voidbrd;
933 struct channel_t *ch;
934 int port = 0;
935 int type;
936 u32 uart_poll;
937 unsigned long flags;
938 unsigned long flags2;
939
940
941
942
943
944 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
945 return IRQ_NONE;
946
947
948 spin_lock_irqsave(&brd->bd_intr_lock, flags);
949
950
951
952
953
954
955 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
956
957
958
959
960
961
962 if (!uart_poll) {
963 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
964 return IRQ_NONE;
965 }
966
967
968
969
970
971
972
973 while ((uart_poll & 0xff) != 0) {
974 type = uart_poll >> (8 + (port * 3));
975 type &= 0x7;
976
977 uart_poll &= ~(0x01 << port);
978
979
980 switch (type) {
981 case UART_17158_RXRDY_TIMEOUT:
982
983
984
985
986
987
988 if (port >= brd->nasync)
989 break;
990
991 ch = brd->channels[port];
992 neo_copy_data_from_uart_to_queue(ch);
993
994
995
996
997
998 spin_lock_irqsave(&ch->ch_lock, flags2);
999 dgnc_check_queue_flow_control(ch);
1000 spin_unlock_irqrestore(&ch->ch_lock, flags2);
1001
1002 break;
1003
1004 case UART_17158_RX_LINE_STATUS:
1005
1006
1007
1008 neo_parse_lsr(brd, port);
1009 break;
1010
1011 case UART_17158_TXRDY:
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026 neo_parse_isr(brd, port);
1027 break;
1028
1029 case UART_17158_MSR:
1030
1031
1032
1033 neo_parse_isr(brd, port);
1034 break;
1035
1036 default:
1037
1038
1039
1040
1041
1042
1043 break;
1044 }
1045
1046 port++;
1047 }
1048
1049
1050
1051 tasklet_schedule(&brd->helper_tasklet);
1052
1053 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
1054
1055 return IRQ_HANDLED;
1056}
1057
1058
1059
1060
1061
1062
1063static void neo_disable_receiver(struct channel_t *ch)
1064{
1065 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1066
1067 tmp &= ~(UART_IER_RDI);
1068 writeb(tmp, &ch->ch_neo_uart->ier);
1069 neo_pci_posting_flush(ch->ch_bd);
1070}
1071
1072
1073
1074
1075
1076
1077static void neo_enable_receiver(struct channel_t *ch)
1078{
1079 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1080
1081 tmp |= (UART_IER_RDI);
1082 writeb(tmp, &ch->ch_neo_uart->ier);
1083 neo_pci_posting_flush(ch->ch_bd);
1084}
1085
1086static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1087{
1088 int qleft = 0;
1089 unsigned char linestatus = 0;
1090 unsigned char error_mask = 0;
1091 int n = 0;
1092 int total = 0;
1093 ushort head;
1094 ushort tail;
1095 unsigned long flags;
1096
1097 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1098 return;
1099
1100 spin_lock_irqsave(&ch->ch_lock, flags);
1101
1102
1103 head = ch->ch_r_head & RQUEUEMASK;
1104 tail = ch->ch_r_tail & RQUEUEMASK;
1105
1106
1107 linestatus = ch->ch_cached_lsr;
1108 ch->ch_cached_lsr = 0;
1109
1110
1111 qleft = tail - head - 1;
1112 if (qleft < 0)
1113 qleft += RQUEUEMASK + 1;
1114
1115
1116
1117
1118
1119
1120
1121
1122 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1123 total = 0;
1124 } else {
1125 total = readb(&ch->ch_neo_uart->rfifo);
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1136 total -= 1;
1137 else
1138 total -= 3;
1139 }
1140
1141
1142
1143
1144
1145
1146
1147 total = min(total, qleft);
1148
1149 while (total > 0) {
1150
1151
1152
1153
1154 linestatus = readb(&ch->ch_neo_uart->lsr);
1155
1156
1157
1158
1159
1160
1161 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1162 break;
1163
1164
1165 n = min(((uint)total), (RQUEUESIZE - (uint)head));
1166
1167
1168
1169
1170
1171
1172
1173 n = min_t(uint, n, 12);
1174
1175
1176
1177
1178
1179
1180 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1181 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1182
1183 linestatus = 0;
1184
1185
1186 memcpy_fromio(ch->ch_rqueue + head,
1187 &ch->ch_neo_uart->txrxburst, n);
1188
1189
1190
1191
1192
1193
1194 memset(ch->ch_equeue + head, 0, n);
1195
1196
1197 head = (head + n) & RQUEUEMASK;
1198 total -= n;
1199 qleft -= n;
1200 ch->ch_rxcount += n;
1201 }
1202
1203
1204
1205
1206
1207 if (ch->ch_c_iflag & IGNBRK)
1208 error_mask |= UART_LSR_BI;
1209
1210
1211
1212
1213
1214 while (1) {
1215
1216
1217
1218
1219 linestatus |= readb(&ch->ch_neo_uart->lsr);
1220
1221
1222
1223
1224
1225
1226 if (!(linestatus & UART_LSR_DR)) {
1227 ch->ch_cached_lsr = linestatus;
1228 break;
1229 }
1230
1231
1232 linestatus &= ~UART_LSR_DR;
1233
1234
1235
1236
1237
1238
1239 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1240 linestatus &= ~(UART_LSR_THRE |
1241 UART_17158_TX_AND_FIFO_CLR);
1242 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1243 }
1244
1245
1246
1247 if (linestatus & error_mask) {
1248 unsigned char discard;
1249
1250 linestatus = 0;
1251 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1252 continue;
1253 }
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264 while (qleft < 1) {
1265 tail = (tail + 1) & RQUEUEMASK;
1266 ch->ch_r_tail = tail;
1267 ch->ch_err_overrun++;
1268 qleft++;
1269 }
1270
1271 memcpy_fromio(ch->ch_rqueue + head,
1272 &ch->ch_neo_uart->txrxburst, 1);
1273 ch->ch_equeue[head] = (unsigned char)linestatus;
1274
1275
1276 linestatus = 0;
1277
1278
1279 head = (head + 1) & RQUEUEMASK;
1280
1281 qleft--;
1282 ch->ch_rxcount++;
1283 }
1284
1285
1286
1287 ch->ch_r_head = head & RQUEUEMASK;
1288 ch->ch_e_head = head & EQUEUEMASK;
1289
1290 spin_unlock_irqrestore(&ch->ch_lock, flags);
1291}
1292
1293
1294
1295
1296
1297static int neo_drain(struct tty_struct *tty, uint seconds)
1298{
1299 unsigned long flags;
1300 struct channel_t *ch;
1301 struct un_t *un;
1302 int rc = 0;
1303
1304 if (!tty || tty->magic != TTY_MAGIC)
1305 return -ENXIO;
1306
1307 un = (struct un_t *)tty->driver_data;
1308 if (!un || un->magic != DGNC_UNIT_MAGIC)
1309 return -ENXIO;
1310
1311 ch = un->un_ch;
1312 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1313 return -ENXIO;
1314
1315 spin_lock_irqsave(&ch->ch_lock, flags);
1316 un->un_flags |= UN_EMPTY;
1317 spin_unlock_irqrestore(&ch->ch_lock, flags);
1318
1319
1320
1321
1322
1323 rc = wait_event_interruptible_timeout(un->un_flags_wait,
1324 ((un->un_flags & UN_EMPTY) == 0),
1325 msecs_to_jiffies(seconds * 1000));
1326
1327
1328 return rc;
1329}
1330
1331
1332
1333
1334
1335
1336static void neo_flush_uart_write(struct channel_t *ch)
1337{
1338 unsigned char tmp = 0;
1339 int i = 0;
1340
1341 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1342 return;
1343
1344 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1345 &ch->ch_neo_uart->isr_fcr);
1346 neo_pci_posting_flush(ch->ch_bd);
1347
1348 for (i = 0; i < 10; i++) {
1349
1350
1351
1352
1353 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1354 if (tmp & 4)
1355 udelay(10);
1356 else
1357 break;
1358 }
1359
1360 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1361}
1362
1363
1364
1365
1366
1367
1368static void neo_flush_uart_read(struct channel_t *ch)
1369{
1370 unsigned char tmp = 0;
1371 int i = 0;
1372
1373 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1374 return;
1375
1376 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1377 &ch->ch_neo_uart->isr_fcr);
1378 neo_pci_posting_flush(ch->ch_bd);
1379
1380 for (i = 0; i < 10; i++) {
1381
1382
1383
1384
1385 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1386 if (tmp & 2)
1387 udelay(10);
1388 else
1389 break;
1390 }
1391}
1392
1393static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1394{
1395 ushort head;
1396 ushort tail;
1397 int n;
1398 int s;
1399 int qlen;
1400 uint len_written = 0;
1401 unsigned long flags;
1402
1403 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1404 return;
1405
1406 spin_lock_irqsave(&ch->ch_lock, flags);
1407
1408
1409 if (ch->ch_w_tail == ch->ch_w_head)
1410 goto exit_unlock;
1411
1412
1413 if ((ch->ch_flags & CH_FORCED_STOP) ||
1414 (ch->ch_flags & CH_BREAK_SENDING))
1415 goto exit_unlock;
1416
1417
1418
1419 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1420 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
1421
1422
1423 ch->ch_cached_lsr |= lsrbits;
1424 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1425 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1426
1427
1428
1429
1430
1431
1432 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1433 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1434 ch->ch_mostat |= (UART_MCR_RTS);
1435 neo_assert_modem_signals(ch);
1436 }
1437 ch->ch_tun.un_flags |= (UN_EMPTY);
1438 }
1439
1440
1441
1442
1443
1444 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1445 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1446 ch->ch_mostat |= (UART_MCR_DTR);
1447 neo_assert_modem_signals(ch);
1448 }
1449 ch->ch_tun.un_flags |= (UN_EMPTY);
1450 }
1451
1452 writeb(ch->ch_wqueue[ch->ch_w_tail],
1453 &ch->ch_neo_uart->txrx);
1454 ch->ch_w_tail++;
1455 ch->ch_w_tail &= WQUEUEMASK;
1456 ch->ch_txcount++;
1457 }
1458
1459 goto exit_unlock;
1460 }
1461
1462
1463
1464 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1465 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1466 goto exit_unlock;
1467
1468 len_written = 0;
1469
1470 n = readb(&ch->ch_neo_uart->tfifo);
1471
1472 if ((unsigned int)n > ch->ch_t_tlevel)
1473 goto exit_unlock;
1474
1475 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1476 } else {
1477 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1478 }
1479
1480
1481 head = ch->ch_w_head & WQUEUEMASK;
1482 tail = ch->ch_w_tail & WQUEUEMASK;
1483 qlen = (head - tail) & WQUEUEMASK;
1484
1485
1486 n = min(n, qlen);
1487
1488 while (n > 0) {
1489 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1490 s = min(s, n);
1491
1492 if (s <= 0)
1493 break;
1494
1495
1496
1497
1498
1499
1500 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1501 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1502 ch->ch_mostat |= (UART_MCR_RTS);
1503 neo_assert_modem_signals(ch);
1504 }
1505 ch->ch_tun.un_flags |= (UN_EMPTY);
1506 }
1507
1508
1509
1510
1511
1512
1513 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1514 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1515 ch->ch_mostat |= (UART_MCR_DTR);
1516 neo_assert_modem_signals(ch);
1517 }
1518 ch->ch_tun.un_flags |= (UN_EMPTY);
1519 }
1520
1521 memcpy_toio(&ch->ch_neo_uart->txrxburst,
1522 ch->ch_wqueue + tail, s);
1523
1524
1525 tail = (tail + s) & WQUEUEMASK;
1526 n -= s;
1527 ch->ch_txcount += s;
1528 len_written += s;
1529 }
1530
1531
1532 ch->ch_w_tail = tail & WQUEUEMASK;
1533
1534 if (len_written > 0) {
1535 neo_pci_posting_flush(ch->ch_bd);
1536 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1537 }
1538
1539exit_unlock:
1540 spin_unlock_irqrestore(&ch->ch_lock, flags);
1541}
1542
1543static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
1544{
1545 unsigned char msignals = signals;
1546
1547 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1548 return;
1549
1550
1551
1552
1553
1554 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1555 unsigned char mswap = msignals;
1556
1557 if (mswap & UART_MSR_DDCD) {
1558 msignals &= ~UART_MSR_DDCD;
1559 msignals |= UART_MSR_DDSR;
1560 }
1561 if (mswap & UART_MSR_DDSR) {
1562 msignals &= ~UART_MSR_DDSR;
1563 msignals |= UART_MSR_DDCD;
1564 }
1565 if (mswap & UART_MSR_DCD) {
1566 msignals &= ~UART_MSR_DCD;
1567 msignals |= UART_MSR_DSR;
1568 }
1569 if (mswap & UART_MSR_DSR) {
1570 msignals &= ~UART_MSR_DSR;
1571 msignals |= UART_MSR_DCD;
1572 }
1573 }
1574
1575
1576
1577
1578
1579 msignals &= 0xf0;
1580
1581 if (msignals & UART_MSR_DCD)
1582 ch->ch_mistat |= UART_MSR_DCD;
1583 else
1584 ch->ch_mistat &= ~UART_MSR_DCD;
1585
1586 if (msignals & UART_MSR_DSR)
1587 ch->ch_mistat |= UART_MSR_DSR;
1588 else
1589 ch->ch_mistat &= ~UART_MSR_DSR;
1590
1591 if (msignals & UART_MSR_RI)
1592 ch->ch_mistat |= UART_MSR_RI;
1593 else
1594 ch->ch_mistat &= ~UART_MSR_RI;
1595
1596 if (msignals & UART_MSR_CTS)
1597 ch->ch_mistat |= UART_MSR_CTS;
1598 else
1599 ch->ch_mistat &= ~UART_MSR_CTS;
1600}
1601
1602
1603static void neo_assert_modem_signals(struct channel_t *ch)
1604{
1605 unsigned char out;
1606
1607 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1608 return;
1609
1610 out = ch->ch_mostat;
1611
1612 if (ch->ch_flags & CH_LOOPBACK)
1613 out |= UART_MCR_LOOP;
1614
1615 writeb(out, &ch->ch_neo_uart->mcr);
1616 neo_pci_posting_flush(ch->ch_bd);
1617
1618
1619 udelay(10);
1620}
1621
1622static void neo_send_start_character(struct channel_t *ch)
1623{
1624 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1625 return;
1626
1627 if (ch->ch_startc != _POSIX_VDISABLE) {
1628 ch->ch_xon_sends++;
1629 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1630 neo_pci_posting_flush(ch->ch_bd);
1631 udelay(10);
1632 }
1633}
1634
1635static void neo_send_stop_character(struct channel_t *ch)
1636{
1637 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1638 return;
1639
1640 if (ch->ch_stopc != _POSIX_VDISABLE) {
1641 ch->ch_xoff_sends++;
1642 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1643 neo_pci_posting_flush(ch->ch_bd);
1644 udelay(10);
1645 }
1646}
1647
1648
1649
1650static void neo_uart_init(struct channel_t *ch)
1651{
1652 writeb(0, &ch->ch_neo_uart->ier);
1653 writeb(0, &ch->ch_neo_uart->efr);
1654 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1655
1656
1657 readb(&ch->ch_neo_uart->txrx);
1658 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1659 &ch->ch_neo_uart->isr_fcr);
1660 readb(&ch->ch_neo_uart->lsr);
1661 readb(&ch->ch_neo_uart->msr);
1662
1663 ch->ch_flags |= CH_FIFO_ENABLED;
1664
1665
1666 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1667 neo_pci_posting_flush(ch->ch_bd);
1668}
1669
1670
1671
1672static void neo_uart_off(struct channel_t *ch)
1673{
1674
1675 writeb(0, &ch->ch_neo_uart->efr);
1676
1677
1678 writeb(0, &ch->ch_neo_uart->ier);
1679 neo_pci_posting_flush(ch->ch_bd);
1680}
1681
1682static uint neo_get_uart_bytes_left(struct channel_t *ch)
1683{
1684 unsigned char left = 0;
1685 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
1686
1687
1688 ch->ch_cached_lsr |= lsr;
1689
1690
1691 if (!(lsr & UART_LSR_TEMT)) {
1692 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1693 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1694 left = 1;
1695 } else {
1696 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1697 left = 0;
1698 }
1699
1700 return left;
1701}
1702
1703
1704static void neo_send_break(struct channel_t *ch, int msecs)
1705{
1706
1707
1708 if (msecs == 0) {
1709 if (ch->ch_flags & CH_BREAK_SENDING) {
1710 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1711
1712 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1713 neo_pci_posting_flush(ch->ch_bd);
1714 ch->ch_flags &= ~(CH_BREAK_SENDING);
1715 ch->ch_stop_sending_break = 0;
1716 }
1717 return;
1718 }
1719
1720
1721
1722
1723
1724
1725 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1726
1727
1728 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1729 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1730
1731 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1732 neo_pci_posting_flush(ch->ch_bd);
1733 ch->ch_flags |= (CH_BREAK_SENDING);
1734 }
1735}
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1746{
1747 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1748 return;
1749
1750 writeb(c, &ch->ch_neo_uart->txrx);
1751 neo_pci_posting_flush(ch->ch_bd);
1752}
1753
1754static unsigned int neo_read_eeprom(unsigned char __iomem *base,
1755 unsigned int address)
1756{
1757 unsigned int enable;
1758 unsigned int bits;
1759 unsigned int databit;
1760 unsigned int val;
1761
1762
1763 writeb(NEO_EECS, base + NEO_EEREG);
1764
1765 enable = address | 0x180;
1766
1767 for (bits = 9; bits--; ) {
1768 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1769
1770 writeb(databit | NEO_EECS, base + NEO_EEREG);
1771 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1772 }
1773
1774 val = 0;
1775
1776 for (bits = 17; bits--; ) {
1777
1778 writeb(NEO_EECS, base + NEO_EEREG);
1779 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1780 val <<= 1;
1781
1782 if (readb(base + NEO_EEREG) & NEO_EEDO)
1783 val |= 1;
1784 }
1785
1786
1787 writeb(NEO_EECS, base + NEO_EEREG);
1788
1789
1790 writeb(0x00, base + NEO_EEREG);
1791
1792 return val;
1793}
1794
1795static void neo_vpd(struct dgnc_board *brd)
1796{
1797 unsigned int i = 0;
1798 unsigned int a;
1799
1800 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1801 return;
1802
1803 if (!brd->re_map_membase)
1804 return;
1805
1806
1807 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1808 a = neo_read_eeprom(brd->re_map_membase, i);
1809 brd->vpd[i * 2] = a & 0xff;
1810 brd->vpd[(i * 2) + 1] = (a >> 8) & 0xff;
1811 }
1812
1813
1814
1815
1816
1817
1818
1819 if (((brd->vpd[0x08] != 0x82) &&
1820 (brd->vpd[0x10] != 0x82)) ||
1821 (brd->vpd[0x7F] != 0x78)) {
1822 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1823 } else {
1824
1825 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1826 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1827 strncpy(brd->serial_num, &brd->vpd[i + 3], 9);
1828 }
1829}
1830