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15#define _HCI_HAL_INIT_C_
16
17#include <osdep_service.h>
18#include <drv_types.h>
19#include <rtw_efuse.h>
20#include <fw.h>
21#include <rtl8188e_hal.h>
22#include <rtl8188e_led.h>
23#include <rtw_iol.h>
24#include <phy.h>
25
26#define HAL_BB_ENABLE 1
27
28static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
29{
30 struct hal_data_8188e *haldata = adapt->HalData;
31
32 switch (NumOutPipe) {
33 case 3:
34 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
35 haldata->OutEpNumber = 3;
36 break;
37 case 2:
38 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
39 haldata->OutEpNumber = 2;
40 break;
41 case 1:
42 haldata->OutEpQueueSel = TX_SELE_HQ;
43 haldata->OutEpNumber = 1;
44 break;
45 default:
46 break;
47 }
48 DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
49}
50
51static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
52{
53 bool result = false;
54
55 _ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
56
57
58 if (adapt->HalData->OutEpNumber == 1) {
59 if (NumInPipe != 1)
60 return result;
61 }
62
63
64
65 result = Hal_MappingOutPipe(adapt, NumOutPipe);
66
67 return result;
68}
69
70void rtw_hal_chip_configure(struct adapter *adapt)
71{
72 struct hal_data_8188e *haldata = adapt->HalData;
73 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt);
74
75 if (pdvobjpriv->ishighspeed)
76 haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;
77 else
78 haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;
79
80 haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
81
82 haldata->UsbTxAggMode = 1;
83 haldata->UsbTxAggDescNum = 0x6;
84
85 haldata->UsbRxAggMode = USB_RX_AGG_DMA;
86 haldata->UsbRxAggBlockCount = 8;
87 haldata->UsbRxAggBlockTimeout = 0x6;
88 haldata->UsbRxAggPageCount = 48;
89 haldata->UsbRxAggPageTimeout = 0x4;
90
91 HalUsbSetQueuePipeMapping8188EUsb(adapt,
92 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
93}
94
95u32 rtw_hal_power_on(struct adapter *adapt)
96{
97 u16 value16;
98
99 if (adapt->HalData->bMacPwrCtrlOn)
100 return _SUCCESS;
101
102 if (!rtl88eu_pwrseqcmdparsing(adapt, PWR_CUT_ALL_MSK,
103 Rtl8188E_NIC_PWR_ON_FLOW)) {
104 DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
105 return _FAIL;
106 }
107
108
109
110 usb_write16(adapt, REG_CR, 0x00);
111
112
113 value16 = usb_read16(adapt, REG_CR);
114 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
115 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
116
117
118 usb_write16(adapt, REG_CR, value16);
119 adapt->HalData->bMacPwrCtrlOn = true;
120
121 return _SUCCESS;
122}
123
124
125static void _InitInterrupt(struct adapter *Adapter)
126{
127 u32 imr, imr_ex;
128 u8 usb_opt;
129
130
131 usb_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
132
133 imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
134 usb_write32(Adapter, REG_HIMR_88E, imr);
135 Adapter->HalData->IntrMask[0] = imr;
136
137 imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
138 usb_write32(Adapter, REG_HIMRE_88E, imr_ex);
139 Adapter->HalData->IntrMask[1] = imr_ex;
140
141
142
143
144 usb_opt = usb_read8(Adapter, REG_USB_SPECIAL_OPTION);
145
146 if (!adapter_to_dvobj(Adapter)->ishighspeed)
147 usb_opt = usb_opt & (~INT_BULK_SEL);
148 else
149 usb_opt = usb_opt | (INT_BULK_SEL);
150
151 usb_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
152}
153
154static void _InitQueueReservedPage(struct adapter *Adapter)
155{
156 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
157 u32 numHQ = 0;
158 u32 numLQ = 0;
159 u32 numNQ = 0;
160 u32 numPubQ;
161 u32 value32;
162 u8 value8;
163 bool bWiFiConfig = pregistrypriv->wifi_spec;
164
165 if (bWiFiConfig) {
166 if (Adapter->HalData->OutEpQueueSel & TX_SELE_HQ)
167 numHQ = 0x29;
168
169 if (Adapter->HalData->OutEpQueueSel & TX_SELE_LQ)
170 numLQ = 0x1C;
171
172
173 if (Adapter->HalData->OutEpQueueSel & TX_SELE_NQ)
174 numNQ = 0x1C;
175 value8 = (u8)_NPQ(numNQ);
176 usb_write8(Adapter, REG_RQPN_NPQ, value8);
177
178 numPubQ = 0xA8 - numHQ - numLQ - numNQ;
179
180
181 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
182 usb_write32(Adapter, REG_RQPN, value32);
183 } else {
184 usb_write16(Adapter, REG_RQPN_NPQ, 0x0000);
185 usb_write16(Adapter, REG_RQPN_NPQ, 0x0d);
186 usb_write32(Adapter, REG_RQPN, 0x808E000d);
187 }
188}
189
190static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
191{
192 usb_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
193 usb_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
194 usb_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
195 usb_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
196 usb_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
197}
198
199static void _InitPageBoundary(struct adapter *Adapter)
200{
201
202
203 u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
204
205 usb_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
206}
207
208static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
209 u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
210 u16 hiQ)
211{
212 u16 value16 = (usb_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
213
214 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
215 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
216 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
217
218 usb_write16(Adapter, REG_TRXDMA_CTRL, value16);
219}
220
221static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
222{
223 u16 value = 0;
224
225 switch (Adapter->HalData->OutEpQueueSel) {
226 case TX_SELE_HQ:
227 value = QUEUE_HIGH;
228 break;
229 case TX_SELE_LQ:
230 value = QUEUE_LOW;
231 break;
232 case TX_SELE_NQ:
233 value = QUEUE_NORMAL;
234 break;
235 default:
236 break;
237 }
238 _InitNormalChipRegPriority(Adapter, value, value, value, value,
239 value, value);
240}
241
242static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
243{
244 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
245 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
246 u16 valueHi = 0;
247 u16 valueLow = 0;
248
249 switch (Adapter->HalData->OutEpQueueSel) {
250 case (TX_SELE_HQ | TX_SELE_LQ):
251 valueHi = QUEUE_HIGH;
252 valueLow = QUEUE_LOW;
253 break;
254 case (TX_SELE_NQ | TX_SELE_LQ):
255 valueHi = QUEUE_NORMAL;
256 valueLow = QUEUE_LOW;
257 break;
258 case (TX_SELE_HQ | TX_SELE_NQ):
259 valueHi = QUEUE_HIGH;
260 valueLow = QUEUE_NORMAL;
261 break;
262 default:
263 break;
264 }
265
266 if (!pregistrypriv->wifi_spec) {
267 beQ = valueLow;
268 bkQ = valueLow;
269 viQ = valueHi;
270 voQ = valueHi;
271 mgtQ = valueHi;
272 hiQ = valueHi;
273 } else {
274 beQ = valueLow;
275 bkQ = valueHi;
276 viQ = valueHi;
277 voQ = valueLow;
278 mgtQ = valueHi;
279 hiQ = valueHi;
280 }
281 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
282}
283
284static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
285{
286 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
287 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
288
289 if (!pregistrypriv->wifi_spec) {
290 beQ = QUEUE_LOW;
291 bkQ = QUEUE_LOW;
292 viQ = QUEUE_NORMAL;
293 voQ = QUEUE_HIGH;
294 mgtQ = QUEUE_HIGH;
295 hiQ = QUEUE_HIGH;
296 } else {
297 beQ = QUEUE_LOW;
298 bkQ = QUEUE_NORMAL;
299 viQ = QUEUE_NORMAL;
300 voQ = QUEUE_HIGH;
301 mgtQ = QUEUE_HIGH;
302 hiQ = QUEUE_HIGH;
303 }
304 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
305}
306
307static void _InitQueuePriority(struct adapter *Adapter)
308{
309 switch (Adapter->HalData->OutEpNumber) {
310 case 1:
311 _InitNormalChipOneOutEpPriority(Adapter);
312 break;
313 case 2:
314 _InitNormalChipTwoOutEpPriority(Adapter);
315 break;
316 case 3:
317 _InitNormalChipThreeOutEpPriority(Adapter);
318 break;
319 default:
320 break;
321 }
322}
323
324static void _InitNetworkType(struct adapter *Adapter)
325{
326 u32 value32;
327
328 value32 = usb_read32(Adapter, REG_CR);
329
330 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
331
332 usb_write32(Adapter, REG_CR, value32);
333}
334
335static void _InitTransferPageSize(struct adapter *Adapter)
336{
337
338
339 u8 value8;
340 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
341 usb_write8(Adapter, REG_PBP, value8);
342}
343
344static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
345{
346 usb_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
347}
348
349static void _InitWMACSetting(struct adapter *Adapter)
350{
351 struct hal_data_8188e *haldata = Adapter->HalData;
352
353 haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
354 RCR_CBSSID_DATA | RCR_CBSSID_BCN |
355 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
356 RCR_APP_MIC | RCR_APP_PHYSTS;
357
358
359 usb_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
360
361
362 usb_write32(Adapter, REG_MAR, 0xFFFFFFFF);
363 usb_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
364}
365
366static void _InitAdaptiveCtrl(struct adapter *Adapter)
367{
368 u16 value16;
369 u32 value32;
370
371
372 value32 = usb_read32(Adapter, REG_RRSR);
373 value32 &= ~RATE_BITMAP_ALL;
374 value32 |= RATE_RRSR_CCK_ONLY_1M;
375 usb_write32(Adapter, REG_RRSR, value32);
376
377
378
379
380 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
381 usb_write16(Adapter, REG_SPEC_SIFS, value16);
382
383
384 value16 = _LRL(0x30) | _SRL(0x30);
385 usb_write16(Adapter, REG_RL, value16);
386}
387
388static void _InitEDCA(struct adapter *Adapter)
389{
390
391 usb_write16(Adapter, REG_SPEC_SIFS, 0x100a);
392 usb_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
393
394
395 usb_write16(Adapter, REG_SIFS_CTX, 0x100a);
396
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398 usb_write16(Adapter, REG_SIFS_TRX, 0x100a);
399
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401 usb_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
402 usb_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
403 usb_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
404 usb_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
405}
406
407static void _InitRDGSetting(struct adapter *Adapter)
408{
409 usb_write8(Adapter, REG_RD_CTRL, 0xFF);
410 usb_write16(Adapter, REG_RD_NAV_NXT, 0x200);
411 usb_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
412}
413
414static void _InitRxSetting(struct adapter *Adapter)
415{
416 usb_write32(Adapter, REG_MACID, 0x87654321);
417 usb_write32(Adapter, 0x0700, 0x87654321);
418}
419
420static void _InitRetryFunction(struct adapter *Adapter)
421{
422 u8 value8;
423
424 value8 = usb_read8(Adapter, REG_FWHW_TXQ_CTRL);
425 value8 |= EN_AMPDU_RTY_NEW;
426 usb_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
427
428
429 usb_write8(Adapter, REG_ACKTO, 0x40);
430}
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448static void usb_AggSettingTxUpdate(struct adapter *Adapter)
449{
450 struct hal_data_8188e *haldata = Adapter->HalData;
451 u32 value32;
452
453 if (Adapter->registrypriv.wifi_spec)
454 haldata->UsbTxAggMode = false;
455
456 if (haldata->UsbTxAggMode) {
457 value32 = usb_read32(Adapter, REG_TDECTRL);
458 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
459 value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
460
461 usb_write32(Adapter, REG_TDECTRL, value32);
462 }
463}
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480
481static void
482usb_AggSettingRxUpdate(
483 struct adapter *Adapter
484 )
485{
486 struct hal_data_8188e *haldata = Adapter->HalData;
487 u8 valueDMA;
488 u8 valueUSB;
489
490 valueDMA = usb_read8(Adapter, REG_TRXDMA_CTRL);
491 valueUSB = usb_read8(Adapter, REG_USB_SPECIAL_OPTION);
492
493 switch (haldata->UsbRxAggMode) {
494 case USB_RX_AGG_DMA:
495 valueDMA |= RXDMA_AGG_EN;
496 valueUSB &= ~USB_AGG_EN;
497 break;
498 case USB_RX_AGG_USB:
499 valueDMA &= ~RXDMA_AGG_EN;
500 valueUSB |= USB_AGG_EN;
501 break;
502 case USB_RX_AGG_MIX:
503 valueDMA |= RXDMA_AGG_EN;
504 valueUSB |= USB_AGG_EN;
505 break;
506 case USB_RX_AGG_DISABLE:
507 default:
508 valueDMA &= ~RXDMA_AGG_EN;
509 valueUSB &= ~USB_AGG_EN;
510 break;
511 }
512
513 usb_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
514 usb_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
515
516 switch (haldata->UsbRxAggMode) {
517 case USB_RX_AGG_DMA:
518 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
519 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, haldata->UsbRxAggPageTimeout);
520 break;
521 case USB_RX_AGG_USB:
522 usb_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
523 usb_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
524 break;
525 case USB_RX_AGG_MIX:
526 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
527 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (haldata->UsbRxAggPageTimeout & 0x1F));
528 usb_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
529 usb_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
530 break;
531 case USB_RX_AGG_DISABLE:
532 default:
533
534 break;
535 }
536
537 switch (PBP_128) {
538 case PBP_128:
539 haldata->HwRxPageSize = 128;
540 break;
541 case PBP_64:
542 haldata->HwRxPageSize = 64;
543 break;
544 case PBP_256:
545 haldata->HwRxPageSize = 256;
546 break;
547 case PBP_512:
548 haldata->HwRxPageSize = 512;
549 break;
550 case PBP_1024:
551 haldata->HwRxPageSize = 1024;
552 break;
553 default:
554 break;
555 }
556}
557
558static void InitUsbAggregationSetting(struct adapter *Adapter)
559{
560
561 usb_AggSettingTxUpdate(Adapter);
562
563
564 usb_AggSettingRxUpdate(Adapter);
565}
566
567static void _InitBeaconParameters(struct adapter *Adapter)
568{
569 struct hal_data_8188e *haldata = Adapter->HalData;
570
571 usb_write16(Adapter, REG_BCN_CTRL, 0x1010);
572
573
574 usb_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);
575 usb_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
576 usb_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
577
578
579
580 usb_write16(Adapter, REG_BCNTCFG, 0x660F);
581
582 haldata->RegBcnCtrlVal = usb_read8(Adapter, REG_BCN_CTRL);
583 haldata->RegTxPause = usb_read8(Adapter, REG_TXPAUSE);
584 haldata->RegFwHwTxQCtrl = usb_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
585 haldata->RegReg542 = usb_read8(Adapter, REG_TBTT_PROHIBIT+2);
586 haldata->RegCR_1 = usb_read8(Adapter, REG_CR+1);
587}
588
589static void _BeaconFunctionEnable(struct adapter *Adapter,
590 bool Enable, bool Linked)
591{
592 usb_write8(Adapter, REG_BCN_CTRL, (BIT(4) | BIT(3) | BIT(1)));
593
594 usb_write8(Adapter, REG_RD_CTRL+1, 0x6F);
595}
596
597
598static void _BBTurnOnBlock(struct adapter *Adapter)
599{
600 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
601 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
602}
603
604static void _InitAntenna_Selection(struct adapter *Adapter)
605{
606 struct hal_data_8188e *haldata = Adapter->HalData;
607
608 if (haldata->AntDivCfg == 0)
609 return;
610 DBG_88E("==> %s ....\n", __func__);
611
612 usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0) | BIT(23));
613 phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01);
614
615 if (phy_query_bb_reg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
616 haldata->CurAntenna = Antenna_A;
617 else
618 haldata->CurAntenna = Antenna_B;
619 DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
620}
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637
638enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
639{
640 u8 val8;
641 enum rt_rf_power_state rfpowerstate = rf_off;
642
643 if (adapt->pwrctrlpriv.bHWPowerdown) {
644 val8 = usb_read8(adapt, REG_HSISR);
645 DBG_88E("pwrdown, 0x5c(BIT(7))=%02x\n", val8);
646 rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on;
647 } else {
648 usb_write8(adapt, REG_MAC_PINMUX_CFG, usb_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT(3)));
649 val8 = usb_read8(adapt, REG_GPIO_IO_SEL);
650 DBG_88E("GPIO_IN=%02x\n", val8);
651 rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off;
652 }
653 return rfpowerstate;
654}
655
656u32 rtl8188eu_hal_init(struct adapter *Adapter)
657{
658 u8 value8 = 0;
659 u16 value16;
660 u8 txpktbuf_bndy;
661 u32 status = _SUCCESS;
662 struct hal_data_8188e *haldata = Adapter->HalData;
663 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
664 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
665 unsigned long init_start_time = jiffies;
666
667 #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
668
669 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
670
671 if (Adapter->pwrctrlpriv.bkeepfwalive) {
672 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
673 rtl88eu_phy_iq_calibrate(Adapter, true);
674 } else {
675 rtl88eu_phy_iq_calibrate(Adapter, false);
676 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
677 }
678
679 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
680 rtl88eu_phy_lc_calibrate(Adapter);
681
682 goto exit;
683 }
684
685 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
686 status = rtw_hal_power_on(Adapter);
687 if (status == _FAIL) {
688 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
689 goto exit;
690 }
691
692
693 haldata->CurrentChannel = 6;
694
695 if (pwrctrlpriv->reg_rfoff)
696 pwrctrlpriv->rf_pwrstate = rf_off;
697
698
699
700
701
702 if (!pregistrypriv->wifi_spec) {
703 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
704 } else {
705
706 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
707 }
708
709 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
710 _InitQueueReservedPage(Adapter);
711 _InitQueuePriority(Adapter);
712 _InitPageBoundary(Adapter);
713 _InitTransferPageSize(Adapter);
714
715 _InitTxBufferBoundary(Adapter, 0);
716
717 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
718 if (Adapter->registrypriv.mp_mode == 1) {
719 _InitRxSetting(Adapter);
720 Adapter->bFWReady = false;
721 } else {
722 status = rtl88eu_download_fw(Adapter);
723
724 if (status) {
725 DBG_88E("%s: Download Firmware failed!!\n", __func__);
726 Adapter->bFWReady = false;
727 return status;
728 }
729 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializeadapt8192CSdio(): Download Firmware Success!!\n"));
730 Adapter->bFWReady = true;
731 }
732 rtl8188e_InitializeFirmwareVars(Adapter);
733
734 rtl88eu_phy_mac_config(Adapter);
735
736 rtl88eu_phy_bb_config(Adapter);
737
738 rtl88eu_phy_rf_config(Adapter);
739
740 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
741 status = rtl8188e_iol_efuse_patch(Adapter);
742 if (status == _FAIL) {
743 DBG_88E("%s rtl8188e_iol_efuse_patch failed\n", __func__);
744 goto exit;
745 }
746
747 _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
748
749 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
750 status = InitLLTTable(Adapter, txpktbuf_bndy);
751 if (status == _FAIL) {
752 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
753 goto exit;
754 }
755
756 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
757
758 _InitDriverInfoSize(Adapter, DRVINFO_SZ);
759
760 _InitInterrupt(Adapter);
761 hal_init_macaddr(Adapter);
762 _InitNetworkType(Adapter);
763 _InitWMACSetting(Adapter);
764 _InitAdaptiveCtrl(Adapter);
765 _InitEDCA(Adapter);
766 _InitRetryFunction(Adapter);
767 InitUsbAggregationSetting(Adapter);
768 _InitBeaconParameters(Adapter);
769
770
771
772 value16 = usb_read16(Adapter, REG_CR);
773 value16 |= (MACTXEN | MACRXEN);
774 usb_write8(Adapter, REG_CR, value16);
775
776 if (haldata->bRDGEnable)
777 _InitRDGSetting(Adapter);
778
779
780
781 value8 = usb_read8(Adapter, REG_TX_RPT_CTRL);
782 usb_write8(Adapter, REG_TX_RPT_CTRL, (value8 | BIT(1) | BIT(0)));
783
784 usb_write8(Adapter, REG_TX_RPT_CTRL+1, 2);
785
786 usb_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
787
788 usb_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
789
790 usb_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);
791 usb_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);
792
793
794 haldata->RfRegChnlVal[0] = rtw_hal_read_rfreg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
795 haldata->RfRegChnlVal[1] = rtw_hal_read_rfreg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
796
797HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
798 _BBTurnOnBlock(Adapter);
799
800HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
801 invalidate_cam_all(Adapter);
802
803HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
804
805 phy_set_tx_power_level(Adapter, haldata->CurrentChannel);
806
807
808
809
810 _InitAntenna_Selection(Adapter);
811
812
813
814
815
816 usb_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
817
818
819
820 usb_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
821
822 if (pregistrypriv->wifi_spec)
823 usb_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
824
825
826 usb_write8(Adapter, 0x652, 0x0);
827
828HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
829 rtl8188e_InitHalDm(Adapter);
830
831
832
833
834
835
836
837
838 pwrctrlpriv->rf_pwrstate = rf_on;
839
840
841 usb_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
842
843
844 usb_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);
845
846
847 usb_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
848
849
850 usb_write16(Adapter, REG_TXDMA_OFFSET_CHK, (usb_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
851
852HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
853
854 if (pwrctrlpriv->rf_pwrstate == rf_on) {
855 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
856 rtl88eu_phy_iq_calibrate(Adapter, true);
857 } else {
858 rtl88eu_phy_iq_calibrate(Adapter, false);
859 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
860 }
861
862HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
863
864 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
865
866HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
867 rtl88eu_phy_lc_calibrate(Adapter);
868 }
869
870
871
872 usb_write8(Adapter, REG_USB_HRPWM, 0);
873
874
875 usb_write32(Adapter, REG_FWHW_TXQ_CTRL, usb_read32(Adapter, REG_FWHW_TXQ_CTRL) | BIT(12));
876
877exit:
878HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
879
880 DBG_88E("%s in %dms\n", __func__,
881 jiffies_to_msecs(jiffies - init_start_time));
882
883 return status;
884}
885
886static void CardDisableRTL8188EU(struct adapter *Adapter)
887{
888 u8 val8;
889
890 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
891
892
893 val8 = usb_read8(Adapter, REG_TX_RPT_CTRL);
894 usb_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT(1)));
895
896
897 usb_write8(Adapter, REG_CR, 0x0);
898
899
900 rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK,
901 Rtl8188E_NIC_LPS_ENTER_FLOW);
902
903
904
905 val8 = usb_read8(Adapter, REG_MCUFWDL);
906 if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) {
907
908 val8 = usb_read8(Adapter, REG_SYS_FUNC_EN+1);
909 val8 &= ~BIT(2);
910 usb_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
911 }
912
913
914 usb_write8(Adapter, REG_MCUFWDL, 0);
915
916
917
918 val8 = usb_read8(Adapter, REG_32K_CTRL);
919 usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT(0)));
920
921
922 rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK,
923 Rtl8188E_NIC_DISABLE_FLOW);
924
925
926 val8 = usb_read8(Adapter, REG_RSV_CTRL+1);
927 usb_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT(3))));
928 val8 = usb_read8(Adapter, REG_RSV_CTRL+1);
929 usb_write8(Adapter, REG_RSV_CTRL+1, val8 | BIT(3));
930
931
932 val8 = usb_read8(Adapter, GPIO_IN);
933 usb_write8(Adapter, GPIO_OUT, val8);
934 usb_write8(Adapter, GPIO_IO_SEL, 0xFF);
935
936 val8 = usb_read8(Adapter, REG_GPIO_IO_SEL);
937 usb_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
938 val8 = usb_read8(Adapter, REG_GPIO_IO_SEL+1);
939 usb_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);
940 usb_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);
941 Adapter->HalData->bMacPwrCtrlOn = false;
942 Adapter->bFWReady = false;
943}
944
945static void rtl8192cu_hw_power_down(struct adapter *adapt)
946{
947
948
949
950
951 usb_write8(adapt, REG_RSV_CTRL, 0x0);
952 usb_write16(adapt, REG_APS_FSMCO, 0x8812);
953}
954
955u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
956{
957 DBG_88E("==> %s\n", __func__);
958
959 usb_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
960 usb_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
961
962 DBG_88E("bkeepfwalive(%x)\n", Adapter->pwrctrlpriv.bkeepfwalive);
963 if (Adapter->pwrctrlpriv.bkeepfwalive) {
964 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
965 rtl8192cu_hw_power_down(Adapter);
966 } else {
967 if (Adapter->hw_init_completed) {
968 CardDisableRTL8188EU(Adapter);
969
970 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
971 rtl8192cu_hw_power_down(Adapter);
972 }
973 }
974 return _SUCCESS;
975}
976
977u32 rtw_hal_inirp_init(struct adapter *Adapter)
978{
979 u8 i;
980 struct recv_buf *precvbuf;
981 uint status;
982 struct recv_priv *precvpriv = &Adapter->recvpriv;
983
984 status = _SUCCESS;
985
986 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
987 ("===> usb_inirp_init\n"));
988
989
990 precvbuf = precvpriv->precv_buf;
991 for (i = 0; i < NR_RECVBUFF; i++) {
992 if (usb_read_port(Adapter, RECV_BULK_IN_ADDR, precvbuf) == false) {
993 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n"));
994 status = _FAIL;
995 goto exit;
996 }
997
998 precvbuf++;
999 }
1000
1001exit:
1002
1003 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n"));
1004
1005
1006 return status;
1007}
1008
1009
1010
1011
1012
1013
1014static void Hal_EfuseParsePIDVID_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1015{
1016 struct hal_data_8188e *haldata = adapt->HalData;
1017
1018 if (!AutoLoadFail) {
1019
1020 haldata->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
1021 haldata->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]);
1022
1023
1024 haldata->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
1025 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1026 } else {
1027 haldata->EEPROMVID = EEPROM_Default_VID;
1028 haldata->EEPROMPID = EEPROM_Default_PID;
1029
1030
1031 haldata->EEPROMCustomerID = EEPROM_Default_CustomerID;
1032 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1033 }
1034
1035 DBG_88E("VID = 0x%04X, PID = 0x%04X\n", haldata->EEPROMVID, haldata->EEPROMPID);
1036 DBG_88E("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", haldata->EEPROMCustomerID, haldata->EEPROMSubCustomerID);
1037}
1038
1039static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1040{
1041 u16 i;
1042 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
1043 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1044
1045 if (AutoLoadFail) {
1046 for (i = 0; i < 6; i++)
1047 eeprom->mac_addr[i] = sMacAddr[i];
1048 } else {
1049
1050 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
1051 }
1052 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1053 ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %pM\n",
1054 eeprom->mac_addr));
1055}
1056
1057static void
1058readAdapterInfo_8188EU(
1059 struct adapter *adapt
1060 )
1061{
1062 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1063
1064
1065 Hal_EfuseParseIDCode88E(adapt, eeprom->efuse_eeprom_data);
1066 Hal_EfuseParsePIDVID_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1067 Hal_EfuseParseMACAddr_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1068
1069 Hal_ReadPowerSavingMode88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1070 Hal_ReadTxPowerInfo88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1071 Hal_EfuseParseEEPROMVer88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1072 rtl8188e_EfuseParseChnlPlan(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1073 Hal_EfuseParseXtal_8188E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1074 Hal_EfuseParseCustomerID88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1075 Hal_ReadAntennaDiversity88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1076 Hal_EfuseParseBoardType88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1077 Hal_ReadThermalMeter_88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1078}
1079
1080static void _ReadPROMContent(
1081 struct adapter *Adapter
1082 )
1083{
1084 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(Adapter);
1085 u8 eeValue;
1086
1087
1088 eeValue = usb_read8(Adapter, REG_9346CR);
1089 eeprom->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1090 eeprom->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1091
1092 DBG_88E("Boot from %s, Autoload %s !\n", (eeprom->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1093 (eeprom->bautoload_fail_flag ? "Fail" : "OK"));
1094
1095 Hal_InitPGData88E(Adapter);
1096 readAdapterInfo_8188EU(Adapter);
1097}
1098
1099void rtw_hal_read_chip_info(struct adapter *Adapter)
1100{
1101 unsigned long start = jiffies;
1102
1103 MSG_88E("====> %s\n", __func__);
1104
1105 _ReadPROMContent(Adapter);
1106
1107 MSG_88E("<==== %s in %d ms\n", __func__,
1108 jiffies_to_msecs(jiffies - start));
1109}
1110
1111#define GPIO_DEBUG_PORT_NUM 0
1112static void rtl8192cu_trigger_gpio_0(struct adapter *adapt)
1113{
1114}
1115
1116static void ResumeTxBeacon(struct adapter *adapt)
1117{
1118 struct hal_data_8188e *haldata = adapt->HalData;
1119
1120
1121
1122
1123 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT(6));
1124 haldata->RegFwHwTxQCtrl |= BIT(6);
1125 usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff);
1126 haldata->RegReg542 |= BIT(0);
1127 usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1128}
1129
1130static void StopTxBeacon(struct adapter *adapt)
1131{
1132 struct hal_data_8188e *haldata = adapt->HalData;
1133
1134
1135
1136
1137 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT(6)));
1138 haldata->RegFwHwTxQCtrl &= (~BIT(6));
1139 usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64);
1140 haldata->RegReg542 &= ~(BIT(0));
1141 usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1142
1143
1144}
1145
1146static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
1147{
1148 u8 val8;
1149 u8 mode = *((u8 *)val);
1150
1151
1152 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
1153
1154
1155 val8 = usb_read8(Adapter, MSR)&0x0c;
1156 val8 |= mode;
1157 usb_write8(Adapter, MSR, val8);
1158
1159 DBG_88E("%s()-%d mode = %d\n", __func__, __LINE__, mode);
1160
1161 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
1162 StopTxBeacon(Adapter);
1163
1164 usb_write8(Adapter, REG_BCN_CTRL, 0x19);
1165 } else if (mode == _HW_STATE_ADHOC_) {
1166 ResumeTxBeacon(Adapter);
1167 usb_write8(Adapter, REG_BCN_CTRL, 0x1a);
1168 } else if (mode == _HW_STATE_AP_) {
1169 ResumeTxBeacon(Adapter);
1170
1171 usb_write8(Adapter, REG_BCN_CTRL, 0x12);
1172
1173
1174 usb_write32(Adapter, REG_RCR, 0x7000208e);
1175
1176 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1177
1178 usb_write16(Adapter, REG_RXFLTMAP1, 0x0400);
1179
1180
1181 usb_write8(Adapter, REG_BCNDMATIM, 0x02);
1182
1183 usb_write8(Adapter, REG_ATIMWND, 0x0a);
1184 usb_write16(Adapter, REG_BCNTCFG, 0x00);
1185 usb_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
1186 usb_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
1187
1188
1189 usb_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
1190
1191
1192 usb_write8(Adapter, REG_MBID_NUM, usb_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4));
1193
1194
1195
1196 usb_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | BIT(1)));
1197
1198
1199 usb_write8(Adapter, REG_BCN_CTRL_1, usb_read8(Adapter, REG_BCN_CTRL_1) | BIT(0));
1200 }
1201}
1202
1203static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val)
1204{
1205 u8 idx = 0;
1206 u32 reg_macid;
1207
1208 reg_macid = REG_MACID;
1209
1210 for (idx = 0; idx < 6; idx++)
1211 usb_write8(Adapter, (reg_macid+idx), val[idx]);
1212}
1213
1214static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val)
1215{
1216 u8 idx = 0;
1217 u32 reg_bssid;
1218
1219 reg_bssid = REG_BSSID;
1220
1221 for (idx = 0; idx < 6; idx++)
1222 usb_write8(Adapter, (reg_bssid+idx), val[idx]);
1223}
1224
1225static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val)
1226{
1227 u32 bcn_ctrl_reg;
1228
1229 bcn_ctrl_reg = REG_BCN_CTRL;
1230
1231 if (*((u8 *)val))
1232 usb_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
1233 else
1234 usb_write8(Adapter, bcn_ctrl_reg, usb_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
1235}
1236
1237void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
1238{
1239 struct hal_data_8188e *haldata = Adapter->HalData;
1240 struct dm_priv *pdmpriv = &haldata->dmpriv;
1241 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1242
1243 switch (variable) {
1244 case HW_VAR_MEDIA_STATUS:
1245 {
1246 u8 val8;
1247
1248 val8 = usb_read8(Adapter, MSR)&0x0c;
1249 val8 |= *((u8 *)val);
1250 usb_write8(Adapter, MSR, val8);
1251 }
1252 break;
1253 case HW_VAR_MEDIA_STATUS1:
1254 {
1255 u8 val8;
1256
1257 val8 = usb_read8(Adapter, MSR) & 0x03;
1258 val8 |= *((u8 *)val) << 2;
1259 usb_write8(Adapter, MSR, val8);
1260 }
1261 break;
1262 case HW_VAR_SET_OPMODE:
1263 hw_var_set_opmode(Adapter, variable, val);
1264 break;
1265 case HW_VAR_MAC_ADDR:
1266 hw_var_set_macaddr(Adapter, variable, val);
1267 break;
1268 case HW_VAR_BSSID:
1269 hw_var_set_bssid(Adapter, variable, val);
1270 break;
1271 case HW_VAR_BASIC_RATE:
1272 {
1273 u16 BrateCfg = 0;
1274 u8 RateIndex = 0;
1275
1276
1277
1278
1279
1280 HalSetBrateCfg(Adapter, val, &BrateCfg);
1281 DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
1282
1283
1284
1285
1286
1287
1288 BrateCfg = (BrateCfg | 0xd) & 0x15d;
1289 haldata->BasicRateSet = BrateCfg;
1290
1291 BrateCfg |= 0x01;
1292
1293 usb_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
1294 usb_write8(Adapter, REG_RRSR+1, (BrateCfg >> 8) & 0xff);
1295 usb_write8(Adapter, REG_RRSR+2, usb_read8(Adapter, REG_RRSR+2)&0xf0);
1296
1297
1298 while (BrateCfg > 0x1) {
1299 BrateCfg >>= 1;
1300 RateIndex++;
1301 }
1302
1303 usb_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
1304 }
1305 break;
1306 case HW_VAR_TXPAUSE:
1307 usb_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
1308 break;
1309 case HW_VAR_BCN_FUNC:
1310 hw_var_set_bcn_func(Adapter, variable, val);
1311 break;
1312 case HW_VAR_CORRECT_TSF:
1313 {
1314 u64 tsf;
1315 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1316 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1317
1318 tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) - 1024;
1319
1320 if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1321 StopTxBeacon(Adapter);
1322
1323
1324 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
1325
1326 usb_write32(Adapter, REG_TSFTR, tsf);
1327 usb_write32(Adapter, REG_TSFTR+4, tsf>>32);
1328
1329
1330 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(3));
1331
1332 if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1333 ResumeTxBeacon(Adapter);
1334 }
1335 break;
1336 case HW_VAR_CHECK_BSSID:
1337 if (*((u8 *)val)) {
1338 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1339 } else {
1340 u32 val32;
1341
1342 val32 = usb_read32(Adapter, REG_RCR);
1343
1344 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1345
1346 usb_write32(Adapter, REG_RCR, val32);
1347 }
1348 break;
1349 case HW_VAR_MLME_DISCONNECT:
1350
1351
1352 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
1353
1354
1355 usb_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1356
1357
1358 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
1359 break;
1360 case HW_VAR_MLME_SITESURVEY:
1361 if (*((u8 *)val)) {
1362
1363 u32 v = usb_read32(Adapter, REG_RCR);
1364 v &= ~(RCR_CBSSID_BCN);
1365 usb_write32(Adapter, REG_RCR, v);
1366
1367 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
1368
1369
1370 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
1371 } else {
1372 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1373 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1374
1375 if ((is_client_associated_to_ap(Adapter)) ||
1376 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) {
1377
1378 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1379
1380
1381 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1382 } else if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1383 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1384
1385 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1386 }
1387
1388 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1389 }
1390 break;
1391 case HW_VAR_MLME_JOIN:
1392 {
1393 u8 RetryLimit = 0x30;
1394 u8 type = *((u8 *)val);
1395 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1396
1397 if (type == 0) {
1398
1399 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1400
1401 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1402
1403 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
1404 RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
1405 else
1406 RetryLimit = 0x7;
1407 } else if (type == 1) {
1408
1409 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
1410 } else if (type == 2) {
1411
1412
1413 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1414
1415 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
1416 RetryLimit = 0x7;
1417 }
1418 usb_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
1419 }
1420 break;
1421 case HW_VAR_BEACON_INTERVAL:
1422 usb_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
1423 break;
1424 case HW_VAR_SLOT_TIME:
1425 {
1426 u8 u1bAIFS, aSifsTime;
1427 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1428 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1429
1430 usb_write8(Adapter, REG_SLOT, val[0]);
1431
1432 if (pmlmeinfo->WMM_enable == 0) {
1433 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
1434 aSifsTime = 10;
1435 else
1436 aSifsTime = 16;
1437
1438 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
1439
1440
1441 usb_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
1442 usb_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
1443 usb_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
1444 usb_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
1445 }
1446 }
1447 break;
1448 case HW_VAR_RESP_SIFS:
1449
1450 usb_write8(Adapter, REG_R2T_SIFS, val[0]);
1451 usb_write8(Adapter, REG_R2T_SIFS+1, val[1]);
1452
1453 usb_write8(Adapter, REG_T2T_SIFS, val[2]);
1454 usb_write8(Adapter, REG_T2T_SIFS+1, val[3]);
1455 break;
1456 case HW_VAR_ACK_PREAMBLE:
1457 {
1458 u8 regTmp;
1459 u8 bShortPreamble = *((bool *)val);
1460
1461 regTmp = (haldata->nCur40MhzPrimeSC)<<5;
1462 if (bShortPreamble)
1463 regTmp |= 0x80;
1464
1465 usb_write8(Adapter, REG_RRSR+2, regTmp);
1466 }
1467 break;
1468 case HW_VAR_SEC_CFG:
1469 usb_write8(Adapter, REG_SECCFG, *((u8 *)val));
1470 break;
1471 case HW_VAR_DM_FUNC_OP:
1472 if (val[0])
1473 podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
1474 else
1475 podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
1476 break;
1477 case HW_VAR_DM_FUNC_SET:
1478 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1479 pdmpriv->DMFlag = pdmpriv->InitDMFlag;
1480 podmpriv->SupportAbility = pdmpriv->InitODMFlag;
1481 } else {
1482 podmpriv->SupportAbility |= *((u32 *)val);
1483 }
1484 break;
1485 case HW_VAR_DM_FUNC_CLR:
1486 podmpriv->SupportAbility &= *((u32 *)val);
1487 break;
1488 case HW_VAR_CAM_EMPTY_ENTRY:
1489 {
1490 u8 ucIndex = *((u8 *)val);
1491 u8 i;
1492 u32 ulCommand = 0;
1493 u32 ulContent = 0;
1494 u32 ulEncAlgo = CAM_AES;
1495
1496 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
1497
1498 if (i == 0)
1499 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
1500 else
1501 ulContent = 0;
1502
1503 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
1504 ulCommand = ulCommand | CAM_POLLINIG|CAM_WRITE;
1505
1506 usb_write32(Adapter, WCAMI, ulContent);
1507 usb_write32(Adapter, RWCAM, ulCommand);
1508 }
1509 }
1510 break;
1511 case HW_VAR_CAM_INVALID_ALL:
1512 usb_write32(Adapter, RWCAM, BIT(31) | BIT(30));
1513 break;
1514 case HW_VAR_CAM_WRITE:
1515 {
1516 u32 cmd;
1517 u32 *cam_val = (u32 *)val;
1518 usb_write32(Adapter, WCAMI, cam_val[0]);
1519
1520 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
1521 usb_write32(Adapter, RWCAM, cmd);
1522 }
1523 break;
1524 case HW_VAR_AC_PARAM_VO:
1525 usb_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
1526 break;
1527 case HW_VAR_AC_PARAM_VI:
1528 usb_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
1529 break;
1530 case HW_VAR_AC_PARAM_BE:
1531 haldata->AcParam_BE = ((u32 *)(val))[0];
1532 usb_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
1533 break;
1534 case HW_VAR_AC_PARAM_BK:
1535 usb_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
1536 break;
1537 case HW_VAR_ACM_CTRL:
1538 {
1539 u8 acm_ctrl = *((u8 *)val);
1540 u8 AcmCtrl = usb_read8(Adapter, REG_ACMHWCTRL);
1541
1542 if (acm_ctrl > 1)
1543 AcmCtrl = AcmCtrl | 0x1;
1544
1545 if (acm_ctrl & BIT(3))
1546 AcmCtrl |= AcmHw_VoqEn;
1547 else
1548 AcmCtrl &= (~AcmHw_VoqEn);
1549
1550 if (acm_ctrl & BIT(2))
1551 AcmCtrl |= AcmHw_ViqEn;
1552 else
1553 AcmCtrl &= (~AcmHw_ViqEn);
1554
1555 if (acm_ctrl & BIT(1))
1556 AcmCtrl |= AcmHw_BeqEn;
1557 else
1558 AcmCtrl &= (~AcmHw_BeqEn);
1559
1560 DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1561 usb_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
1562 }
1563 break;
1564 case HW_VAR_AMPDU_MIN_SPACE:
1565 {
1566 u8 MinSpacingToSet;
1567 u8 SecMinSpace;
1568
1569 MinSpacingToSet = *((u8 *)val);
1570 if (MinSpacingToSet <= 7) {
1571 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
1572 case _NO_PRIVACY_:
1573 case _AES_:
1574 SecMinSpace = 0;
1575 break;
1576 case _WEP40_:
1577 case _WEP104_:
1578 case _TKIP_:
1579 case _TKIP_WTMIC_:
1580 SecMinSpace = 6;
1581 break;
1582 default:
1583 SecMinSpace = 7;
1584 break;
1585 }
1586 if (MinSpacingToSet < SecMinSpace)
1587 MinSpacingToSet = SecMinSpace;
1588 usb_write8(Adapter, REG_AMPDU_MIN_SPACE, (usb_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
1589 }
1590 }
1591 break;
1592 case HW_VAR_AMPDU_FACTOR:
1593 {
1594 u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1595 u8 FactorToSet;
1596 u8 *pRegToSet;
1597 u8 index = 0;
1598
1599 pRegToSet = RegToSet_Normal;
1600 FactorToSet = *((u8 *)val);
1601 if (FactorToSet <= 3) {
1602 FactorToSet = 1 << (FactorToSet + 2);
1603 if (FactorToSet > 0xf)
1604 FactorToSet = 0xf;
1605
1606 for (index = 0; index < 4; index++) {
1607 if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
1608 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
1609
1610 if ((pRegToSet[index] & 0x0f) > FactorToSet)
1611 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
1612
1613 usb_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
1614 }
1615 }
1616 }
1617 break;
1618 case HW_VAR_RXDMA_AGG_PG_TH:
1619 {
1620 u8 threshold = *((u8 *)val);
1621 if (threshold == 0)
1622 threshold = haldata->UsbRxAggPageCount;
1623 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
1624 }
1625 break;
1626 case HW_VAR_SET_RPWM:
1627 break;
1628 case HW_VAR_H2C_FW_PWRMODE:
1629 {
1630 u8 psmode = (*(u8 *)val);
1631
1632
1633
1634 if (psmode != PS_MODE_ACTIVE)
1635 ODM_RF_Saving(podmpriv, true);
1636 rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
1637 }
1638 break;
1639 case HW_VAR_H2C_FW_JOINBSSRPT:
1640 {
1641 u8 mstatus = (*(u8 *)val);
1642 rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
1643 }
1644 break;
1645 case HW_VAR_INITIAL_GAIN:
1646 {
1647 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1648 u32 rx_gain = ((u32 *)(val))[0];
1649
1650 if (rx_gain == 0xff) {
1651 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
1652 } else {
1653 pDigTable->BackupIGValue = pDigTable->CurIGValue;
1654 ODM_Write_DIG(podmpriv, rx_gain);
1655 }
1656 }
1657 break;
1658 case HW_VAR_TRIGGER_GPIO_0:
1659 rtl8192cu_trigger_gpio_0(Adapter);
1660 break;
1661 case HW_VAR_RPT_TIMER_SETTING:
1662 {
1663 u16 min_rpt_time = (*(u16 *)val);
1664 ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
1665 }
1666 break;
1667 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
1668 {
1669 u8 Optimum_antenna = (*(u8 *)val);
1670 u8 Ant;
1671
1672 if (haldata->CurAntenna != Optimum_antenna) {
1673 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
1674 rtl88eu_dm_update_rx_idle_ant(&haldata->odmpriv, Ant);
1675
1676 haldata->CurAntenna = Optimum_antenna;
1677 }
1678 }
1679 break;
1680 case HW_VAR_EFUSE_BYTES:
1681 haldata->EfuseUsedBytes = *((u16 *)val);
1682 break;
1683 case HW_VAR_FIFO_CLEARN_UP:
1684 {
1685 struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
1686 u8 trycnt = 100;
1687
1688
1689 usb_write8(Adapter, REG_TXPAUSE, 0xff);
1690
1691
1692 Adapter->xmitpriv.nqos_ssn = usb_read16(Adapter, REG_NQOS_SEQ);
1693
1694 if (!pwrpriv->bkeepfwalive) {
1695
1696 usb_write32(Adapter, REG_RXPKT_NUM, (usb_read32(Adapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1697 do {
1698 if (!(usb_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE))
1699 break;
1700 } while (trycnt--);
1701 if (trycnt == 0)
1702 DBG_88E("Stop RX DMA failed......\n");
1703
1704
1705 usb_write16(Adapter, REG_RQPN_NPQ, 0x0);
1706 usb_write32(Adapter, REG_RQPN, 0x80000000);
1707 mdelay(10);
1708 }
1709 }
1710 break;
1711 case HW_VAR_CHECK_TXBUF:
1712 break;
1713 case HW_VAR_APFM_ON_MAC:
1714 haldata->bMacPwrCtrlOn = *val;
1715 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
1716 break;
1717 case HW_VAR_TX_RPT_MAX_MACID:
1718 {
1719 u8 maxMacid = *val;
1720 DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1);
1721 usb_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
1722 }
1723 break;
1724 case HW_VAR_H2C_MEDIA_STATUS_RPT:
1725 rtl8188e_set_FwMediaStatus_cmd(Adapter, (*(__le16 *)val));
1726 break;
1727 case HW_VAR_BCN_VALID:
1728
1729 usb_write8(Adapter, REG_TDECTRL+2, usb_read8(Adapter, REG_TDECTRL+2) | BIT(0));
1730 break;
1731 default:
1732 break;
1733 }
1734}
1735
1736void rtw_hal_get_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
1737{
1738 switch (variable) {
1739 case HW_VAR_BASIC_RATE:
1740 *((u16 *)(val)) = Adapter->HalData->BasicRateSet;
1741 case HW_VAR_TXPAUSE:
1742 val[0] = usb_read8(Adapter, REG_TXPAUSE);
1743 break;
1744 case HW_VAR_BCN_VALID:
1745
1746 val[0] = (BIT(0) & usb_read8(Adapter, REG_TDECTRL+2)) ? true : false;
1747 break;
1748 case HW_VAR_RF_TYPE:
1749 val[0] = RF_1T1R;
1750 break;
1751 case HW_VAR_FWLPS_RF_ON:
1752 {
1753
1754 if (Adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
1755
1756
1757 val[0] = true;
1758 } else {
1759 u32 valRCR;
1760 valRCR = usb_read32(Adapter, REG_RCR);
1761 valRCR &= 0x00070000;
1762 if (valRCR)
1763 val[0] = false;
1764 else
1765 val[0] = true;
1766 }
1767 }
1768 break;
1769 case HW_VAR_CURRENT_ANTENNA:
1770 val[0] = Adapter->HalData->CurAntenna;
1771 break;
1772 case HW_VAR_EFUSE_BYTES:
1773 *((u16 *)(val)) = Adapter->HalData->EfuseUsedBytes;
1774 break;
1775 case HW_VAR_APFM_ON_MAC:
1776 *val = Adapter->HalData->bMacPwrCtrlOn;
1777 break;
1778 case HW_VAR_CHK_HI_QUEUE_EMPTY:
1779 *val = ((usb_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00) == 0) ? true : false;
1780 break;
1781 default:
1782 break;
1783 }
1784}
1785
1786
1787
1788
1789
1790u8 rtw_hal_get_def_var(
1791 struct adapter *Adapter,
1792 enum hal_def_variable eVariable,
1793 void *pValue
1794 )
1795{
1796 struct hal_data_8188e *haldata = Adapter->HalData;
1797 u8 bResult = _SUCCESS;
1798
1799 switch (eVariable) {
1800 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1801 {
1802 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1803 struct sta_priv *pstapriv = &Adapter->stapriv;
1804 struct sta_info *psta;
1805 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1806 if (psta)
1807 *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1808 }
1809 break;
1810 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1811 *((u8 *)pValue) = (haldata->AntDivCfg == 0) ? false : true;
1812 break;
1813 case HAL_DEF_CURRENT_ANTENNA:
1814 *((u8 *)pValue) = haldata->CurAntenna;
1815 break;
1816 case HAL_DEF_DRVINFO_SZ:
1817 *((u32 *)pValue) = DRVINFO_SZ;
1818 break;
1819 case HAL_DEF_MAX_RECVBUF_SZ:
1820 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1821 break;
1822 case HAL_DEF_RX_PACKET_OFFSET:
1823 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1824 break;
1825 case HAL_DEF_DBG_DM_FUNC:
1826 *((u32 *)pValue) = haldata->odmpriv.SupportAbility;
1827 break;
1828 case HAL_DEF_RA_DECISION_RATE:
1829 {
1830 u8 MacID = *((u8 *)pValue);
1831 *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, MacID);
1832 }
1833 break;
1834 case HAL_DEF_RA_SGI:
1835 {
1836 u8 MacID = *((u8 *)pValue);
1837 *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&haldata->odmpriv, MacID);
1838 }
1839 break;
1840 case HAL_DEF_PT_PWR_STATUS:
1841 {
1842 u8 MacID = *((u8 *)pValue);
1843 *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, MacID);
1844 }
1845 break;
1846 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1847 *((u32 *)pValue) = MAX_AMPDU_FACTOR_64K;
1848 break;
1849 case HW_DEF_RA_INFO_DUMP:
1850 {
1851 u8 entry_id = *((u8 *)pValue);
1852 if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
1853 DBG_88E("============ RA status check ===================\n");
1854 DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
1855 entry_id,
1856 haldata->odmpriv.RAInfo[entry_id].RateID,
1857 haldata->odmpriv.RAInfo[entry_id].RAUseRate,
1858 haldata->odmpriv.RAInfo[entry_id].RateSGI,
1859 haldata->odmpriv.RAInfo[entry_id].DecisionRate,
1860 haldata->odmpriv.RAInfo[entry_id].PTStage);
1861 }
1862 }
1863 break;
1864 case HW_DEF_ODM_DBG_FLAG:
1865 {
1866 struct odm_dm_struct *dm_ocm = &haldata->odmpriv;
1867 pr_info("dm_ocm->DebugComponents = 0x%llx\n", dm_ocm->DebugComponents);
1868 }
1869 break;
1870 case HAL_DEF_DBG_DUMP_RXPKT:
1871 *((u8 *)pValue) = haldata->bDumpRxPkt;
1872 break;
1873 case HAL_DEF_DBG_DUMP_TXPKT:
1874 *((u8 *)pValue) = haldata->bDumpTxPkt;
1875 break;
1876 default:
1877 bResult = _FAIL;
1878 break;
1879 }
1880
1881 return bResult;
1882}
1883
1884void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
1885{
1886 u8 init_rate = 0;
1887 u8 networkType, raid;
1888 u32 mask, rate_bitmap;
1889 u8 shortGIrate = false;
1890 int supportRateNum = 0;
1891 struct sta_info *psta;
1892 struct odm_dm_struct *odmpriv = &adapt->HalData->odmpriv;
1893 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
1894 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1895 struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
1896
1897 if (mac_id >= NUM_STA)
1898 return;
1899 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
1900 if (psta == NULL)
1901 return;
1902 switch (mac_id) {
1903 case 0:
1904 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
1905 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
1906 raid = networktype_to_raid(networkType);
1907 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
1908 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&pmlmeinfo->HT_caps) : 0;
1909 if (support_short_GI(adapt, &pmlmeinfo->HT_caps))
1910 shortGIrate = true;
1911 break;
1912 case 1:
1913 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1914 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
1915 networkType = WIRELESS_11B;
1916 else
1917 networkType = WIRELESS_11G;
1918 raid = networktype_to_raid(networkType);
1919 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
1920 break;
1921 default:
1922 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1923 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
1924 raid = networktype_to_raid(networkType);
1925 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
1926
1927
1928 break;
1929 }
1930
1931 rate_bitmap = ODM_Get_Rate_Bitmap(odmpriv, mac_id, mask, rssi_level);
1932 DBG_88E("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
1933 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
1934
1935 mask &= rate_bitmap;
1936
1937 init_rate = get_highest_rate_idx(mask)&0x3f;
1938
1939 ODM_RA_UpdateRateInfo_8188E(odmpriv, mac_id, raid, mask, shortGIrate);
1940
1941
1942 psta->raid = raid;
1943 psta->init_rate = init_rate;
1944}
1945
1946void rtw_hal_bcn_related_reg_setting(struct adapter *adapt)
1947{
1948 u32 value32;
1949 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
1950 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1951 u32 bcn_ctrl_reg = REG_BCN_CTRL;
1952
1953
1954
1955 usb_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
1956 usb_write8(adapt, REG_ATIMWND, 0x02);
1957
1958 _InitBeaconParameters(adapt);
1959
1960 usb_write8(adapt, REG_SLOT, 0x09);
1961
1962 value32 = usb_read32(adapt, REG_TCR);
1963 value32 &= ~TSFRST;
1964 usb_write32(adapt, REG_TCR, value32);
1965
1966 value32 |= TSFRST;
1967 usb_write32(adapt, REG_TCR, value32);
1968
1969
1970 usb_write8(adapt, REG_RXTSF_OFFSET_CCK, 0x50);
1971 usb_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
1972
1973 _BeaconFunctionEnable(adapt, true, true);
1974
1975 ResumeTxBeacon(adapt);
1976
1977 usb_write8(adapt, bcn_ctrl_reg, usb_read8(adapt, bcn_ctrl_reg) | BIT(1));
1978}
1979
1980void rtw_hal_def_value_init(struct adapter *adapt)
1981{
1982 struct hal_data_8188e *haldata = adapt->HalData;
1983 struct pwrctrl_priv *pwrctrlpriv;
1984 u8 i;
1985
1986 pwrctrlpriv = &adapt->pwrctrlpriv;
1987
1988
1989 if (!pwrctrlpriv->bkeepfwalive)
1990 haldata->LastHMEBoxNum = 0;
1991
1992
1993 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
1994 haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;
1995 haldata->pwrGroupCnt = 0;
1996 haldata->PGMaxGroup = 13;
1997 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
1998 for (i = 0; i < HP_THERMAL_NUM; i++)
1999 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
2000}
2001