LXR linux/drivers/staging/rtl8192u/r819xU

   1#ifndef R819XUSB_CMDPKT_H
   2#define R819XUSB_CMDPKT_H
   3/* Different command packet have dedicated message length and definition. */
   4#define         CMPK_RX_TX_FB_SIZE              sizeof(cmpk_txfb_t)     /* 20 */
   5#define         CMPK_TX_SET_CONFIG_SIZE         sizeof(cmpk_set_cfg_t)  /* 16 */
   6#define         CMPK_BOTH_QUERY_CONFIG_SIZE     sizeof(cmpk_set_cfg_t)  /* 16 */
   7#define         CMPK_RX_TX_STS_SIZE             sizeof(cmpk_tx_status_t)
   8#define         CMPK_RX_DBG_MSG_SIZE            sizeof(cmpk_rx_dbginfo_t)
   9#define         CMPK_TX_RAHIS_SIZE              sizeof(cmpk_tx_rahis_t)
  10
  11/* 2008/05/08 amy For USB constant. */
  12#define ISR_TxBcnOk             BIT(27)         /* Transmit Beacon OK */
  13#define ISR_TxBcnErr            BIT(26)         /* Transmit Beacon Error */
  14#define ISR_BcnTimerIntr        BIT(13)         /* Beacon Timer Interrupt */
  15
  16
  17/* Define element ID of command packet. */
  18
  19/*------------------------------Define structure----------------------------*/
  20/* Define different command packet structure. */
  21/* 1. RX side: TX feedback packet. */
  22typedef struct tag_cmd_pkt_tx_feedback {
  23        /* DWORD 0 */
  24        u8      element_id;                     /* Command packet type. */
  25        u8      length;                         /* Command packet length. */
  26        /* Change tx feedback info field. */
  27        /*------TX Feedback Info Field */
  28        u8      TID:4;
  29        u8      fail_reason:3;
  30        u8      tok:1;                          /* Transmit ok. */
  31        u8      reserve1:4;
  32        u8      pkt_type:2;
  33        u8      bandwidth:1;
  34        u8      qos_pkt:1;
  35
  36        /* DWORD 1 */
  37        u8      reserve2;
  38        /*------TX Feedback Info Field */
  39        u8      retry_cnt;
  40        u16     pkt_id;
  41
  42        /* DWORD 3 */
  43        u16     seq_num;
  44        u8      s_rate;                         /* Start rate. */
  45        u8      f_rate;                         /* Final rate. */
  46
  47        /* DWORD 4 */
  48        u8      s_rts_rate;
  49        u8      f_rts_rate;
  50        u16     pkt_length;
  51
  52        /* DWORD 5 */
  53        u16     reserve3;
  54        u16     duration;
  55} cmpk_txfb_t;
  56
  57/* 2. RX side: Interrupt status packet. It includes Beacon State,
  58 * Beacon Timer Interrupt and other useful informations in MAC ISR Reg.
  59 */
  60typedef struct tag_cmd_pkt_interrupt_status {
  61        u8      element_id;                     /* Command packet type. */
  62        u8      length;                         /* Command packet length. */
  63        u16     reserve;
  64        u32     interrupt_status;               /* Interrupt Status. */
  65} cmpk_intr_sta_t;
  66
  67
  68/* 3. TX side: Set configuration packet. */
  69typedef struct tag_cmd_pkt_set_configuration {
  70        u8      element_id;                     /* Command packet type. */
  71        u8      length;                         /* Command packet length. */
  72        u16     reserve1;
  73        /* Configuration info. */
  74        u8      cfg_reserve1:3;
  75        u8      cfg_size:2;
  76        u8      cfg_type:2;
  77        u8      cfg_action:1;
  78        u8      cfg_reserve2;
  79        u8      cfg_page:4;
  80        u8      cfg_reserve3:4;
  81        u8      cfg_offset;
  82        u32     value;
  83        u32     mask;
  84} cmpk_set_cfg_t;
  85
  86/* 4. Both side : TX/RX query configuraton packet. The query structure is the
  87 *    same as set configuration.
  88 */
  89#define         cmpk_query_cfg_t        cmpk_set_cfg_t
  90
  91/* 5. Multi packet feedback status. */
  92typedef struct tag_tx_stats_feedback {
  93        /* For endian transfer --> Driver will not the same as
  94         *  firmware structure.
  95         */
  96        /* DW 0 */
  97        u16     reserve1;
  98        u8      length;                         /* Command packet length */
  99        u8      element_id;                     /* Command packet type */
 100
 101        /* DW 1 */
 102        u16     txfail;                         /* Tx fail count */
 103        u16     txok;                           /* Tx ok count */
 104
 105        /* DW 2 */
 106        u16     txmcok;                         /* Tx multicast */
 107        u16     txretry;                        /* Tx retry count */
 108
 109        /* DW 3 */
 110        u16     txucok;                         /* Tx unicast */
 111        u16     txbcok;                         /* Tx broadcast */
 112
 113        /* DW 4 */
 114        u16     txbcfail;
 115        u16     txmcfail;
 116
 117        /* DW 5 */
 118        u16     reserve2;
 119        u16     txucfail;
 120
 121        /* DW 6-8 */
 122        u32     txmclength;
 123        u32     txbclength;
 124        u32     txuclength;
 125
 126        /* DW 9 */
 127        u16     reserve3_23;
 128        u8      reserve3_1;
 129        u8      rate;
 130} __packed cmpk_tx_status_t;
 131
 132/* 6. Debug feedback message. */
 133/* Define RX debug message  */
 134typedef struct tag_rx_debug_message_feedback {
 135        /* For endian transfer --> for driver */
 136        /* DW 0 */
 137        u16     reserve1;
 138        u8      length;                         /* Command packet length */
 139        u8      element_id;                     /* Command packet type */
 140
 141        /* DW 1-?? */
 142        /* Variable debug message. */
 143
 144} cmpk_rx_dbginfo_t;
 145
 146/* Define transmit rate history. For big endian format. */
 147typedef struct tag_tx_rate_history {
 148        /* For endian transfer --> for driver */
 149        /* DW 0 */
 150        u8      element_id;                     /* Command packet type */
 151        u8      length;                         /* Command packet length */
 152        u16     reserved1;
 153
 154        /* DW 1-2       CCK rate counter */
 155        u16     cck[4];
 156
 157        /* DW 3-6 */
 158        u16     ofdm[8];
 159
 160        /* DW 7-14      BW=0 SG=0
 161         * DW 15-22     BW=1 SG=0
 162         * DW 23-30     BW=0 SG=1
 163         * DW 31-38     BW=1 SG=1
 164         */
 165        u16     ht_mcs[4][16];
 166
 167} __packed cmpk_tx_rahis_t;
 168
 169typedef enum tag_command_packet_directories {
 170        RX_TX_FEEDBACK                  = 0,
 171        RX_INTERRUPT_STATUS             = 1,
 172        TX_SET_CONFIG                   = 2,
 173        BOTH_QUERY_CONFIG               = 3,
 174        RX_TX_STATUS                    = 4,
 175        RX_DBGINFO_FEEDBACK             = 5,
 176        RX_TX_PER_PKT_FEEDBACK          = 6,
 177        RX_TX_RATE_HISTORY              = 7,
 178        RX_CMD_ELE_MAX
 179} cmpk_element_e;
 180
 181typedef enum _rt_status {
 182        RT_STATUS_SUCCESS,
 183        RT_STATUS_FAILURE,
 184        RT_STATUS_PENDING,
 185        RT_STATUS_RESOURCE
 186} rt_status, *prt_status;
 187
 188u32 cmpk_message_handle_rx(struct net_device *dev,
 189                           struct ieee80211_rx_stats *pstats);
 190rt_status SendTxCommandPacket(struct net_device *dev,
 191                              void *pData, u32 DataLen);
 192
 193
 194#endif
 195