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23#include <linux/blkdev.h>
24#include <linux/kthread.h>
25#include <linux/sched.h>
26#include <linux/workqueue.h>
27#include <linux/kernel.h>
28
29#include "rtsx.h"
30#include "sd.h"
31#include "xd.h"
32#include "ms.h"
33
34void do_remaining_work(struct rtsx_chip *chip)
35{
36 struct sd_info *sd_card = &chip->sd_card;
37#ifdef XD_DELAY_WRITE
38 struct xd_info *xd_card = &chip->xd_card;
39#endif
40 struct ms_info *ms_card = &chip->ms_card;
41
42 if (chip->card_ready & SD_CARD) {
43 if (sd_card->seq_mode) {
44 rtsx_set_stat(chip, RTSX_STAT_RUN);
45 sd_card->cleanup_counter++;
46 } else {
47 sd_card->cleanup_counter = 0;
48 }
49 }
50
51#ifdef XD_DELAY_WRITE
52 if (chip->card_ready & XD_CARD) {
53 if (xd_card->delay_write.delay_write_flag) {
54 rtsx_set_stat(chip, RTSX_STAT_RUN);
55 xd_card->cleanup_counter++;
56 } else {
57 xd_card->cleanup_counter = 0;
58 }
59 }
60#endif
61
62 if (chip->card_ready & MS_CARD) {
63 if (CHK_MSPRO(ms_card)) {
64 if (ms_card->seq_mode) {
65 rtsx_set_stat(chip, RTSX_STAT_RUN);
66 ms_card->cleanup_counter++;
67 } else {
68 ms_card->cleanup_counter = 0;
69 }
70 } else {
71#ifdef MS_DELAY_WRITE
72 if (ms_card->delay_write.delay_write_flag) {
73 rtsx_set_stat(chip, RTSX_STAT_RUN);
74 ms_card->cleanup_counter++;
75 } else {
76 ms_card->cleanup_counter = 0;
77 }
78#endif
79 }
80 }
81
82 if (sd_card->cleanup_counter > POLLING_WAIT_CNT)
83 sd_cleanup_work(chip);
84
85 if (xd_card->cleanup_counter > POLLING_WAIT_CNT)
86 xd_cleanup_work(chip);
87
88 if (ms_card->cleanup_counter > POLLING_WAIT_CNT)
89 ms_cleanup_work(chip);
90}
91
92void try_to_switch_sdio_ctrl(struct rtsx_chip *chip)
93{
94 u8 reg1 = 0, reg2 = 0;
95
96 rtsx_read_register(chip, 0xFF34, ®1);
97 rtsx_read_register(chip, 0xFF38, ®2);
98 dev_dbg(rtsx_dev(chip), "reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n",
99 reg1, reg2);
100 if ((reg1 & 0xC0) && (reg2 & 0xC0)) {
101 chip->sd_int = 1;
102 rtsx_write_register(chip, SDIO_CTRL, 0xFF,
103 SDIO_BUS_CTRL | SDIO_CD_CTRL);
104 rtsx_write_register(chip, PWR_GATE_CTRL,
105 LDO3318_PWR_MASK, LDO_ON);
106 }
107}
108
109#ifdef SUPPORT_SDIO_ASPM
110void dynamic_configure_sdio_aspm(struct rtsx_chip *chip)
111{
112 u8 buf[12], reg;
113 int i;
114
115 for (i = 0; i < 12; i++)
116 rtsx_read_register(chip, 0xFF08 + i, &buf[i]);
117 rtsx_read_register(chip, 0xFF25, ®);
118 if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) {
119 chip->sdio_counter = 0;
120 chip->sdio_idle = 0;
121 } else {
122 if (!chip->sdio_idle) {
123 chip->sdio_counter++;
124 if (chip->sdio_counter >= SDIO_IDLE_COUNT) {
125 chip->sdio_counter = 0;
126 chip->sdio_idle = 1;
127 }
128 }
129 }
130 memcpy(chip->sdio_raw_data, buf, 12);
131
132 if (chip->sdio_idle) {
133 if (!chip->sdio_aspm) {
134 dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
135 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC,
136 0x30 | (chip->aspm_level[1] << 2));
137 chip->sdio_aspm = 1;
138 }
139 } else {
140 if (chip->sdio_aspm) {
141 dev_dbg(rtsx_dev(chip), "SDIO exit ASPM!\n");
142 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30);
143 chip->sdio_aspm = 0;
144 }
145 }
146}
147#endif
148
149void do_reset_sd_card(struct rtsx_chip *chip)
150{
151 int retval;
152
153 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
154 chip->sd_reset_counter, chip->card2lun[SD_CARD]);
155
156 if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT) {
157 clear_bit(SD_NR, &chip->need_reset);
158 chip->sd_reset_counter = 0;
159 chip->sd_show_cnt = 0;
160 return;
161 }
162
163 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
164
165 rtsx_set_stat(chip, RTSX_STAT_RUN);
166 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
167
168 retval = reset_sd_card(chip);
169 if (chip->need_release & SD_CARD)
170 return;
171 if (retval == STATUS_SUCCESS) {
172 clear_bit(SD_NR, &chip->need_reset);
173 chip->sd_reset_counter = 0;
174 chip->sd_show_cnt = 0;
175 chip->card_ready |= SD_CARD;
176 chip->card_fail &= ~SD_CARD;
177 chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
178 } else {
179 if (chip->sd_io || (chip->sd_reset_counter >= MAX_RESET_CNT)) {
180 clear_bit(SD_NR, &chip->need_reset);
181 chip->sd_reset_counter = 0;
182 chip->sd_show_cnt = 0;
183 } else {
184 chip->sd_reset_counter++;
185 }
186 chip->card_ready &= ~SD_CARD;
187 chip->card_fail |= SD_CARD;
188 chip->capacity[chip->card2lun[SD_CARD]] = 0;
189 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
190
191 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
192 if (!chip->ft2_fast_mode)
193 card_power_off(chip, SD_CARD);
194 if (chip->sd_io) {
195 chip->sd_int = 0;
196 try_to_switch_sdio_ctrl(chip);
197 } else {
198 disable_card_clock(chip, SD_CARD);
199 }
200 }
201}
202
203void do_reset_xd_card(struct rtsx_chip *chip)
204{
205 int retval;
206
207 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
208 chip->xd_reset_counter, chip->card2lun[XD_CARD]);
209
210 if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT) {
211 clear_bit(XD_NR, &chip->need_reset);
212 chip->xd_reset_counter = 0;
213 chip->xd_show_cnt = 0;
214 return;
215 }
216
217 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
218
219 rtsx_set_stat(chip, RTSX_STAT_RUN);
220 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
221
222 retval = reset_xd_card(chip);
223 if (chip->need_release & XD_CARD)
224 return;
225 if (retval == STATUS_SUCCESS) {
226 clear_bit(XD_NR, &chip->need_reset);
227 chip->xd_reset_counter = 0;
228 chip->card_ready |= XD_CARD;
229 chip->card_fail &= ~XD_CARD;
230 chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
231 } else {
232 if (chip->xd_reset_counter >= MAX_RESET_CNT) {
233 clear_bit(XD_NR, &chip->need_reset);
234 chip->xd_reset_counter = 0;
235 chip->xd_show_cnt = 0;
236 } else {
237 chip->xd_reset_counter++;
238 }
239 chip->card_ready &= ~XD_CARD;
240 chip->card_fail |= XD_CARD;
241 chip->capacity[chip->card2lun[XD_CARD]] = 0;
242 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
243
244 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
245 if (!chip->ft2_fast_mode)
246 card_power_off(chip, XD_CARD);
247 disable_card_clock(chip, XD_CARD);
248 }
249}
250
251void do_reset_ms_card(struct rtsx_chip *chip)
252{
253 int retval;
254
255 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
256 chip->ms_reset_counter, chip->card2lun[MS_CARD]);
257
258 if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT) {
259 clear_bit(MS_NR, &chip->need_reset);
260 chip->ms_reset_counter = 0;
261 chip->ms_show_cnt = 0;
262 return;
263 }
264
265 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
266
267 rtsx_set_stat(chip, RTSX_STAT_RUN);
268 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
269
270 retval = reset_ms_card(chip);
271 if (chip->need_release & MS_CARD)
272 return;
273 if (retval == STATUS_SUCCESS) {
274 clear_bit(MS_NR, &chip->need_reset);
275 chip->ms_reset_counter = 0;
276 chip->card_ready |= MS_CARD;
277 chip->card_fail &= ~MS_CARD;
278 chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
279 } else {
280 if (chip->ms_reset_counter >= MAX_RESET_CNT) {
281 clear_bit(MS_NR, &chip->need_reset);
282 chip->ms_reset_counter = 0;
283 chip->ms_show_cnt = 0;
284 } else {
285 chip->ms_reset_counter++;
286 }
287 chip->card_ready &= ~MS_CARD;
288 chip->card_fail |= MS_CARD;
289 chip->capacity[chip->card2lun[MS_CARD]] = 0;
290 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
291
292 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
293 if (!chip->ft2_fast_mode)
294 card_power_off(chip, MS_CARD);
295 disable_card_clock(chip, MS_CARD);
296 }
297}
298
299static void release_sdio(struct rtsx_chip *chip)
300{
301 if (chip->sd_io) {
302 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
303 SD_STOP | SD_CLR_ERR);
304
305 if (chip->chip_insert_with_sdio) {
306 chip->chip_insert_with_sdio = 0;
307
308 if (CHECK_PID(chip, 0x5288))
309 rtsx_write_register(chip, 0xFE5A, 0x08, 0x00);
310 else
311 rtsx_write_register(chip, 0xFE70, 0x80, 0x00);
312 }
313
314 rtsx_write_register(chip, SDIO_CTRL, SDIO_CD_CTRL, 0);
315 chip->sd_io = 0;
316 }
317}
318
319void rtsx_power_off_card(struct rtsx_chip *chip)
320{
321 if ((chip->card_ready & SD_CARD) || chip->sd_io) {
322 sd_cleanup_work(chip);
323 sd_power_off_card3v3(chip);
324 }
325
326 if (chip->card_ready & XD_CARD) {
327 xd_cleanup_work(chip);
328 xd_power_off_card3v3(chip);
329 }
330
331 if (chip->card_ready & MS_CARD) {
332 ms_cleanup_work(chip);
333 ms_power_off_card3v3(chip);
334 }
335}
336
337void rtsx_release_cards(struct rtsx_chip *chip)
338{
339 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
340
341 if ((chip->card_ready & SD_CARD) || chip->sd_io) {
342 if (chip->int_reg & SD_EXIST)
343 sd_cleanup_work(chip);
344 release_sd_card(chip);
345 }
346
347 if (chip->card_ready & XD_CARD) {
348 if (chip->int_reg & XD_EXIST)
349 xd_cleanup_work(chip);
350 release_xd_card(chip);
351 }
352
353 if (chip->card_ready & MS_CARD) {
354 if (chip->int_reg & MS_EXIST)
355 ms_cleanup_work(chip);
356 release_ms_card(chip);
357 }
358}
359
360void rtsx_reset_cards(struct rtsx_chip *chip)
361{
362 if (!chip->need_reset)
363 return;
364
365 rtsx_set_stat(chip, RTSX_STAT_RUN);
366
367 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
368
369 rtsx_disable_aspm(chip);
370
371 if ((chip->need_reset & SD_CARD) && chip->chip_insert_with_sdio)
372 clear_bit(SD_NR, &chip->need_reset);
373
374 if (chip->need_reset & XD_CARD) {
375 chip->card_exist |= XD_CARD;
376
377 if (chip->xd_show_cnt >= MAX_SHOW_CNT)
378 do_reset_xd_card(chip);
379 else
380 chip->xd_show_cnt++;
381 }
382 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
383 if (chip->card_exist & XD_CARD) {
384 clear_bit(SD_NR, &chip->need_reset);
385 clear_bit(MS_NR, &chip->need_reset);
386 }
387 }
388 if (chip->need_reset & SD_CARD) {
389 chip->card_exist |= SD_CARD;
390
391 if (chip->sd_show_cnt >= MAX_SHOW_CNT) {
392 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
393 do_reset_sd_card(chip);
394 } else {
395 chip->sd_show_cnt++;
396 }
397 }
398 if (chip->need_reset & MS_CARD) {
399 chip->card_exist |= MS_CARD;
400
401 if (chip->ms_show_cnt >= MAX_SHOW_CNT)
402 do_reset_ms_card(chip);
403 else
404 chip->ms_show_cnt++;
405 }
406}
407
408void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip)
409{
410 rtsx_set_stat(chip, RTSX_STAT_RUN);
411
412 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
413
414 if (reset_chip)
415 rtsx_reset_chip(chip);
416
417 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
418
419 if ((chip->int_reg & SD_EXIST) && (chip->need_reinit & SD_CARD)) {
420 release_sdio(chip);
421 release_sd_card(chip);
422
423 wait_timeout(100);
424
425 chip->card_exist |= SD_CARD;
426 do_reset_sd_card(chip);
427 }
428
429 if ((chip->int_reg & XD_EXIST) && (chip->need_reinit & XD_CARD)) {
430 release_xd_card(chip);
431
432 wait_timeout(100);
433
434 chip->card_exist |= XD_CARD;
435 do_reset_xd_card(chip);
436 }
437
438 if ((chip->int_reg & MS_EXIST) && (chip->need_reinit & MS_CARD)) {
439 release_ms_card(chip);
440
441 wait_timeout(100);
442
443 chip->card_exist |= MS_CARD;
444 do_reset_ms_card(chip);
445 }
446
447 chip->need_reinit = 0;
448}
449
450#ifdef DISABLE_CARD_INT
451void card_cd_debounce(struct rtsx_chip *chip, unsigned long *need_reset,
452 unsigned long *need_release)
453{
454 u8 release_map = 0, reset_map = 0;
455
456 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
457
458 if (chip->card_exist) {
459 if (chip->card_exist & XD_CARD) {
460 if (!(chip->int_reg & XD_EXIST))
461 release_map |= XD_CARD;
462 } else if (chip->card_exist & SD_CARD) {
463 if (!(chip->int_reg & SD_EXIST))
464 release_map |= SD_CARD;
465 } else if (chip->card_exist & MS_CARD) {
466 if (!(chip->int_reg & MS_EXIST))
467 release_map |= MS_CARD;
468 }
469 } else {
470 if (chip->int_reg & XD_EXIST)
471 reset_map |= XD_CARD;
472 else if (chip->int_reg & SD_EXIST)
473 reset_map |= SD_CARD;
474 else if (chip->int_reg & MS_EXIST)
475 reset_map |= MS_CARD;
476 }
477
478 if (reset_map) {
479 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
480 int i;
481
482 for (i = 0; i < (DEBOUNCE_CNT); i++) {
483 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
484
485 if (chip->int_reg & XD_EXIST)
486 xd_cnt++;
487 else
488 xd_cnt = 0;
489
490 if (chip->int_reg & SD_EXIST)
491 sd_cnt++;
492 else
493 sd_cnt = 0;
494
495 if (chip->int_reg & MS_EXIST)
496 ms_cnt++;
497 else
498 ms_cnt = 0;
499
500 wait_timeout(30);
501 }
502
503 reset_map = 0;
504 if (!(chip->card_exist & XD_CARD) &&
505 (xd_cnt > (DEBOUNCE_CNT - 1)))
506 reset_map |= XD_CARD;
507 if (!(chip->card_exist & SD_CARD) &&
508 (sd_cnt > (DEBOUNCE_CNT - 1)))
509 reset_map |= SD_CARD;
510 if (!(chip->card_exist & MS_CARD) &&
511 (ms_cnt > (DEBOUNCE_CNT - 1)))
512 reset_map |= MS_CARD;
513 }
514
515 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
516 rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00);
517
518 if (need_reset)
519 *need_reset = reset_map;
520 if (need_release)
521 *need_release = release_map;
522}
523#endif
524
525void rtsx_init_cards(struct rtsx_chip *chip)
526{
527 if (RTSX_TST_DELINK(chip) && (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
528 dev_dbg(rtsx_dev(chip), "Reset chip in polling thread!\n");
529 rtsx_reset_chip(chip);
530 RTSX_CLR_DELINK(chip);
531 }
532
533#ifdef DISABLE_CARD_INT
534 card_cd_debounce(chip, &chip->need_reset, &chip->need_release);
535#endif
536
537 if (chip->need_release) {
538 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
539 if (chip->int_reg & XD_EXIST) {
540 clear_bit(SD_NR, &chip->need_release);
541 clear_bit(MS_NR, &chip->need_release);
542 }
543 }
544
545 if (!(chip->card_exist & SD_CARD) && !chip->sd_io)
546 clear_bit(SD_NR, &chip->need_release);
547 if (!(chip->card_exist & XD_CARD))
548 clear_bit(XD_NR, &chip->need_release);
549 if (!(chip->card_exist & MS_CARD))
550 clear_bit(MS_NR, &chip->need_release);
551
552 dev_dbg(rtsx_dev(chip), "chip->need_release = 0x%x\n",
553 (unsigned int)(chip->need_release));
554
555#ifdef SUPPORT_OCP
556 if (chip->need_release) {
557 if (chip->ocp_stat & (CARD_OC_NOW | CARD_OC_EVER))
558 rtsx_write_register(chip, OCPCLR,
559 CARD_OC_INT_CLR |
560 CARD_OC_CLR,
561 CARD_OC_INT_CLR |
562 CARD_OC_CLR);
563 chip->ocp_stat = 0;
564 }
565#endif
566 if (chip->need_release) {
567 rtsx_set_stat(chip, RTSX_STAT_RUN);
568 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
569 }
570
571 if (chip->need_release & SD_CARD) {
572 clear_bit(SD_NR, &chip->need_release);
573 chip->card_exist &= ~SD_CARD;
574 chip->card_ejected &= ~SD_CARD;
575 chip->card_fail &= ~SD_CARD;
576 CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]);
577 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
578 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
579
580 release_sdio(chip);
581 release_sd_card(chip);
582 }
583
584 if (chip->need_release & XD_CARD) {
585 clear_bit(XD_NR, &chip->need_release);
586 chip->card_exist &= ~XD_CARD;
587 chip->card_ejected &= ~XD_CARD;
588 chip->card_fail &= ~XD_CARD;
589 CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]);
590 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
591
592 release_xd_card(chip);
593
594 if (CHECK_PID(chip, 0x5288) &&
595 CHECK_BARO_PKG(chip, QFN))
596 rtsx_write_register(chip, HOST_SLEEP_STATE,
597 0xC0, 0xC0);
598 }
599
600 if (chip->need_release & MS_CARD) {
601 clear_bit(MS_NR, &chip->need_release);
602 chip->card_exist &= ~MS_CARD;
603 chip->card_ejected &= ~MS_CARD;
604 chip->card_fail &= ~MS_CARD;
605 CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]);
606 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
607
608 release_ms_card(chip);
609 }
610
611 dev_dbg(rtsx_dev(chip), "chip->card_exist = 0x%x\n",
612 chip->card_exist);
613
614 if (!chip->card_exist)
615 turn_off_led(chip, LED_GPIO);
616 }
617
618 if (chip->need_reset) {
619 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x\n",
620 (unsigned int)(chip->need_reset));
621
622 rtsx_reset_cards(chip);
623 }
624
625 if (chip->need_reinit) {
626 dev_dbg(rtsx_dev(chip), "chip->need_reinit = 0x%x\n",
627 (unsigned int)(chip->need_reinit));
628
629 rtsx_reinit_cards(chip, 0);
630 }
631}
632
633int switch_ssc_clock(struct rtsx_chip *chip, int clk)
634{
635 int retval;
636 u8 n = (u8)(clk - 2), min_n, max_n;
637 u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask;
638 int sd_vpclk_phase_reset = 0;
639
640 if (chip->cur_clk == clk)
641 return STATUS_SUCCESS;
642
643 min_n = 60;
644 max_n = 120;
645 max_div = CLK_DIV_4;
646
647 dev_dbg(rtsx_dev(chip), "Switch SSC clock to %dMHz (cur_clk = %d)\n",
648 clk, chip->cur_clk);
649
650 if ((clk <= 2) || (n > max_n)) {
651 rtsx_trace(chip);
652 return STATUS_FAIL;
653 }
654
655 mcu_cnt = (u8)(125 / clk + 3);
656 if (mcu_cnt > 7)
657 mcu_cnt = 7;
658
659 div = CLK_DIV_1;
660 while ((n < min_n) && (div < max_div)) {
661 n = (n + 2) * 2 - 2;
662 div++;
663 }
664 dev_dbg(rtsx_dev(chip), "n = %d, div = %d\n", n, div);
665
666 if (chip->ssc_en) {
667 ssc_depth = 0x01;
668 n -= 2;
669 } else {
670 ssc_depth = 0;
671 }
672
673 ssc_depth_mask = 0x03;
674
675 dev_dbg(rtsx_dev(chip), "ssc_depth = %d\n", ssc_depth);
676
677 rtsx_init_cmd(chip);
678 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
679 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
680 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
681 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth);
682 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
683 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
684 if (sd_vpclk_phase_reset) {
685 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
686 PHASE_NOT_RESET, 0);
687 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
688 PHASE_NOT_RESET, PHASE_NOT_RESET);
689 }
690
691 retval = rtsx_send_cmd(chip, 0, WAIT_TIME);
692 if (retval < 0) {
693 rtsx_trace(chip);
694 return STATUS_ERROR;
695 }
696
697 udelay(10);
698 retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0);
699 if (retval) {
700 rtsx_trace(chip);
701 return retval;
702 }
703
704 chip->cur_clk = clk;
705
706 return STATUS_SUCCESS;
707}
708
709int switch_normal_clock(struct rtsx_chip *chip, int clk)
710{
711 int retval;
712 u8 sel, div, mcu_cnt;
713 int sd_vpclk_phase_reset = 0;
714
715 if (chip->cur_clk == clk)
716 return STATUS_SUCCESS;
717
718 switch (clk) {
719 case CLK_20:
720 dev_dbg(rtsx_dev(chip), "Switch clock to 20MHz\n");
721 sel = SSC_80;
722 div = CLK_DIV_4;
723 mcu_cnt = 7;
724 break;
725
726 case CLK_30:
727 dev_dbg(rtsx_dev(chip), "Switch clock to 30MHz\n");
728 sel = SSC_120;
729 div = CLK_DIV_4;
730 mcu_cnt = 7;
731 break;
732
733 case CLK_40:
734 dev_dbg(rtsx_dev(chip), "Switch clock to 40MHz\n");
735 sel = SSC_80;
736 div = CLK_DIV_2;
737 mcu_cnt = 7;
738 break;
739
740 case CLK_50:
741 dev_dbg(rtsx_dev(chip), "Switch clock to 50MHz\n");
742 sel = SSC_100;
743 div = CLK_DIV_2;
744 mcu_cnt = 6;
745 break;
746
747 case CLK_60:
748 dev_dbg(rtsx_dev(chip), "Switch clock to 60MHz\n");
749 sel = SSC_120;
750 div = CLK_DIV_2;
751 mcu_cnt = 6;
752 break;
753
754 case CLK_80:
755 dev_dbg(rtsx_dev(chip), "Switch clock to 80MHz\n");
756 sel = SSC_80;
757 div = CLK_DIV_1;
758 mcu_cnt = 5;
759 break;
760
761 case CLK_100:
762 dev_dbg(rtsx_dev(chip), "Switch clock to 100MHz\n");
763 sel = SSC_100;
764 div = CLK_DIV_1;
765 mcu_cnt = 5;
766 break;
767
768 case CLK_120:
769 dev_dbg(rtsx_dev(chip), "Switch clock to 120MHz\n");
770 sel = SSC_120;
771 div = CLK_DIV_1;
772 mcu_cnt = 5;
773 break;
774
775 case CLK_150:
776 dev_dbg(rtsx_dev(chip), "Switch clock to 150MHz\n");
777 sel = SSC_150;
778 div = CLK_DIV_1;
779 mcu_cnt = 4;
780 break;
781
782 case CLK_200:
783 dev_dbg(rtsx_dev(chip), "Switch clock to 200MHz\n");
784 sel = SSC_200;
785 div = CLK_DIV_1;
786 mcu_cnt = 4;
787 break;
788
789 default:
790 dev_dbg(rtsx_dev(chip), "Try to switch to an illegal clock (%d)\n",
791 clk);
792 rtsx_trace(chip);
793 return STATUS_FAIL;
794 }
795
796 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ);
797 if (retval) {
798 rtsx_trace(chip);
799 return retval;
800 }
801 if (sd_vpclk_phase_reset) {
802 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
803 PHASE_NOT_RESET, 0);
804 if (retval) {
805 rtsx_trace(chip);
806 return retval;
807 }
808 retval = rtsx_write_register(chip, SD_VPCLK1_CTL,
809 PHASE_NOT_RESET, 0);
810 if (retval) {
811 rtsx_trace(chip);
812 return retval;
813 }
814 }
815 retval = rtsx_write_register(chip, CLK_DIV, 0xFF,
816 (div << 4) | mcu_cnt);
817 if (retval) {
818 rtsx_trace(chip);
819 return retval;
820 }
821 retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel);
822 if (retval) {
823 rtsx_trace(chip);
824 return retval;
825 }
826
827 if (sd_vpclk_phase_reset) {
828 udelay(200);
829 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
830 PHASE_NOT_RESET, PHASE_NOT_RESET);
831 if (retval) {
832 rtsx_trace(chip);
833 return retval;
834 }
835 retval = rtsx_write_register(chip, SD_VPCLK1_CTL,
836 PHASE_NOT_RESET, PHASE_NOT_RESET);
837 if (retval) {
838 rtsx_trace(chip);
839 return retval;
840 }
841 udelay(200);
842 }
843 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0);
844 if (retval) {
845 rtsx_trace(chip);
846 return retval;
847 }
848
849 chip->cur_clk = clk;
850
851 return STATUS_SUCCESS;
852}
853
854void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip,
855 u32 byte_cnt, u8 pack_size)
856{
857 if (pack_size > DMA_1024)
858 pack_size = DMA_512;
859
860 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT);
861
862 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24));
863 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(byte_cnt >> 16));
864 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(byte_cnt >> 8));
865 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC0, 0xFF, (u8)byte_cnt);
866
867 if (dir == DMA_FROM_DEVICE) {
868 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL,
869 0x03 | DMA_PACK_SIZE_MASK,
870 DMA_DIR_FROM_CARD | DMA_EN | pack_size);
871 } else {
872 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL,
873 0x03 | DMA_PACK_SIZE_MASK,
874 DMA_DIR_TO_CARD | DMA_EN | pack_size);
875 }
876
877 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
878}
879
880int enable_card_clock(struct rtsx_chip *chip, u8 card)
881{
882 int retval;
883 u8 clk_en = 0;
884
885 if (card & XD_CARD)
886 clk_en |= XD_CLK_EN;
887 if (card & SD_CARD)
888 clk_en |= SD_CLK_EN;
889 if (card & MS_CARD)
890 clk_en |= MS_CLK_EN;
891
892 retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, clk_en);
893 if (retval) {
894 rtsx_trace(chip);
895 return retval;
896 }
897
898 return STATUS_SUCCESS;
899}
900
901int disable_card_clock(struct rtsx_chip *chip, u8 card)
902{
903 int retval;
904 u8 clk_en = 0;
905
906 if (card & XD_CARD)
907 clk_en |= XD_CLK_EN;
908 if (card & SD_CARD)
909 clk_en |= SD_CLK_EN;
910 if (card & MS_CARD)
911 clk_en |= MS_CLK_EN;
912
913 retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, 0);
914 if (retval) {
915 rtsx_trace(chip);
916 return retval;
917 }
918
919 return STATUS_SUCCESS;
920}
921
922int card_power_on(struct rtsx_chip *chip, u8 card)
923{
924 int retval;
925 u8 mask, val1, val2;
926
927 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
928 mask = MS_POWER_MASK;
929 val1 = MS_PARTIAL_POWER_ON;
930 val2 = MS_POWER_ON;
931 } else {
932 mask = SD_POWER_MASK;
933 val1 = SD_PARTIAL_POWER_ON;
934 val2 = SD_POWER_ON;
935 }
936
937 rtsx_init_cmd(chip);
938 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1);
939
940 retval = rtsx_send_cmd(chip, 0, 100);
941 if (retval != STATUS_SUCCESS) {
942 rtsx_trace(chip);
943 return STATUS_FAIL;
944 }
945
946 udelay(chip->pmos_pwr_on_interval);
947
948 rtsx_init_cmd(chip);
949 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2);
950
951 retval = rtsx_send_cmd(chip, 0, 100);
952 if (retval != STATUS_SUCCESS) {
953 rtsx_trace(chip);
954 return STATUS_FAIL;
955 }
956
957 return STATUS_SUCCESS;
958}
959
960int card_power_off(struct rtsx_chip *chip, u8 card)
961{
962 int retval;
963 u8 mask, val;
964
965 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
966 mask = MS_POWER_MASK;
967 val = MS_POWER_OFF;
968 } else {
969 mask = SD_POWER_MASK;
970 val = SD_POWER_OFF;
971 }
972
973 retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val);
974 if (retval) {
975 rtsx_trace(chip);
976 return retval;
977 }
978
979 return STATUS_SUCCESS;
980}
981
982int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
983 u32 sec_addr, u16 sec_cnt)
984{
985 int retval;
986 unsigned int lun = SCSI_LUN(srb);
987 int i;
988
989 if (!chip->rw_card[lun]) {
990 rtsx_trace(chip);
991 return STATUS_FAIL;
992 }
993
994 for (i = 0; i < 3; i++) {
995 chip->rw_need_retry = 0;
996
997 retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt);
998 if (retval != STATUS_SUCCESS) {
999 if (rtsx_check_chip_exist(chip) != STATUS_SUCCESS) {
1000 rtsx_release_chip(chip);
1001 rtsx_trace(chip);
1002 return STATUS_FAIL;
1003 }
1004 if (detect_card_cd(chip, chip->cur_card) !=
1005 STATUS_SUCCESS) {
1006 rtsx_trace(chip);
1007 return STATUS_FAIL;
1008 }
1009
1010 if (!chip->rw_need_retry) {
1011 dev_dbg(rtsx_dev(chip), "RW fail, but no need to retry\n");
1012 break;
1013 }
1014 } else {
1015 chip->rw_need_retry = 0;
1016 break;
1017 }
1018
1019 dev_dbg(rtsx_dev(chip), "Retry RW, (i = %d)\n", i);
1020 }
1021
1022 return retval;
1023}
1024
1025int card_share_mode(struct rtsx_chip *chip, int card)
1026{
1027 int retval;
1028 u8 mask, value;
1029
1030 if (CHECK_PID(chip, 0x5208)) {
1031 mask = CARD_SHARE_MASK;
1032 if (card == SD_CARD) {
1033 value = CARD_SHARE_48_SD;
1034 } else if (card == MS_CARD) {
1035 value = CARD_SHARE_48_MS;
1036 } else if (card == XD_CARD) {
1037 value = CARD_SHARE_48_XD;
1038 } else {
1039 rtsx_trace(chip);
1040 return STATUS_FAIL;
1041 }
1042
1043 } else if (CHECK_PID(chip, 0x5288)) {
1044 mask = 0x03;
1045 if (card == SD_CARD) {
1046 value = CARD_SHARE_BAROSSA_SD;
1047 } else if (card == MS_CARD) {
1048 value = CARD_SHARE_BAROSSA_MS;
1049 } else if (card == XD_CARD) {
1050 value = CARD_SHARE_BAROSSA_XD;
1051 } else {
1052 rtsx_trace(chip);
1053 return STATUS_FAIL;
1054 }
1055
1056 } else {
1057 rtsx_trace(chip);
1058 return STATUS_FAIL;
1059 }
1060
1061 retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value);
1062 if (retval) {
1063 rtsx_trace(chip);
1064 return retval;
1065 }
1066
1067 return STATUS_SUCCESS;
1068}
1069
1070int select_card(struct rtsx_chip *chip, int card)
1071{
1072 int retval;
1073
1074 if (chip->cur_card != card) {
1075 u8 mod;
1076
1077 if (card == SD_CARD) {
1078 mod = SD_MOD_SEL;
1079 } else if (card == MS_CARD) {
1080 mod = MS_MOD_SEL;
1081 } else if (card == XD_CARD) {
1082 mod = XD_MOD_SEL;
1083 } else if (card == SPI_CARD) {
1084 mod = SPI_MOD_SEL;
1085 } else {
1086 rtsx_trace(chip);
1087 return STATUS_FAIL;
1088 }
1089
1090 retval = rtsx_write_register(chip, CARD_SELECT, 0x07, mod);
1091 if (retval) {
1092 rtsx_trace(chip);
1093 return retval;
1094 }
1095 chip->cur_card = card;
1096
1097 retval = card_share_mode(chip, card);
1098 if (retval != STATUS_SUCCESS) {
1099 rtsx_trace(chip);
1100 return STATUS_FAIL;
1101 }
1102 }
1103
1104 return STATUS_SUCCESS;
1105}
1106
1107void toggle_gpio(struct rtsx_chip *chip, u8 gpio)
1108{
1109 u8 temp_reg;
1110
1111 rtsx_read_register(chip, CARD_GPIO, &temp_reg);
1112 temp_reg ^= (0x01 << gpio);
1113 rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg);
1114}
1115
1116void turn_on_led(struct rtsx_chip *chip, u8 gpio)
1117{
1118 if (CHECK_PID(chip, 0x5288))
1119 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio),
1120 (u8)(1 << gpio));
1121 else
1122 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1123}
1124
1125void turn_off_led(struct rtsx_chip *chip, u8 gpio)
1126{
1127 if (CHECK_PID(chip, 0x5288))
1128 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1129 else
1130 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio),
1131 (u8)(1 << gpio));
1132}
1133
1134int detect_card_cd(struct rtsx_chip *chip, int card)
1135{
1136 u32 card_cd, status;
1137
1138 if (card == SD_CARD) {
1139 card_cd = SD_EXIST;
1140 } else if (card == MS_CARD) {
1141 card_cd = MS_EXIST;
1142 } else if (card == XD_CARD) {
1143 card_cd = XD_EXIST;
1144 } else {
1145 dev_dbg(rtsx_dev(chip), "Wrong card type: 0x%x\n", card);
1146 rtsx_trace(chip);
1147 return STATUS_FAIL;
1148 }
1149
1150 status = rtsx_readl(chip, RTSX_BIPR);
1151 if (!(status & card_cd)) {
1152 rtsx_trace(chip);
1153 return STATUS_FAIL;
1154 }
1155
1156 return STATUS_SUCCESS;
1157}
1158
1159int check_card_exist(struct rtsx_chip *chip, unsigned int lun)
1160{
1161 if (chip->card_exist & chip->lun2card[lun])
1162 return 1;
1163
1164 return 0;
1165}
1166
1167int check_card_ready(struct rtsx_chip *chip, unsigned int lun)
1168{
1169 if (chip->card_ready & chip->lun2card[lun])
1170 return 1;
1171
1172 return 0;
1173}
1174
1175int check_card_wp(struct rtsx_chip *chip, unsigned int lun)
1176{
1177 if (chip->card_wp & chip->lun2card[lun])
1178 return 1;
1179
1180 return 0;
1181}
1182
1183u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun)
1184{
1185 if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
1186 return (u8)XD_CARD;
1187 else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
1188 return (u8)SD_CARD;
1189 else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
1190 return (u8)MS_CARD;
1191
1192 return 0;
1193}
1194
1195void eject_card(struct rtsx_chip *chip, unsigned int lun)
1196{
1197 do_remaining_work(chip);
1198
1199 if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
1200 release_sd_card(chip);
1201 chip->card_ejected |= SD_CARD;
1202 chip->card_ready &= ~SD_CARD;
1203 chip->capacity[lun] = 0;
1204 } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
1205 release_xd_card(chip);
1206 chip->card_ejected |= XD_CARD;
1207 chip->card_ready &= ~XD_CARD;
1208 chip->capacity[lun] = 0;
1209 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
1210 release_ms_card(chip);
1211 chip->card_ejected |= MS_CARD;
1212 chip->card_ready &= ~MS_CARD;
1213 chip->capacity[lun] = 0;
1214 }
1215}
1216
