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13#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14#define __DRIVERS_USB_CHIPIDEA_CI_H
15
16#include <linux/list.h>
17#include <linux/irqreturn.h>
18#include <linux/usb.h>
19#include <linux/usb/gadget.h>
20#include <linux/usb/otg-fsm.h>
21#include <linux/usb/otg.h>
22#include <linux/ulpi/interface.h>
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26
27#define TD_PAGE_COUNT 5
28#define CI_HDRC_PAGE_SIZE 4096ul
29#define ENDPT_MAX 32
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34
35#define ID_ID 0x0
36#define ID_HWGENERAL 0x4
37#define ID_HWHOST 0x8
38#define ID_HWDEVICE 0xc
39#define ID_HWTXBUF 0x10
40#define ID_HWRXBUF 0x14
41#define ID_SBUSCFG 0x90
42
43
44enum ci_hw_regs {
45 CAP_CAPLENGTH,
46 CAP_HCCPARAMS,
47 CAP_DCCPARAMS,
48 CAP_TESTMODE,
49 CAP_LAST = CAP_TESTMODE,
50 OP_USBCMD,
51 OP_USBSTS,
52 OP_USBINTR,
53 OP_DEVICEADDR,
54 OP_ENDPTLISTADDR,
55 OP_TTCTRL,
56 OP_BURSTSIZE,
57 OP_ULPI_VIEWPORT,
58 OP_PORTSC,
59 OP_DEVLC,
60 OP_OTGSC,
61 OP_USBMODE,
62 OP_ENDPTSETUPSTAT,
63 OP_ENDPTPRIME,
64 OP_ENDPTFLUSH,
65 OP_ENDPTSTAT,
66 OP_ENDPTCOMPLETE,
67 OP_ENDPTCTRL,
68
69 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
70};
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88struct ci_hw_ep {
89 struct usb_ep ep;
90 u8 dir;
91 u8 num;
92 u8 type;
93 char name[16];
94 struct {
95 struct list_head queue;
96 struct ci_hw_qh *ptr;
97 dma_addr_t dma;
98 } qh;
99 int wedge;
100
101
102 struct ci_hdrc *ci;
103 spinlock_t *lock;
104 struct dma_pool *td_pool;
105 struct td_node *pending_td;
106};
107
108enum ci_role {
109 CI_ROLE_HOST = 0,
110 CI_ROLE_GADGET,
111 CI_ROLE_END,
112};
113
114enum ci_revision {
115 CI_REVISION_1X = 10,
116 CI_REVISION_20 = 20,
117 CI_REVISION_21,
118 CI_REVISION_22,
119 CI_REVISION_23,
120 CI_REVISION_24,
121 CI_REVISION_25,
122 CI_REVISION_25_PLUS,
123 CI_REVISION_UNKNOWN = 99,
124};
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132
133struct ci_role_driver {
134 int (*start)(struct ci_hdrc *);
135 void (*stop)(struct ci_hdrc *);
136 irqreturn_t (*irq)(struct ci_hdrc *);
137 const char *name;
138};
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150struct hw_bank {
151 unsigned lpm;
152 resource_size_t phys;
153 void __iomem *abs;
154 void __iomem *cap;
155 void __iomem *op;
156 size_t size;
157 void __iomem *regmap[OP_LAST + 1];
158};
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208struct ci_hdrc {
209 struct device *dev;
210 spinlock_t lock;
211 struct hw_bank hw_bank;
212 int irq;
213 struct ci_role_driver *roles[CI_ROLE_END];
214 enum ci_role role;
215 bool is_otg;
216 struct usb_otg otg;
217 struct otg_fsm fsm;
218 struct hrtimer otg_fsm_hrtimer;
219 ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS];
220 unsigned enabled_otg_timer_bits;
221 enum otg_fsm_timer next_otg_timer;
222 struct work_struct work;
223 struct workqueue_struct *wq;
224
225 struct dma_pool *qh_pool;
226 struct dma_pool *td_pool;
227
228 struct usb_gadget gadget;
229 struct usb_gadget_driver *driver;
230 unsigned hw_ep_max;
231 struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
232 u32 ep0_dir;
233 struct ci_hw_ep *ep0out, *ep0in;
234
235 struct usb_request *status;
236 bool setaddr;
237 u8 address;
238 u8 remote_wakeup;
239 u8 suspended;
240 u8 test_mode;
241
242 struct ci_hdrc_platform_data *platdata;
243 int vbus_active;
244#ifdef CONFIG_USB_CHIPIDEA_ULPI
245 struct ulpi *ulpi;
246 struct ulpi_ops ulpi_ops;
247#endif
248 struct phy *phy;
249
250 struct usb_phy *usb_phy;
251 struct usb_hcd *hcd;
252 struct dentry *debugfs;
253 bool id_event;
254 bool b_sess_valid_event;
255 bool imx28_write_fix;
256 bool supports_runtime_pm;
257 bool in_lpm;
258 bool wakeup_int;
259 enum ci_revision rev;
260};
261
262static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
263{
264 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
265 return ci->roles[ci->role];
266}
267
268static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
269{
270 int ret;
271
272 if (role >= CI_ROLE_END)
273 return -EINVAL;
274
275 if (!ci->roles[role])
276 return -ENXIO;
277
278 ret = ci->roles[role]->start(ci);
279 if (!ret)
280 ci->role = role;
281 return ret;
282}
283
284static inline void ci_role_stop(struct ci_hdrc *ci)
285{
286 enum ci_role role = ci->role;
287
288 if (role == CI_ROLE_END)
289 return;
290
291 ci->role = CI_ROLE_END;
292
293 ci->roles[role]->stop(ci);
294}
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304static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
305{
306 return ioread32(ci->hw_bank.abs + offset) & mask;
307}
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316static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
317 u32 mask, u32 data)
318{
319 if (~mask)
320 data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
321 | (data & mask);
322
323 iowrite32(data, ci->hw_bank.abs + offset);
324}
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334static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
335{
336 return ioread32(ci->hw_bank.regmap[reg]) & mask;
337}
338
339#ifdef CONFIG_SOC_IMX28
340static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
341{
342 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
343}
344#else
345static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
346{
347}
348#endif
349
350static inline void __hw_write(struct ci_hdrc *ci, u32 val,
351 void __iomem *addr)
352{
353 if (ci->imx28_write_fix)
354 imx28_ci_writel(val, addr);
355 else
356 iowrite32(val, addr);
357}
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366static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
367 u32 mask, u32 data)
368{
369 if (~mask)
370 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
371 | (data & mask);
372
373 __hw_write(ci, data, ci->hw_bank.regmap[reg]);
374}
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384static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
385 u32 mask)
386{
387 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
388
389 __hw_write(ci, val, ci->hw_bank.regmap[reg]);
390 return val;
391}
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402static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
403 u32 mask, u32 data)
404{
405 u32 val = hw_read(ci, reg, ~0);
406
407 hw_write(ci, reg, mask, data);
408 return (val & mask) >> __ffs(mask);
409}
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417static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
418{
419#ifdef CONFIG_USB_OTG_FSM
420 struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
421
422 return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
423 ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
424 otg_caps->hnp_support || otg_caps->adp_support);
425#else
426 return false;
427#endif
428}
429
430#if IS_ENABLED(CONFIG_USB_CHIPIDEA_ULPI)
431int ci_ulpi_init(struct ci_hdrc *ci);
432void ci_ulpi_exit(struct ci_hdrc *ci);
433int ci_ulpi_resume(struct ci_hdrc *ci);
434#else
435static inline int ci_ulpi_init(struct ci_hdrc *ci) { return 0; }
436static inline void ci_ulpi_exit(struct ci_hdrc *ci) { }
437static inline int ci_ulpi_resume(struct ci_hdrc *ci) { return 0; }
438#endif
439
440u32 hw_read_intr_enable(struct ci_hdrc *ci);
441
442u32 hw_read_intr_status(struct ci_hdrc *ci);
443
444int hw_device_reset(struct ci_hdrc *ci);
445
446int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
447
448u8 hw_port_test_get(struct ci_hdrc *ci);
449
450void hw_phymode_configure(struct ci_hdrc *ci);
451
452void ci_platform_configure(struct ci_hdrc *ci);
453
454int dbg_create_files(struct ci_hdrc *ci);
455
456void dbg_remove_files(struct ci_hdrc *ci);
457#endif
458