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67#include <linux/scatterlist.h>
68#include <linux/slab.h>
69#include <linux/dma-mapping.h>
70#include "xhci.h"
71#include "xhci-trace.h"
72#include "xhci-mtk.h"
73
74
75
76
77
78dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 union xhci_trb *trb)
80{
81 unsigned long segment_offset;
82
83 if (!seg || !trb || trb < seg->trbs)
84 return 0;
85
86 segment_offset = trb - seg->trbs;
87 if (segment_offset >= TRBS_PER_SEGMENT)
88 return 0;
89 return seg->dma + (segment_offset * sizeof(*trb));
90}
91
92static bool trb_is_noop(union xhci_trb *trb)
93{
94 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
95}
96
97static bool trb_is_link(union xhci_trb *trb)
98{
99 return TRB_TYPE_LINK_LE32(trb->link.control);
100}
101
102static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
103{
104 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
105}
106
107static bool last_trb_on_ring(struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
109{
110 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
111}
112
113static bool link_trb_toggles_cycle(union xhci_trb *trb)
114{
115 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
116}
117
118static bool last_td_in_urb(struct xhci_td *td)
119{
120 struct urb_priv *urb_priv = td->urb->hcpriv;
121
122 return urb_priv->num_tds_done == urb_priv->num_tds;
123}
124
125static void inc_td_cnt(struct urb *urb)
126{
127 struct urb_priv *urb_priv = urb->hcpriv;
128
129 urb_priv->num_tds_done++;
130}
131
132static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
133{
134 if (trb_is_link(trb)) {
135
136 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
137 } else {
138 trb->generic.field[0] = 0;
139 trb->generic.field[1] = 0;
140 trb->generic.field[2] = 0;
141
142 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
143 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
144 }
145}
146
147
148
149
150
151static void next_trb(struct xhci_hcd *xhci,
152 struct xhci_ring *ring,
153 struct xhci_segment **seg,
154 union xhci_trb **trb)
155{
156 if (trb_is_link(*trb)) {
157 *seg = (*seg)->next;
158 *trb = ((*seg)->trbs);
159 } else {
160 (*trb)++;
161 }
162}
163
164
165
166
167
168static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
169{
170 ring->deq_updates++;
171
172
173 if (ring->type == TYPE_EVENT) {
174 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
175 ring->dequeue++;
176 return;
177 }
178 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
179 ring->cycle_state ^= 1;
180 ring->deq_seg = ring->deq_seg->next;
181 ring->dequeue = ring->deq_seg->trbs;
182 return;
183 }
184
185
186 if (!trb_is_link(ring->dequeue)) {
187 ring->dequeue++;
188 ring->num_trbs_free++;
189 }
190 while (trb_is_link(ring->dequeue)) {
191 ring->deq_seg = ring->deq_seg->next;
192 ring->dequeue = ring->deq_seg->trbs;
193 }
194 return;
195}
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
215 bool more_trbs_coming)
216{
217 u32 chain;
218 union xhci_trb *next;
219
220 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
221
222 if (!trb_is_link(ring->enqueue))
223 ring->num_trbs_free--;
224 next = ++(ring->enqueue);
225
226 ring->enq_updates++;
227
228 while (trb_is_link(next)) {
229
230
231
232
233
234
235
236
237 if (!chain && !more_trbs_coming)
238 break;
239
240
241
242
243
244 if (!(ring->type == TYPE_ISOC &&
245 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
246 !xhci_link_trb_quirk(xhci)) {
247 next->link.control &= cpu_to_le32(~TRB_CHAIN);
248 next->link.control |= cpu_to_le32(chain);
249 }
250
251 wmb();
252 next->link.control ^= cpu_to_le32(TRB_CYCLE);
253
254
255 if (link_trb_toggles_cycle(next))
256 ring->cycle_state ^= 1;
257
258 ring->enq_seg = ring->enq_seg->next;
259 ring->enqueue = ring->enq_seg->trbs;
260 next = ring->enqueue;
261 }
262}
263
264
265
266
267
268static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
269 unsigned int num_trbs)
270{
271 int num_trbs_in_deq_seg;
272
273 if (ring->num_trbs_free < num_trbs)
274 return 0;
275
276 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
277 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
278 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
279 return 0;
280 }
281
282 return 1;
283}
284
285
286void xhci_ring_cmd_db(struct xhci_hcd *xhci)
287{
288 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
289 return;
290
291 xhci_dbg(xhci, "// Ding dong!\n");
292 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
293
294 readl(&xhci->dba->doorbell[0]);
295}
296
297static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
298{
299 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
300}
301
302static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
303{
304 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
305 cmd_list);
306}
307
308
309
310
311
312
313static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
314 struct xhci_command *cur_cmd)
315{
316 struct xhci_command *i_cmd;
317
318
319 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
320
321 if (i_cmd->status != COMP_COMMAND_ABORTED)
322 continue;
323
324 i_cmd->status = COMP_STOPPED;
325
326 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
327 i_cmd->command_trb);
328
329 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
330
331
332
333
334
335 }
336
337 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
338
339
340 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
341 !(xhci->xhc_state & XHCI_STATE_DYING)) {
342 xhci->current_cmd = cur_cmd;
343 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
344 xhci_ring_cmd_db(xhci);
345 }
346}
347
348
349static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
350{
351 u64 temp_64;
352 int ret;
353
354 xhci_dbg(xhci, "Abort command ring\n");
355
356 reinit_completion(&xhci->cmd_ring_stop_completion);
357
358 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
359 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
360 &xhci->op_regs->cmd_ring);
361
362
363
364
365
366
367
368
369 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
370 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
371 if (ret < 0) {
372 xhci_err(xhci,
373 "Stop command ring failed, maybe the host is dead\n");
374 xhci->xhc_state |= XHCI_STATE_DYING;
375 xhci_halt(xhci);
376 return -ESHUTDOWN;
377 }
378
379
380
381
382
383
384 spin_unlock_irqrestore(&xhci->lock, flags);
385 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
386 msecs_to_jiffies(2000));
387 spin_lock_irqsave(&xhci->lock, flags);
388 if (!ret) {
389 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
390 xhci_cleanup_command_queue(xhci);
391 } else {
392 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
393 }
394 return 0;
395}
396
397void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
398 unsigned int slot_id,
399 unsigned int ep_index,
400 unsigned int stream_id)
401{
402 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
403 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
404 unsigned int ep_state = ep->ep_state;
405
406
407
408
409
410
411
412 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
413 (ep_state & EP_HALTED))
414 return;
415 writel(DB_VALUE(ep_index, stream_id), db_addr);
416
417
418
419}
420
421
422static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
423 unsigned int slot_id,
424 unsigned int ep_index)
425{
426 unsigned int stream_id;
427 struct xhci_virt_ep *ep;
428
429 ep = &xhci->devs[slot_id]->eps[ep_index];
430
431
432 if (!(ep->ep_state & EP_HAS_STREAMS)) {
433 if (ep->ring && !(list_empty(&ep->ring->td_list)))
434 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
435 return;
436 }
437
438 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
439 stream_id++) {
440 struct xhci_stream_info *stream_info = ep->stream_info;
441 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
442 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
443 stream_id);
444 }
445}
446
447
448
449
450
451struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
452 unsigned int slot_id, unsigned int ep_index,
453 unsigned int stream_id)
454{
455 struct xhci_virt_ep *ep;
456
457 ep = &xhci->devs[slot_id]->eps[ep_index];
458
459 if (!(ep->ep_state & EP_HAS_STREAMS))
460 return ep->ring;
461
462 if (stream_id == 0) {
463 xhci_warn(xhci,
464 "WARN: Slot ID %u, ep index %u has streams, "
465 "but URB has no stream ID.\n",
466 slot_id, ep_index);
467 return NULL;
468 }
469
470 if (stream_id < ep->stream_info->num_streams)
471 return ep->stream_info->stream_rings[stream_id];
472
473 xhci_warn(xhci,
474 "WARN: Slot ID %u, ep index %u has "
475 "stream IDs 1 to %u allocated, "
476 "but stream ID %u is requested.\n",
477 slot_id, ep_index,
478 ep->stream_info->num_streams - 1,
479 stream_id);
480 return NULL;
481}
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
502 unsigned int slot_id, unsigned int ep_index,
503 unsigned int stream_id, struct xhci_td *cur_td,
504 struct xhci_dequeue_state *state)
505{
506 struct xhci_virt_device *dev = xhci->devs[slot_id];
507 struct xhci_virt_ep *ep = &dev->eps[ep_index];
508 struct xhci_ring *ep_ring;
509 struct xhci_segment *new_seg;
510 union xhci_trb *new_deq;
511 dma_addr_t addr;
512 u64 hw_dequeue;
513 bool cycle_found = false;
514 bool td_last_trb_found = false;
515
516 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
517 ep_index, stream_id);
518 if (!ep_ring) {
519 xhci_warn(xhci, "WARN can't find new dequeue state "
520 "for invalid stream ID %u.\n",
521 stream_id);
522 return;
523 }
524
525
526 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
527 "Finding endpoint context");
528
529 if (ep->ep_state & EP_HAS_STREAMS) {
530 struct xhci_stream_ctx *ctx =
531 &ep->stream_info->stream_ctx_array[stream_id];
532 hw_dequeue = le64_to_cpu(ctx->stream_ring);
533 } else {
534 struct xhci_ep_ctx *ep_ctx
535 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
536 hw_dequeue = le64_to_cpu(ep_ctx->deq);
537 }
538
539 new_seg = ep_ring->deq_seg;
540 new_deq = ep_ring->dequeue;
541 state->new_cycle_state = hw_dequeue & 0x1;
542
543
544
545
546
547
548
549 do {
550 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
551 == (dma_addr_t)(hw_dequeue & ~0xf)) {
552 cycle_found = true;
553 if (td_last_trb_found)
554 break;
555 }
556 if (new_deq == cur_td->last_trb)
557 td_last_trb_found = true;
558
559 if (cycle_found && trb_is_link(new_deq) &&
560 link_trb_toggles_cycle(new_deq))
561 state->new_cycle_state ^= 0x1;
562
563 next_trb(xhci, ep_ring, &new_seg, &new_deq);
564
565
566 if (new_deq == ep->ring->dequeue) {
567 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
568 state->new_deq_seg = NULL;
569 state->new_deq_ptr = NULL;
570 return;
571 }
572
573 } while (!cycle_found || !td_last_trb_found);
574
575 state->new_deq_seg = new_seg;
576 state->new_deq_ptr = new_deq;
577
578
579 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
580 "Cycle state = 0x%x", state->new_cycle_state);
581
582 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
583 "New dequeue segment = %p (virtual)",
584 state->new_deq_seg);
585 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
586 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
587 "New dequeue pointer = 0x%llx (DMA)",
588 (unsigned long long) addr);
589}
590
591
592
593
594
595static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
596 struct xhci_td *td, bool flip_cycle)
597{
598 struct xhci_segment *seg = td->start_seg;
599 union xhci_trb *trb = td->first_trb;
600
601 while (1) {
602 trb_to_noop(trb, TRB_TR_NOOP);
603
604
605 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
606 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
607
608 if (trb == td->last_trb)
609 break;
610
611 next_trb(xhci, ep_ring, &seg, &trb);
612 }
613}
614
615static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
616 struct xhci_virt_ep *ep)
617{
618 ep->ep_state &= ~EP_STOP_CMD_PENDING;
619
620 del_timer(&ep->stop_cmd_timer);
621}
622
623
624
625
626
627static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
628 struct xhci_td *cur_td, int status)
629{
630 struct urb *urb = cur_td->urb;
631 struct urb_priv *urb_priv = urb->hcpriv;
632 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
633
634 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
635 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
636 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
637 if (xhci->quirks & XHCI_AMD_PLL_FIX)
638 usb_amd_quirk_pll_enable();
639 }
640 }
641 xhci_urb_free_priv(urb_priv);
642 usb_hcd_unlink_urb_from_ep(hcd, urb);
643 spin_unlock(&xhci->lock);
644 usb_hcd_giveback_urb(hcd, urb, status);
645 trace_xhci_urb_giveback(urb);
646 spin_lock(&xhci->lock);
647}
648
649static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
650 struct xhci_ring *ring, struct xhci_td *td)
651{
652 struct device *dev = xhci_to_hcd(xhci)->self.controller;
653 struct xhci_segment *seg = td->bounce_seg;
654 struct urb *urb = td->urb;
655
656 if (!ring || !seg || !urb)
657 return;
658
659 if (usb_urb_dir_out(urb)) {
660 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
661 DMA_TO_DEVICE);
662 return;
663 }
664
665
666 sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf,
667 seg->bounce_len, seg->bounce_offs);
668 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
669 DMA_FROM_DEVICE);
670 seg->bounce_len = 0;
671 seg->bounce_offs = 0;
672}
673
674
675
676
677
678
679
680
681
682
683
684static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
685 union xhci_trb *trb, struct xhci_event_cmd *event)
686{
687 unsigned int ep_index;
688 struct xhci_ring *ep_ring;
689 struct xhci_virt_ep *ep;
690 struct xhci_td *cur_td = NULL;
691 struct xhci_td *last_unlinked_td;
692
693 struct xhci_dequeue_state deq_state;
694
695 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
696 if (!xhci->devs[slot_id])
697 xhci_warn(xhci, "Stop endpoint command "
698 "completion for disabled slot %u\n",
699 slot_id);
700 return;
701 }
702
703 memset(&deq_state, 0, sizeof(deq_state));
704 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
705 ep = &xhci->devs[slot_id]->eps[ep_index];
706 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
707 struct xhci_td, cancelled_td_list);
708
709 if (list_empty(&ep->cancelled_td_list)) {
710 xhci_stop_watchdog_timer_in_irq(xhci, ep);
711 ep->stopped_td = NULL;
712 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
713 return;
714 }
715
716
717
718
719
720
721 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
722 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
723 "Removing canceled TD starting at 0x%llx (dma).",
724 (unsigned long long)xhci_trb_virt_to_dma(
725 cur_td->start_seg, cur_td->first_trb));
726 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
727 if (!ep_ring) {
728
729
730
731
732
733
734
735
736
737
738
739 xhci_warn(xhci, "WARN Cancelled URB %p "
740 "has invalid stream ID %u.\n",
741 cur_td->urb,
742 cur_td->urb->stream_id);
743 goto remove_finished_td;
744 }
745
746
747
748
749 if (cur_td == ep->stopped_td)
750 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
751 cur_td->urb->stream_id,
752 cur_td, &deq_state);
753 else
754 td_to_noop(xhci, ep_ring, cur_td, false);
755remove_finished_td:
756
757
758
759
760
761 list_del_init(&cur_td->td_list);
762 }
763
764 xhci_stop_watchdog_timer_in_irq(xhci, ep);
765
766
767 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
768 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
769 ep->stopped_td->urb->stream_id, &deq_state);
770 xhci_ring_cmd_db(xhci);
771 } else {
772
773 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
774 }
775
776 ep->stopped_td = NULL;
777
778
779
780
781
782
783
784 do {
785 cur_td = list_first_entry(&ep->cancelled_td_list,
786 struct xhci_td, cancelled_td_list);
787 list_del_init(&cur_td->cancelled_td_list);
788
789
790
791
792
793 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
794 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
795 inc_td_cnt(cur_td->urb);
796 if (last_td_in_urb(cur_td))
797 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
798
799
800
801
802 if (xhci->xhc_state & XHCI_STATE_DYING)
803 return;
804 } while (cur_td != last_unlinked_td);
805
806
807}
808
809static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
810{
811 struct xhci_td *cur_td;
812 struct xhci_td *tmp;
813
814 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
815 list_del_init(&cur_td->td_list);
816
817 if (!list_empty(&cur_td->cancelled_td_list))
818 list_del_init(&cur_td->cancelled_td_list);
819
820 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
821
822 inc_td_cnt(cur_td->urb);
823 if (last_td_in_urb(cur_td))
824 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
825 }
826}
827
828static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
829 int slot_id, int ep_index)
830{
831 struct xhci_td *cur_td;
832 struct xhci_td *tmp;
833 struct xhci_virt_ep *ep;
834 struct xhci_ring *ring;
835
836 ep = &xhci->devs[slot_id]->eps[ep_index];
837 if ((ep->ep_state & EP_HAS_STREAMS) ||
838 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
839 int stream_id;
840
841 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
842 stream_id++) {
843 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
844 "Killing URBs for slot ID %u, ep index %u, stream %u",
845 slot_id, ep_index, stream_id + 1);
846 xhci_kill_ring_urbs(xhci,
847 ep->stream_info->stream_rings[stream_id]);
848 }
849 } else {
850 ring = ep->ring;
851 if (!ring)
852 return;
853 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
854 "Killing URBs for slot ID %u, ep index %u",
855 slot_id, ep_index);
856 xhci_kill_ring_urbs(xhci, ring);
857 }
858
859 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
860 cancelled_td_list) {
861 list_del_init(&cur_td->cancelled_td_list);
862 inc_td_cnt(cur_td->urb);
863
864 if (last_td_in_urb(cur_td))
865 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
866 }
867}
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886void xhci_stop_endpoint_command_watchdog(unsigned long arg)
887{
888 struct xhci_hcd *xhci;
889 struct xhci_virt_ep *ep;
890 int ret, i, j;
891 unsigned long flags;
892
893 ep = (struct xhci_virt_ep *) arg;
894 xhci = ep->xhci;
895
896 spin_lock_irqsave(&xhci->lock, flags);
897
898
899 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
900 timer_pending(&ep->stop_cmd_timer)) {
901 spin_unlock_irqrestore(&xhci->lock, flags);
902 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
903 return;
904 }
905
906 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
907 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
908
909
910
911
912 xhci->xhc_state |= XHCI_STATE_DYING;
913 ep->ep_state &= ~EP_STOP_CMD_PENDING;
914
915
916 xhci_quiesce(xhci);
917 spin_unlock_irqrestore(&xhci->lock, flags);
918
919 ret = xhci_halt(xhci);
920
921 spin_lock_irqsave(&xhci->lock, flags);
922 if (ret < 0) {
923
924
925
926
927
928
929
930 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
931 xhci_warn(xhci, "Completing active URBs anyway.\n");
932
933
934
935
936
937 }
938 for (i = 0; i < MAX_HC_SLOTS; i++) {
939 if (!xhci->devs[i])
940 continue;
941 for (j = 0; j < 31; j++)
942 xhci_kill_endpoint_urbs(xhci, i, j);
943 }
944 spin_unlock_irqrestore(&xhci->lock, flags);
945 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
946 "Calling usb_hc_died()");
947 usb_hc_died(xhci_to_hcd(xhci));
948 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
949 "xHCI host controller is dead.");
950}
951
952
953static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
954 struct xhci_virt_device *dev,
955 struct xhci_ring *ep_ring,
956 unsigned int ep_index)
957{
958 union xhci_trb *dequeue_temp;
959 int num_trbs_free_temp;
960 bool revert = false;
961
962 num_trbs_free_temp = ep_ring->num_trbs_free;
963 dequeue_temp = ep_ring->dequeue;
964
965
966
967
968
969
970
971 if (trb_is_link(ep_ring->dequeue)) {
972 ep_ring->deq_seg = ep_ring->deq_seg->next;
973 ep_ring->dequeue = ep_ring->deq_seg->trbs;
974 }
975
976 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
977
978 ep_ring->num_trbs_free++;
979 ep_ring->dequeue++;
980 if (trb_is_link(ep_ring->dequeue)) {
981 if (ep_ring->dequeue ==
982 dev->eps[ep_index].queued_deq_ptr)
983 break;
984 ep_ring->deq_seg = ep_ring->deq_seg->next;
985 ep_ring->dequeue = ep_ring->deq_seg->trbs;
986 }
987 if (ep_ring->dequeue == dequeue_temp) {
988 revert = true;
989 break;
990 }
991 }
992
993 if (revert) {
994 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
995 ep_ring->num_trbs_free = num_trbs_free_temp;
996 }
997}
998
999
1000
1001
1002
1003
1004
1005
1006static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1007 union xhci_trb *trb, u32 cmd_comp_code)
1008{
1009 unsigned int ep_index;
1010 unsigned int stream_id;
1011 struct xhci_ring *ep_ring;
1012 struct xhci_virt_device *dev;
1013 struct xhci_virt_ep *ep;
1014 struct xhci_ep_ctx *ep_ctx;
1015 struct xhci_slot_ctx *slot_ctx;
1016
1017 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1018 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1019 dev = xhci->devs[slot_id];
1020 ep = &dev->eps[ep_index];
1021
1022 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1023 if (!ep_ring) {
1024 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1025 stream_id);
1026
1027 goto cleanup;
1028 }
1029
1030 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1031 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1032
1033 if (cmd_comp_code != COMP_SUCCESS) {
1034 unsigned int ep_state;
1035 unsigned int slot_state;
1036
1037 switch (cmd_comp_code) {
1038 case COMP_TRB_ERROR:
1039 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1040 break;
1041 case COMP_CONTEXT_STATE_ERROR:
1042 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1043 ep_state = GET_EP_CTX_STATE(ep_ctx);
1044 slot_state = le32_to_cpu(slot_ctx->dev_state);
1045 slot_state = GET_SLOT_STATE(slot_state);
1046 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1047 "Slot state = %u, EP state = %u",
1048 slot_state, ep_state);
1049 break;
1050 case COMP_SLOT_NOT_ENABLED_ERROR:
1051 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1052 slot_id);
1053 break;
1054 default:
1055 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1056 cmd_comp_code);
1057 break;
1058 }
1059
1060
1061
1062
1063
1064
1065 } else {
1066 u64 deq;
1067
1068 if (ep->ep_state & EP_HAS_STREAMS) {
1069 struct xhci_stream_ctx *ctx =
1070 &ep->stream_info->stream_ctx_array[stream_id];
1071 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1072 } else {
1073 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1074 }
1075 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1076 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1077 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1078 ep->queued_deq_ptr) == deq) {
1079
1080
1081
1082 update_ring_for_set_deq_completion(xhci, dev,
1083 ep_ring, ep_index);
1084 } else {
1085 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1086 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1087 ep->queued_deq_seg, ep->queued_deq_ptr);
1088 }
1089 }
1090
1091cleanup:
1092 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1093 dev->eps[ep_index].queued_deq_seg = NULL;
1094 dev->eps[ep_index].queued_deq_ptr = NULL;
1095
1096 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1097}
1098
1099static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1100 union xhci_trb *trb, u32 cmd_comp_code)
1101{
1102 unsigned int ep_index;
1103
1104 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1105
1106
1107
1108 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1109 "Ignoring reset ep completion code of %u", cmd_comp_code);
1110
1111
1112
1113
1114
1115 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1116 struct xhci_command *command;
1117 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1118 if (!command) {
1119 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1120 return;
1121 }
1122 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1123 "Queueing configure endpoint command");
1124 xhci_queue_configure_endpoint(xhci, command,
1125 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1126 false);
1127 xhci_ring_cmd_db(xhci);
1128 } else {
1129
1130 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1131 }
1132}
1133
1134static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1135 struct xhci_command *command, u32 cmd_comp_code)
1136{
1137 if (cmd_comp_code == COMP_SUCCESS)
1138 command->slot_id = slot_id;
1139 else
1140 command->slot_id = 0;
1141}
1142
1143static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1144{
1145 struct xhci_virt_device *virt_dev;
1146
1147 virt_dev = xhci->devs[slot_id];
1148 if (!virt_dev)
1149 return;
1150 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1151
1152 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1153 xhci_free_virt_device(xhci, slot_id);
1154}
1155
1156static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1157 struct xhci_event_cmd *event, u32 cmd_comp_code)
1158{
1159 struct xhci_virt_device *virt_dev;
1160 struct xhci_input_control_ctx *ctrl_ctx;
1161 unsigned int ep_index;
1162 unsigned int ep_state;
1163 u32 add_flags, drop_flags;
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173 virt_dev = xhci->devs[slot_id];
1174 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1175 if (!ctrl_ctx) {
1176 xhci_warn(xhci, "Could not get input context, bad type.\n");
1177 return;
1178 }
1179
1180 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1181 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1182
1183 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1184
1185
1186
1187
1188
1189
1190
1191 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1192 ep_index != (unsigned int) -1 &&
1193 add_flags - SLOT_FLAG == drop_flags) {
1194 ep_state = virt_dev->eps[ep_index].ep_state;
1195 if (!(ep_state & EP_HALTED))
1196 return;
1197 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1198 "Completed config ep cmd - "
1199 "last ep index = %d, state = %d",
1200 ep_index, ep_state);
1201
1202 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1203 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1204 return;
1205 }
1206 return;
1207}
1208
1209static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1210 struct xhci_event_cmd *event)
1211{
1212 xhci_dbg(xhci, "Completed reset device command.\n");
1213 if (!xhci->devs[slot_id])
1214 xhci_warn(xhci, "Reset device command completion "
1215 "for disabled slot %u\n", slot_id);
1216}
1217
1218static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1219 struct xhci_event_cmd *event)
1220{
1221 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1222 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1223 return;
1224 }
1225 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1226 "NEC firmware version %2x.%02x",
1227 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1228 NEC_FW_MINOR(le32_to_cpu(event->status)));
1229}
1230
1231static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1232{
1233 list_del(&cmd->cmd_list);
1234
1235 if (cmd->completion) {
1236 cmd->status = status;
1237 complete(cmd->completion);
1238 } else {
1239 kfree(cmd);
1240 }
1241}
1242
1243void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1244{
1245 struct xhci_command *cur_cmd, *tmp_cmd;
1246 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1247 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1248}
1249
1250void xhci_handle_command_timeout(struct work_struct *work)
1251{
1252 struct xhci_hcd *xhci;
1253 int ret;
1254 unsigned long flags;
1255 u64 hw_ring_state;
1256
1257 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1258
1259 spin_lock_irqsave(&xhci->lock, flags);
1260
1261
1262
1263
1264
1265 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1266 spin_unlock_irqrestore(&xhci->lock, flags);
1267 return;
1268 }
1269
1270 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1271
1272
1273 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1274 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1275 (hw_ring_state & CMD_RING_RUNNING)) {
1276
1277 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1278 xhci_dbg(xhci, "Command timeout\n");
1279 ret = xhci_abort_cmd_ring(xhci, flags);
1280 if (unlikely(ret == -ESHUTDOWN)) {
1281 xhci_err(xhci, "Abort command ring failed\n");
1282 xhci_cleanup_command_queue(xhci);
1283 spin_unlock_irqrestore(&xhci->lock, flags);
1284 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1285 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1286
1287 return;
1288 }
1289
1290 goto time_out_completed;
1291 }
1292
1293
1294 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1295 xhci_dbg(xhci, "host removed, ring start fail?\n");
1296 xhci_cleanup_command_queue(xhci);
1297
1298 goto time_out_completed;
1299 }
1300
1301
1302 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1303 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1304
1305time_out_completed:
1306 spin_unlock_irqrestore(&xhci->lock, flags);
1307 return;
1308}
1309
1310static void handle_cmd_completion(struct xhci_hcd *xhci,
1311 struct xhci_event_cmd *event)
1312{
1313 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1314 u64 cmd_dma;
1315 dma_addr_t cmd_dequeue_dma;
1316 u32 cmd_comp_code;
1317 union xhci_trb *cmd_trb;
1318 struct xhci_command *cmd;
1319 u32 cmd_type;
1320
1321 cmd_dma = le64_to_cpu(event->cmd_trb);
1322 cmd_trb = xhci->cmd_ring->dequeue;
1323
1324 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1325
1326 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1327 cmd_trb);
1328
1329
1330
1331
1332 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1333 xhci_warn(xhci,
1334 "ERROR mismatched command completion event\n");
1335 return;
1336 }
1337
1338 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1339
1340 cancel_delayed_work(&xhci->cmd_timer);
1341
1342 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1343
1344
1345 if (cmd_comp_code == COMP_STOPPED) {
1346 complete_all(&xhci->cmd_ring_stop_completion);
1347 return;
1348 }
1349
1350 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1351 xhci_err(xhci,
1352 "Command completion event does not match command\n");
1353 return;
1354 }
1355
1356
1357
1358
1359
1360
1361
1362 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1363 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1364 if (cmd->status == COMP_COMMAND_ABORTED) {
1365 if (xhci->current_cmd == cmd)
1366 xhci->current_cmd = NULL;
1367 goto event_handled;
1368 }
1369 }
1370
1371 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1372 switch (cmd_type) {
1373 case TRB_ENABLE_SLOT:
1374 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1375 break;
1376 case TRB_DISABLE_SLOT:
1377 xhci_handle_cmd_disable_slot(xhci, slot_id);
1378 break;
1379 case TRB_CONFIG_EP:
1380 if (!cmd->completion)
1381 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1382 cmd_comp_code);
1383 break;
1384 case TRB_EVAL_CONTEXT:
1385 break;
1386 case TRB_ADDR_DEV:
1387 break;
1388 case TRB_STOP_RING:
1389 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1390 le32_to_cpu(cmd_trb->generic.field[3])));
1391 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1392 break;
1393 case TRB_SET_DEQ:
1394 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1395 le32_to_cpu(cmd_trb->generic.field[3])));
1396 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1397 break;
1398 case TRB_CMD_NOOP:
1399
1400 if (cmd->status == COMP_STOPPED)
1401 cmd_comp_code = COMP_STOPPED;
1402 break;
1403 case TRB_RESET_EP:
1404 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1405 le32_to_cpu(cmd_trb->generic.field[3])));
1406 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1407 break;
1408 case TRB_RESET_DEV:
1409
1410
1411
1412 slot_id = TRB_TO_SLOT_ID(
1413 le32_to_cpu(cmd_trb->generic.field[3]));
1414 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1415 break;
1416 case TRB_NEC_GET_FW:
1417 xhci_handle_cmd_nec_get_fw(xhci, event);
1418 break;
1419 default:
1420
1421 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1422 break;
1423 }
1424
1425
1426 if (!list_is_singular(&xhci->cmd_list)) {
1427 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1428 struct xhci_command, cmd_list);
1429 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1430 } else if (xhci->current_cmd == cmd) {
1431 xhci->current_cmd = NULL;
1432 }
1433
1434event_handled:
1435 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1436
1437 inc_deq(xhci, xhci->cmd_ring);
1438}
1439
1440static void handle_vendor_event(struct xhci_hcd *xhci,
1441 union xhci_trb *event)
1442{
1443 u32 trb_type;
1444
1445 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1446 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1447 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1448 handle_cmd_completion(xhci, &event->event_cmd);
1449}
1450
1451
1452
1453
1454
1455
1456
1457
1458static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1459 struct xhci_hcd *xhci, u32 port_id)
1460{
1461 unsigned int i;
1462 unsigned int num_similar_speed_ports = 0;
1463
1464
1465
1466
1467
1468 for (i = 0; i < (port_id - 1); i++) {
1469 u8 port_speed = xhci->port_array[i];
1470
1471
1472
1473
1474
1475 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1476 continue;
1477
1478
1479
1480
1481
1482
1483 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1484 num_similar_speed_ports++;
1485 }
1486 return num_similar_speed_ports;
1487}
1488
1489static void handle_device_notification(struct xhci_hcd *xhci,
1490 union xhci_trb *event)
1491{
1492 u32 slot_id;
1493 struct usb_device *udev;
1494
1495 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1496 if (!xhci->devs[slot_id]) {
1497 xhci_warn(xhci, "Device Notification event for "
1498 "unused slot %u\n", slot_id);
1499 return;
1500 }
1501
1502 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1503 slot_id);
1504 udev = xhci->devs[slot_id]->udev;
1505 if (udev && udev->parent)
1506 usb_wakeup_notification(udev->parent, udev->portnum);
1507}
1508
1509static void handle_port_status(struct xhci_hcd *xhci,
1510 union xhci_trb *event)
1511{
1512 struct usb_hcd *hcd;
1513 u32 port_id;
1514 u32 temp, temp1;
1515 int max_ports;
1516 int slot_id;
1517 unsigned int faked_port_index;
1518 u8 major_revision;
1519 struct xhci_bus_state *bus_state;
1520 __le32 __iomem **port_array;
1521 bool bogus_port_status = false;
1522
1523
1524 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1525 xhci_warn(xhci,
1526 "WARN: xHC returned failed port status event\n");
1527
1528 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1529 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1530
1531 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1532 if ((port_id <= 0) || (port_id > max_ports)) {
1533 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1534 inc_deq(xhci, xhci->event_ring);
1535 return;
1536 }
1537
1538
1539
1540
1541 major_revision = xhci->port_array[port_id - 1];
1542
1543
1544 hcd = xhci_to_hcd(xhci);
1545 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1546 hcd = xhci->shared_hcd;
1547
1548 if (major_revision == 0) {
1549 xhci_warn(xhci, "Event for port %u not in "
1550 "Extended Capabilities, ignoring.\n",
1551 port_id);
1552 bogus_port_status = true;
1553 goto cleanup;
1554 }
1555 if (major_revision == DUPLICATE_ENTRY) {
1556 xhci_warn(xhci, "Event for port %u duplicated in"
1557 "Extended Capabilities, ignoring.\n",
1558 port_id);
1559 bogus_port_status = true;
1560 goto cleanup;
1561 }
1562
1563
1564
1565
1566
1567
1568
1569
1570 bus_state = &xhci->bus_state[hcd_index(hcd)];
1571 if (hcd->speed >= HCD_USB3)
1572 port_array = xhci->usb3_ports;
1573 else
1574 port_array = xhci->usb2_ports;
1575
1576 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1577 port_id);
1578
1579 temp = readl(port_array[faked_port_index]);
1580 if (hcd->state == HC_STATE_SUSPENDED) {
1581 xhci_dbg(xhci, "resume root hub\n");
1582 usb_hcd_resume_root_hub(hcd);
1583 }
1584
1585 if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE)
1586 bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
1587
1588 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1589 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1590
1591 temp1 = readl(&xhci->op_regs->command);
1592 if (!(temp1 & CMD_RUN)) {
1593 xhci_warn(xhci, "xHC is not running.\n");
1594 goto cleanup;
1595 }
1596
1597 if (DEV_SUPERSPEED_ANY(temp)) {
1598 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1599
1600
1601
1602
1603 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1604 xhci_test_and_clear_bit(xhci, port_array,
1605 faked_port_index, PORT_PLC);
1606 xhci_set_link_state(xhci, port_array, faked_port_index,
1607 XDEV_U0);
1608
1609
1610
1611 bogus_port_status = true;
1612 goto cleanup;
1613 } else if (!test_bit(faked_port_index,
1614 &bus_state->resuming_ports)) {
1615 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1616 bus_state->resume_done[faked_port_index] = jiffies +
1617 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1618 set_bit(faked_port_index, &bus_state->resuming_ports);
1619 mod_timer(&hcd->rh_timer,
1620 bus_state->resume_done[faked_port_index]);
1621
1622 }
1623 }
1624
1625 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1626 DEV_SUPERSPEED_ANY(temp)) {
1627 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1628
1629
1630
1631
1632
1633
1634
1635 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1636 faked_port_index + 1);
1637 if (slot_id && xhci->devs[slot_id])
1638 xhci_ring_device(xhci, slot_id);
1639 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1640 bus_state->port_remote_wakeup &=
1641 ~(1 << faked_port_index);
1642 xhci_test_and_clear_bit(xhci, port_array,
1643 faked_port_index, PORT_PLC);
1644 usb_wakeup_notification(hcd->self.root_hub,
1645 faked_port_index + 1);
1646 bogus_port_status = true;
1647 goto cleanup;
1648 }
1649 }
1650
1651
1652
1653
1654
1655
1656 if (!DEV_SUPERSPEED_ANY(temp) &&
1657 test_and_clear_bit(faked_port_index,
1658 &bus_state->rexit_ports)) {
1659 complete(&bus_state->rexit_done[faked_port_index]);
1660 bogus_port_status = true;
1661 goto cleanup;
1662 }
1663
1664 if (hcd->speed < HCD_USB3)
1665 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1666 PORT_PLC);
1667
1668cleanup:
1669
1670 inc_deq(xhci, xhci->event_ring);
1671
1672
1673
1674
1675
1676 if (bogus_port_status)
1677 return;
1678
1679
1680
1681
1682
1683
1684
1685
1686 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1687 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1688 spin_unlock(&xhci->lock);
1689
1690 usb_hcd_poll_rh_status(hcd);
1691 spin_lock(&xhci->lock);
1692}
1693
1694
1695
1696
1697
1698
1699
1700struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1701 struct xhci_segment *start_seg,
1702 union xhci_trb *start_trb,
1703 union xhci_trb *end_trb,
1704 dma_addr_t suspect_dma,
1705 bool debug)
1706{
1707 dma_addr_t start_dma;
1708 dma_addr_t end_seg_dma;
1709 dma_addr_t end_trb_dma;
1710 struct xhci_segment *cur_seg;
1711
1712 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1713 cur_seg = start_seg;
1714
1715 do {
1716 if (start_dma == 0)
1717 return NULL;
1718
1719 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1720 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1721
1722 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1723
1724 if (debug)
1725 xhci_warn(xhci,
1726 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1727 (unsigned long long)suspect_dma,
1728 (unsigned long long)start_dma,
1729 (unsigned long long)end_trb_dma,
1730 (unsigned long long)cur_seg->dma,
1731 (unsigned long long)end_seg_dma);
1732
1733 if (end_trb_dma > 0) {
1734
1735 if (start_dma <= end_trb_dma) {
1736 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1737 return cur_seg;
1738 } else {
1739
1740
1741
1742 if ((suspect_dma >= start_dma &&
1743 suspect_dma <= end_seg_dma) ||
1744 (suspect_dma >= cur_seg->dma &&
1745 suspect_dma <= end_trb_dma))
1746 return cur_seg;
1747 }
1748 return NULL;
1749 } else {
1750
1751 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1752 return cur_seg;
1753 }
1754 cur_seg = cur_seg->next;
1755 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1756 } while (cur_seg != start_seg);
1757
1758 return NULL;
1759}
1760
1761static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1762 unsigned int slot_id, unsigned int ep_index,
1763 unsigned int stream_id,
1764 struct xhci_td *td, union xhci_trb *ep_trb)
1765{
1766 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1767 struct xhci_command *command;
1768 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1769 if (!command)
1770 return;
1771
1772 ep->ep_state |= EP_HALTED;
1773 ep->stopped_stream = stream_id;
1774
1775 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1776 xhci_cleanup_stalled_ring(xhci, ep_index, td);
1777
1778 ep->stopped_stream = 0;
1779
1780 xhci_ring_cmd_db(xhci);
1781}
1782
1783
1784
1785
1786
1787
1788
1789static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1790 struct xhci_ep_ctx *ep_ctx,
1791 unsigned int trb_comp_code)
1792{
1793
1794 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1795 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1796 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1797
1798
1799
1800
1801
1802
1803 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1804 return 1;
1805
1806 return 0;
1807}
1808
1809int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1810{
1811 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1812
1813
1814
1815 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1816 trb_comp_code);
1817 xhci_dbg(xhci, "Treating code as success.\n");
1818 return 1;
1819 }
1820 return 0;
1821}
1822
1823static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1824 struct xhci_ring *ep_ring, int *status)
1825{
1826 struct urb_priv *urb_priv;
1827 struct urb *urb = NULL;
1828
1829
1830 urb = td->urb;
1831 urb_priv = urb->hcpriv;
1832
1833
1834 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1835
1836
1837
1838
1839
1840
1841 if (urb->actual_length > urb->transfer_buffer_length) {
1842 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1843 urb->transfer_buffer_length, urb->actual_length);
1844 urb->actual_length = 0;
1845 *status = 0;
1846 }
1847 list_del_init(&td->td_list);
1848
1849 if (!list_empty(&td->cancelled_td_list))
1850 list_del_init(&td->cancelled_td_list);
1851
1852 inc_td_cnt(urb);
1853
1854 if (last_td_in_urb(td)) {
1855 if ((urb->actual_length != urb->transfer_buffer_length &&
1856 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1857 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1858 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1859 urb, urb->actual_length,
1860 urb->transfer_buffer_length, *status);
1861
1862
1863 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1864 *status = 0;
1865 xhci_giveback_urb_in_irq(xhci, td, *status);
1866 }
1867
1868 return 0;
1869}
1870
1871static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1872 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1873 struct xhci_virt_ep *ep, int *status, bool skip)
1874{
1875 struct xhci_virt_device *xdev;
1876 struct xhci_ep_ctx *ep_ctx;
1877 struct xhci_ring *ep_ring;
1878 unsigned int slot_id;
1879 u32 trb_comp_code;
1880 int ep_index;
1881
1882 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1883 xdev = xhci->devs[slot_id];
1884 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1885 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1886 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1887 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1888
1889 if (skip)
1890 goto td_cleanup;
1891
1892 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1893 trb_comp_code == COMP_STOPPED ||
1894 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1895
1896
1897
1898
1899 ep->stopped_td = td;
1900 return 0;
1901 }
1902 if (trb_comp_code == COMP_STALL_ERROR ||
1903 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1904 trb_comp_code)) {
1905
1906
1907
1908
1909
1910 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1911 ep_ring->stream_id, td, ep_trb);
1912 } else {
1913
1914 while (ep_ring->dequeue != td->last_trb)
1915 inc_deq(xhci, ep_ring);
1916 inc_deq(xhci, ep_ring);
1917 }
1918
1919td_cleanup:
1920 return xhci_td_cleanup(xhci, td, ep_ring, status);
1921}
1922
1923
1924static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1925 union xhci_trb *stop_trb)
1926{
1927 u32 sum;
1928 union xhci_trb *trb = ring->dequeue;
1929 struct xhci_segment *seg = ring->deq_seg;
1930
1931 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
1932 if (!trb_is_noop(trb) && !trb_is_link(trb))
1933 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
1934 }
1935 return sum;
1936}
1937
1938
1939
1940
1941static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1942 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1943 struct xhci_virt_ep *ep, int *status)
1944{
1945 struct xhci_virt_device *xdev;
1946 struct xhci_ring *ep_ring;
1947 unsigned int slot_id;
1948 int ep_index;
1949 struct xhci_ep_ctx *ep_ctx;
1950 u32 trb_comp_code;
1951 u32 remaining, requested;
1952 u32 trb_type;
1953
1954 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
1955 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1956 xdev = xhci->devs[slot_id];
1957 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1958 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1959 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1960 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1961 requested = td->urb->transfer_buffer_length;
1962 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1963
1964 switch (trb_comp_code) {
1965 case COMP_SUCCESS:
1966 if (trb_type != TRB_STATUS) {
1967 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
1968 (trb_type == TRB_DATA) ? "data" : "setup");
1969 *status = -ESHUTDOWN;
1970 break;
1971 }
1972 *status = 0;
1973 break;
1974 case COMP_SHORT_PACKET:
1975 *status = 0;
1976 break;
1977 case COMP_STOPPED_SHORT_PACKET:
1978 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
1979 td->urb->actual_length = remaining;
1980 else
1981 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1982 goto finish_td;
1983 case COMP_STOPPED:
1984 switch (trb_type) {
1985 case TRB_SETUP:
1986 td->urb->actual_length = 0;
1987 goto finish_td;
1988 case TRB_DATA:
1989 case TRB_NORMAL:
1990 td->urb->actual_length = requested - remaining;
1991 goto finish_td;
1992 case TRB_STATUS:
1993 td->urb->actual_length = requested;
1994 goto finish_td;
1995 default:
1996 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
1997 trb_type);
1998 goto finish_td;
1999 }
2000 case COMP_STOPPED_LENGTH_INVALID:
2001 goto finish_td;
2002 default:
2003 if (!xhci_requires_manual_halt_cleanup(xhci,
2004 ep_ctx, trb_comp_code))
2005 break;
2006 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2007 trb_comp_code, ep_index);
2008
2009 case COMP_STALL_ERROR:
2010
2011 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2012 td->urb->actual_length = requested - remaining;
2013 else if (!td->urb_length_set)
2014 td->urb->actual_length = 0;
2015 goto finish_td;
2016 }
2017
2018
2019 if (trb_type == TRB_SETUP)
2020 goto finish_td;
2021
2022
2023
2024
2025
2026 if (trb_type == TRB_DATA ||
2027 trb_type == TRB_NORMAL) {
2028 td->urb_length_set = true;
2029 td->urb->actual_length = requested - remaining;
2030 xhci_dbg(xhci, "Waiting for status stage event\n");
2031 return 0;
2032 }
2033
2034
2035 if (!td->urb_length_set)
2036 td->urb->actual_length = requested;
2037
2038finish_td:
2039 return finish_td(xhci, td, ep_trb, event, ep, status, false);
2040}
2041
2042
2043
2044
2045static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2046 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2047 struct xhci_virt_ep *ep, int *status)
2048{
2049 struct xhci_ring *ep_ring;
2050 struct urb_priv *urb_priv;
2051 int idx;
2052 struct usb_iso_packet_descriptor *frame;
2053 u32 trb_comp_code;
2054 bool sum_trbs_for_length = false;
2055 u32 remaining, requested, ep_trb_len;
2056 int short_framestatus;
2057
2058 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2059 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2060 urb_priv = td->urb->hcpriv;
2061 idx = urb_priv->num_tds_done;
2062 frame = &td->urb->iso_frame_desc[idx];
2063 requested = frame->length;
2064 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2065 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2066 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2067 -EREMOTEIO : 0;
2068
2069
2070 switch (trb_comp_code) {
2071 case COMP_SUCCESS:
2072 if (remaining) {
2073 frame->status = short_framestatus;
2074 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2075 sum_trbs_for_length = true;
2076 break;
2077 }
2078 frame->status = 0;
2079 break;
2080 case COMP_SHORT_PACKET:
2081 frame->status = short_framestatus;
2082 sum_trbs_for_length = true;
2083 break;
2084 case COMP_BANDWIDTH_OVERRUN_ERROR:
2085 frame->status = -ECOMM;
2086 break;
2087 case COMP_ISOCH_BUFFER_OVERRUN:
2088 case COMP_BABBLE_DETECTED_ERROR:
2089 frame->status = -EOVERFLOW;
2090 break;
2091 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2092 case COMP_STALL_ERROR:
2093 frame->status = -EPROTO;
2094 break;
2095 case COMP_USB_TRANSACTION_ERROR:
2096 frame->status = -EPROTO;
2097 if (ep_trb != td->last_trb)
2098 return 0;
2099 break;
2100 case COMP_STOPPED:
2101 sum_trbs_for_length = true;
2102 break;
2103 case COMP_STOPPED_SHORT_PACKET:
2104
2105 frame->status = short_framestatus;
2106 requested = remaining;
2107 break;
2108 case COMP_STOPPED_LENGTH_INVALID:
2109 requested = 0;
2110 remaining = 0;
2111 break;
2112 default:
2113 sum_trbs_for_length = true;
2114 frame->status = -1;
2115 break;
2116 }
2117
2118 if (sum_trbs_for_length)
2119 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2120 ep_trb_len - remaining;
2121 else
2122 frame->actual_length = requested;
2123
2124 td->urb->actual_length += frame->actual_length;
2125
2126 return finish_td(xhci, td, ep_trb, event, ep, status, false);
2127}
2128
2129static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2130 struct xhci_transfer_event *event,
2131 struct xhci_virt_ep *ep, int *status)
2132{
2133 struct xhci_ring *ep_ring;
2134 struct urb_priv *urb_priv;
2135 struct usb_iso_packet_descriptor *frame;
2136 int idx;
2137
2138 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2139 urb_priv = td->urb->hcpriv;
2140 idx = urb_priv->num_tds_done;
2141 frame = &td->urb->iso_frame_desc[idx];
2142
2143
2144 frame->status = -EXDEV;
2145
2146
2147 frame->actual_length = 0;
2148
2149
2150 while (ep_ring->dequeue != td->last_trb)
2151 inc_deq(xhci, ep_ring);
2152 inc_deq(xhci, ep_ring);
2153
2154 return finish_td(xhci, td, NULL, event, ep, status, true);
2155}
2156
2157
2158
2159
2160static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2161 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2162 struct xhci_virt_ep *ep, int *status)
2163{
2164 struct xhci_ring *ep_ring;
2165 u32 trb_comp_code;
2166 u32 remaining, requested, ep_trb_len;
2167
2168 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2169 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2170 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2171 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2172 requested = td->urb->transfer_buffer_length;
2173
2174 switch (trb_comp_code) {
2175 case COMP_SUCCESS:
2176
2177 if (ep_trb != td->last_trb || remaining) {
2178 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2179 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2180 td->urb->ep->desc.bEndpointAddress,
2181 requested, remaining);
2182 }
2183 *status = 0;
2184 break;
2185 case COMP_SHORT_PACKET:
2186 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2187 td->urb->ep->desc.bEndpointAddress,
2188 requested, remaining);
2189 *status = 0;
2190 break;
2191 case COMP_STOPPED_SHORT_PACKET:
2192 td->urb->actual_length = remaining;
2193 goto finish_td;
2194 case COMP_STOPPED_LENGTH_INVALID:
2195
2196 ep_trb_len = 0;
2197 remaining = 0;
2198 break;
2199 default:
2200
2201 break;
2202 }
2203
2204 if (ep_trb == td->last_trb)
2205 td->urb->actual_length = requested - remaining;
2206 else
2207 td->urb->actual_length =
2208 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2209 ep_trb_len - remaining;
2210finish_td:
2211 if (remaining > requested) {
2212 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2213 remaining);
2214 td->urb->actual_length = 0;
2215 }
2216 return finish_td(xhci, td, ep_trb, event, ep, status, false);
2217}
2218
2219
2220
2221
2222
2223
2224static int handle_tx_event(struct xhci_hcd *xhci,
2225 struct xhci_transfer_event *event)
2226{
2227 struct xhci_virt_device *xdev;
2228 struct xhci_virt_ep *ep;
2229 struct xhci_ring *ep_ring;
2230 unsigned int slot_id;
2231 int ep_index;
2232 struct xhci_td *td = NULL;
2233 dma_addr_t ep_trb_dma;
2234 struct xhci_segment *ep_seg;
2235 union xhci_trb *ep_trb;
2236 int status = -EINPROGRESS;
2237 struct xhci_ep_ctx *ep_ctx;
2238 struct list_head *tmp;
2239 u32 trb_comp_code;
2240 int td_num = 0;
2241 bool handling_skipped_tds = false;
2242
2243 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2244 xdev = xhci->devs[slot_id];
2245 if (!xdev) {
2246 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2247 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2248 (unsigned long long) xhci_trb_virt_to_dma(
2249 xhci->event_ring->deq_seg,
2250 xhci->event_ring->dequeue),
2251 lower_32_bits(le64_to_cpu(event->buffer)),
2252 upper_32_bits(le64_to_cpu(event->buffer)),
2253 le32_to_cpu(event->transfer_len),
2254 le32_to_cpu(event->flags));
2255 xhci_dbg(xhci, "Event ring:\n");
2256 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2257 return -ENODEV;
2258 }
2259
2260
2261 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2262 ep = &xdev->eps[ep_index];
2263 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2264 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2265 if (!ep_ring || GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2266 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2267 "or incorrect stream ring\n");
2268 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2269 (unsigned long long) xhci_trb_virt_to_dma(
2270 xhci->event_ring->deq_seg,
2271 xhci->event_ring->dequeue),
2272 lower_32_bits(le64_to_cpu(event->buffer)),
2273 upper_32_bits(le64_to_cpu(event->buffer)),
2274 le32_to_cpu(event->transfer_len),
2275 le32_to_cpu(event->flags));
2276 xhci_dbg(xhci, "Event ring:\n");
2277 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2278 return -ENODEV;
2279 }
2280
2281
2282 if (ep->skip) {
2283 list_for_each(tmp, &ep_ring->td_list)
2284 td_num++;
2285 }
2286
2287 ep_trb_dma = le64_to_cpu(event->buffer);
2288 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2289
2290 switch (trb_comp_code) {
2291
2292
2293
2294 case COMP_SUCCESS:
2295 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2296 break;
2297 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2298 trb_comp_code = COMP_SHORT_PACKET;
2299 else
2300 xhci_warn_ratelimited(xhci,
2301 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2302 case COMP_SHORT_PACKET:
2303 break;
2304 case COMP_STOPPED:
2305 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2306 break;
2307 case COMP_STOPPED_LENGTH_INVALID:
2308 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2309 break;
2310 case COMP_STOPPED_SHORT_PACKET:
2311 xhci_dbg(xhci, "Stopped with short packet transfer detected\n");
2312 break;
2313 case COMP_STALL_ERROR:
2314 xhci_dbg(xhci, "Stalled endpoint\n");
2315 ep->ep_state |= EP_HALTED;
2316 status = -EPIPE;
2317 break;
2318 case COMP_TRB_ERROR:
2319 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2320 status = -EILSEQ;
2321 break;
2322 case COMP_SPLIT_TRANSACTION_ERROR:
2323 case COMP_USB_TRANSACTION_ERROR:
2324 xhci_dbg(xhci, "Transfer error on endpoint\n");
2325 status = -EPROTO;
2326 break;
2327 case COMP_BABBLE_DETECTED_ERROR:
2328 xhci_dbg(xhci, "Babble error on endpoint\n");
2329 status = -EOVERFLOW;
2330 break;
2331 case COMP_DATA_BUFFER_ERROR:
2332 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2333 status = -ENOSR;
2334 break;
2335 case COMP_BANDWIDTH_OVERRUN_ERROR:
2336 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2337 break;
2338 case COMP_ISOCH_BUFFER_OVERRUN:
2339 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2340 break;
2341 case COMP_RING_UNDERRUN:
2342
2343
2344
2345
2346
2347 xhci_dbg(xhci, "underrun event on endpoint\n");
2348 if (!list_empty(&ep_ring->td_list))
2349 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2350 "still with TDs queued?\n",
2351 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2352 ep_index);
2353 goto cleanup;
2354 case COMP_RING_OVERRUN:
2355 xhci_dbg(xhci, "overrun event on endpoint\n");
2356 if (!list_empty(&ep_ring->td_list))
2357 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2358 "still with TDs queued?\n",
2359 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2360 ep_index);
2361 goto cleanup;
2362 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2363 xhci_warn(xhci, "WARN: detect an incompatible device");
2364 status = -EPROTO;
2365 break;
2366 case COMP_MISSED_SERVICE_ERROR:
2367
2368
2369
2370
2371
2372
2373 ep->skip = true;
2374 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2375 goto cleanup;
2376 case COMP_NO_PING_RESPONSE_ERROR:
2377 ep->skip = true;
2378 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2379 goto cleanup;
2380 default:
2381 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2382 status = 0;
2383 break;
2384 }
2385 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2386 trb_comp_code);
2387 goto cleanup;
2388 }
2389
2390 do {
2391
2392
2393
2394 if (list_empty(&ep_ring->td_list)) {
2395
2396
2397
2398
2399
2400 if (!(trb_comp_code == COMP_STOPPED ||
2401 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2402 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2403 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2404 ep_index);
2405 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2406 (le32_to_cpu(event->flags) &
2407 TRB_TYPE_BITMASK)>>10);
2408 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2409 }
2410 if (ep->skip) {
2411 ep->skip = false;
2412 xhci_dbg(xhci, "td_list is empty while skip "
2413 "flag set. Clear skip flag.\n");
2414 }
2415 goto cleanup;
2416 }
2417
2418
2419 if (ep->skip && td_num == 0) {
2420 ep->skip = false;
2421 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2422 "Clear skip flag.\n");
2423 goto cleanup;
2424 }
2425
2426 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2427 td_list);
2428 if (ep->skip)
2429 td_num--;
2430
2431
2432 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2433 td->last_trb, ep_trb_dma, false);
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2444 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2445 goto cleanup;
2446 }
2447
2448 if (!ep_seg) {
2449 if (!ep->skip ||
2450 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2451
2452
2453
2454
2455 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2456 ep_ring->last_td_was_short) {
2457 ep_ring->last_td_was_short = false;
2458 goto cleanup;
2459 }
2460
2461 xhci_err(xhci,
2462 "ERROR Transfer event TRB DMA ptr not "
2463 "part of current TD ep_index %d "
2464 "comp_code %u\n", ep_index,
2465 trb_comp_code);
2466 trb_in_td(xhci, ep_ring->deq_seg,
2467 ep_ring->dequeue, td->last_trb,
2468 ep_trb_dma, true);
2469 return -ESHUTDOWN;
2470 }
2471
2472 skip_isoc_td(xhci, td, event, ep, &status);
2473 goto cleanup;
2474 }
2475 if (trb_comp_code == COMP_SHORT_PACKET)
2476 ep_ring->last_td_was_short = true;
2477 else
2478 ep_ring->last_td_was_short = false;
2479
2480 if (ep->skip) {
2481 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2482 ep->skip = false;
2483 }
2484
2485 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2486 sizeof(*ep_trb)];
2487
2488 trace_xhci_handle_transfer(ep_ring,
2489 (struct xhci_generic_trb *) ep_trb);
2490
2491
2492
2493
2494
2495
2496
2497 if (trb_is_noop(ep_trb)) {
2498 xhci_dbg(xhci, "ep_trb is a no-op TRB. Skip it\n");
2499 goto cleanup;
2500 }
2501
2502
2503 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2504 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2505 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2506 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2507 else
2508 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2509 &status);
2510cleanup:
2511 handling_skipped_tds = ep->skip &&
2512 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2513 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2514
2515
2516
2517
2518
2519 if (!handling_skipped_tds)
2520 inc_deq(xhci, xhci->event_ring);
2521
2522
2523
2524
2525
2526
2527
2528 } while (handling_skipped_tds);
2529
2530 return 0;
2531}
2532
2533
2534
2535
2536
2537
2538
2539static int xhci_handle_event(struct xhci_hcd *xhci)
2540{
2541 union xhci_trb *event;
2542 int update_ptrs = 1;
2543 int ret;
2544
2545
2546 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2547 xhci_err(xhci, "ERROR event ring not ready\n");
2548 return -ENOMEM;
2549 }
2550
2551 event = xhci->event_ring->dequeue;
2552
2553 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2554 xhci->event_ring->cycle_state)
2555 return 0;
2556
2557 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2558
2559
2560
2561
2562
2563 rmb();
2564
2565 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2566 case TRB_TYPE(TRB_COMPLETION):
2567 handle_cmd_completion(xhci, &event->event_cmd);
2568 break;
2569 case TRB_TYPE(TRB_PORT_STATUS):
2570 handle_port_status(xhci, event);
2571 update_ptrs = 0;
2572 break;
2573 case TRB_TYPE(TRB_TRANSFER):
2574 ret = handle_tx_event(xhci, &event->trans_event);
2575 if (ret >= 0)
2576 update_ptrs = 0;
2577 break;
2578 case TRB_TYPE(TRB_DEV_NOTE):
2579 handle_device_notification(xhci, event);
2580 break;
2581 default:
2582 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2583 TRB_TYPE(48))
2584 handle_vendor_event(xhci, event);
2585 else
2586 xhci_warn(xhci, "ERROR unknown event type %d\n",
2587 TRB_FIELD_TO_TYPE(
2588 le32_to_cpu(event->event_cmd.flags)));
2589 }
2590
2591
2592
2593 if (xhci->xhc_state & XHCI_STATE_DYING) {
2594 xhci_dbg(xhci, "xHCI host dying, returning from "
2595 "event handler.\n");
2596 return 0;
2597 }
2598
2599 if (update_ptrs)
2600
2601 inc_deq(xhci, xhci->event_ring);
2602
2603
2604
2605
2606 return 1;
2607}
2608
2609
2610
2611
2612
2613
2614irqreturn_t xhci_irq(struct usb_hcd *hcd)
2615{
2616 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2617 union xhci_trb *event_ring_deq;
2618 irqreturn_t ret = IRQ_NONE;
2619 dma_addr_t deq;
2620 u64 temp_64;
2621 u32 status;
2622
2623 spin_lock(&xhci->lock);
2624
2625 status = readl(&xhci->op_regs->status);
2626 if (status == 0xffffffff) {
2627 ret = IRQ_HANDLED;
2628 goto out;
2629 }
2630
2631 if (!(status & STS_EINT))
2632 goto out;
2633
2634 if (status & STS_FATAL) {
2635 xhci_warn(xhci, "WARNING: Host System Error\n");
2636 xhci_halt(xhci);
2637 ret = IRQ_HANDLED;
2638 goto out;
2639 }
2640
2641
2642
2643
2644
2645
2646 status |= STS_EINT;
2647 writel(status, &xhci->op_regs->status);
2648
2649
2650
2651 if (hcd->irq) {
2652 u32 irq_pending;
2653
2654 irq_pending = readl(&xhci->ir_set->irq_pending);
2655 irq_pending |= IMAN_IP;
2656 writel(irq_pending, &xhci->ir_set->irq_pending);
2657 }
2658
2659 if (xhci->xhc_state & XHCI_STATE_DYING ||
2660 xhci->xhc_state & XHCI_STATE_HALTED) {
2661 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2662 "Shouldn't IRQs be disabled?\n");
2663
2664
2665
2666 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2667 xhci_write_64(xhci, temp_64 | ERST_EHB,
2668 &xhci->ir_set->erst_dequeue);
2669 ret = IRQ_HANDLED;
2670 goto out;
2671 }
2672
2673 event_ring_deq = xhci->event_ring->dequeue;
2674
2675
2676
2677 while (xhci_handle_event(xhci) > 0) {}
2678
2679 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2680
2681 if (event_ring_deq != xhci->event_ring->dequeue) {
2682 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2683 xhci->event_ring->dequeue);
2684 if (deq == 0)
2685 xhci_warn(xhci, "WARN something wrong with SW event "
2686 "ring dequeue ptr.\n");
2687
2688 temp_64 &= ERST_PTR_MASK;
2689 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2690 }
2691
2692
2693 temp_64 |= ERST_EHB;
2694 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2695 ret = IRQ_HANDLED;
2696
2697out:
2698 spin_unlock(&xhci->lock);
2699
2700 return ret;
2701}
2702
2703irqreturn_t xhci_msi_irq(int irq, void *hcd)
2704{
2705 return xhci_irq(hcd);
2706}
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2718 bool more_trbs_coming,
2719 u32 field1, u32 field2, u32 field3, u32 field4)
2720{
2721 struct xhci_generic_trb *trb;
2722
2723 trb = &ring->enqueue->generic;
2724 trb->field[0] = cpu_to_le32(field1);
2725 trb->field[1] = cpu_to_le32(field2);
2726 trb->field[2] = cpu_to_le32(field3);
2727 trb->field[3] = cpu_to_le32(field4);
2728
2729 trace_xhci_queue_trb(ring, trb);
2730
2731 inc_enq(xhci, ring, more_trbs_coming);
2732}
2733
2734
2735
2736
2737
2738static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2739 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2740{
2741 unsigned int num_trbs_needed;
2742
2743
2744 switch (ep_state) {
2745 case EP_STATE_DISABLED:
2746
2747
2748
2749
2750 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2751 return -ENOENT;
2752 case EP_STATE_ERROR:
2753 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2754
2755
2756 return -EINVAL;
2757 case EP_STATE_HALTED:
2758 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2759 case EP_STATE_STOPPED:
2760 case EP_STATE_RUNNING:
2761 break;
2762 default:
2763 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2764
2765
2766
2767
2768 return -EINVAL;
2769 }
2770
2771 while (1) {
2772 if (room_on_ring(xhci, ep_ring, num_trbs))
2773 break;
2774
2775 if (ep_ring == xhci->cmd_ring) {
2776 xhci_err(xhci, "Do not support expand command ring\n");
2777 return -ENOMEM;
2778 }
2779
2780 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2781 "ERROR no room on ep ring, try ring expansion");
2782 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2783 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2784 mem_flags)) {
2785 xhci_err(xhci, "Ring expansion failed\n");
2786 return -ENOMEM;
2787 }
2788 }
2789
2790 while (trb_is_link(ep_ring->enqueue)) {
2791
2792
2793
2794 if (!xhci_link_trb_quirk(xhci) &&
2795 !(ep_ring->type == TYPE_ISOC &&
2796 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2797 ep_ring->enqueue->link.control &=
2798 cpu_to_le32(~TRB_CHAIN);
2799 else
2800 ep_ring->enqueue->link.control |=
2801 cpu_to_le32(TRB_CHAIN);
2802
2803 wmb();
2804 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2805
2806
2807 if (link_trb_toggles_cycle(ep_ring->enqueue))
2808 ep_ring->cycle_state ^= 1;
2809
2810 ep_ring->enq_seg = ep_ring->enq_seg->next;
2811 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2812 }
2813 return 0;
2814}
2815
2816static int prepare_transfer(struct xhci_hcd *xhci,
2817 struct xhci_virt_device *xdev,
2818 unsigned int ep_index,
2819 unsigned int stream_id,
2820 unsigned int num_trbs,
2821 struct urb *urb,
2822 unsigned int td_index,
2823 gfp_t mem_flags)
2824{
2825 int ret;
2826 struct urb_priv *urb_priv;
2827 struct xhci_td *td;
2828 struct xhci_ring *ep_ring;
2829 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2830
2831 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2832 if (!ep_ring) {
2833 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2834 stream_id);
2835 return -EINVAL;
2836 }
2837
2838 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2839 num_trbs, mem_flags);
2840 if (ret)
2841 return ret;
2842
2843 urb_priv = urb->hcpriv;
2844 td = &urb_priv->td[td_index];
2845
2846 INIT_LIST_HEAD(&td->td_list);
2847 INIT_LIST_HEAD(&td->cancelled_td_list);
2848
2849 if (td_index == 0) {
2850 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2851 if (unlikely(ret))
2852 return ret;
2853 }
2854
2855 td->urb = urb;
2856
2857 list_add_tail(&td->td_list, &ep_ring->td_list);
2858 td->start_seg = ep_ring->enq_seg;
2859 td->first_trb = ep_ring->enqueue;
2860
2861 return 0;
2862}
2863
2864static unsigned int count_trbs(u64 addr, u64 len)
2865{
2866 unsigned int num_trbs;
2867
2868 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
2869 TRB_MAX_BUFF_SIZE);
2870 if (num_trbs == 0)
2871 num_trbs++;
2872
2873 return num_trbs;
2874}
2875
2876static inline unsigned int count_trbs_needed(struct urb *urb)
2877{
2878 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
2879}
2880
2881static unsigned int count_sg_trbs_needed(struct urb *urb)
2882{
2883 struct scatterlist *sg;
2884 unsigned int i, len, full_len, num_trbs = 0;
2885
2886 full_len = urb->transfer_buffer_length;
2887
2888 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
2889 len = sg_dma_len(sg);
2890 num_trbs += count_trbs(sg_dma_address(sg), len);
2891 len = min_t(unsigned int, len, full_len);
2892 full_len -= len;
2893 if (full_len == 0)
2894 break;
2895 }
2896
2897 return num_trbs;
2898}
2899
2900static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
2901{
2902 u64 addr, len;
2903
2904 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2905 len = urb->iso_frame_desc[i].length;
2906
2907 return count_trbs(addr, len);
2908}
2909
2910static void check_trb_math(struct urb *urb, int running_total)
2911{
2912 if (unlikely(running_total != urb->transfer_buffer_length))
2913 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2914 "queued %#x (%d), asked for %#x (%d)\n",
2915 __func__,
2916 urb->ep->desc.bEndpointAddress,
2917 running_total, running_total,
2918 urb->transfer_buffer_length,
2919 urb->transfer_buffer_length);
2920}
2921
2922static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2923 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2924 struct xhci_generic_trb *start_trb)
2925{
2926
2927
2928
2929
2930 wmb();
2931 if (start_cycle)
2932 start_trb->field[3] |= cpu_to_le32(start_cycle);
2933 else
2934 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2935 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2936}
2937
2938static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
2939 struct xhci_ep_ctx *ep_ctx)
2940{
2941 int xhci_interval;
2942 int ep_interval;
2943
2944 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2945 ep_interval = urb->interval;
2946
2947
2948 if (urb->dev->speed == USB_SPEED_LOW ||
2949 urb->dev->speed == USB_SPEED_FULL)
2950 ep_interval *= 8;
2951
2952
2953
2954
2955 if (xhci_interval != ep_interval) {
2956 dev_dbg_ratelimited(&urb->dev->dev,
2957 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
2958 ep_interval, ep_interval == 1 ? "" : "s",
2959 xhci_interval, xhci_interval == 1 ? "" : "s");
2960 urb->interval = xhci_interval;
2961
2962 if (urb->dev->speed == USB_SPEED_LOW ||
2963 urb->dev->speed == USB_SPEED_FULL)
2964 urb->interval /= 8;
2965 }
2966}
2967
2968
2969
2970
2971
2972
2973
2974int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2975 struct urb *urb, int slot_id, unsigned int ep_index)
2976{
2977 struct xhci_ep_ctx *ep_ctx;
2978
2979 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
2980 check_interval(xhci, urb, ep_ctx);
2981
2982 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
2983}
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3006 int trb_buff_len, unsigned int td_total_len,
3007 struct urb *urb, bool more_trbs_coming)
3008{
3009 u32 maxp, total_packet_count;
3010
3011
3012 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3013 return ((td_total_len - transferred) >> 10);
3014
3015
3016 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3017 trb_buff_len == td_total_len)
3018 return 0;
3019
3020
3021 if (xhci->quirks & XHCI_MTK_HOST)
3022 trb_buff_len = 0;
3023
3024 maxp = usb_endpoint_maxp(&urb->ep->desc);
3025 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3026
3027
3028 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3029}
3030
3031
3032static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3033 u32 *trb_buff_len, struct xhci_segment *seg)
3034{
3035 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3036 unsigned int unalign;
3037 unsigned int max_pkt;
3038 u32 new_buff_len;
3039
3040 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3041 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3042
3043
3044 if (unalign == 0)
3045 return 0;
3046
3047 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3048 unalign, *trb_buff_len);
3049
3050
3051 if (*trb_buff_len > unalign) {
3052 *trb_buff_len -= unalign;
3053 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3054 return 0;
3055 }
3056
3057
3058
3059
3060
3061
3062 new_buff_len = max_pkt - (enqd_len % max_pkt);
3063
3064 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3065 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3066
3067
3068 if (usb_urb_dir_out(urb)) {
3069 sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs,
3070 seg->bounce_buf, new_buff_len, enqd_len);
3071 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3072 max_pkt, DMA_TO_DEVICE);
3073 } else {
3074 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3075 max_pkt, DMA_FROM_DEVICE);
3076 }
3077
3078 if (dma_mapping_error(dev, seg->bounce_dma)) {
3079
3080 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3081 return 0;
3082 }
3083 *trb_buff_len = new_buff_len;
3084 seg->bounce_len = new_buff_len;
3085 seg->bounce_offs = enqd_len;
3086
3087 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3088
3089 return 1;
3090}
3091
3092
3093int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3094 struct urb *urb, int slot_id, unsigned int ep_index)
3095{
3096 struct xhci_ring *ring;
3097 struct urb_priv *urb_priv;
3098 struct xhci_td *td;
3099 struct xhci_generic_trb *start_trb;
3100 struct scatterlist *sg = NULL;
3101 bool more_trbs_coming = true;
3102 bool need_zero_pkt = false;
3103 bool first_trb = true;
3104 unsigned int num_trbs;
3105 unsigned int start_cycle, num_sgs = 0;
3106 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3107 int sent_len, ret;
3108 u32 field, length_field, remainder;
3109 u64 addr, send_addr;
3110
3111 ring = xhci_urb_to_transfer_ring(xhci, urb);
3112 if (!ring)
3113 return -EINVAL;
3114
3115 full_len = urb->transfer_buffer_length;
3116
3117 if (urb->num_sgs) {
3118 num_sgs = urb->num_mapped_sgs;
3119 sg = urb->sg;
3120 addr = (u64) sg_dma_address(sg);
3121 block_len = sg_dma_len(sg);
3122 num_trbs = count_sg_trbs_needed(urb);
3123 } else {
3124 num_trbs = count_trbs_needed(urb);
3125 addr = (u64) urb->transfer_dma;
3126 block_len = full_len;
3127 }
3128 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3129 ep_index, urb->stream_id,
3130 num_trbs, urb, 0, mem_flags);
3131 if (unlikely(ret < 0))
3132 return ret;
3133
3134 urb_priv = urb->hcpriv;
3135
3136
3137 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3138 need_zero_pkt = true;
3139
3140 td = &urb_priv->td[0];
3141
3142
3143
3144
3145
3146
3147 start_trb = &ring->enqueue->generic;
3148 start_cycle = ring->cycle_state;
3149 send_addr = addr;
3150
3151
3152 for (enqd_len = 0; first_trb || enqd_len < full_len;
3153 enqd_len += trb_buff_len) {
3154 field = TRB_TYPE(TRB_NORMAL);
3155
3156
3157 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3158 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3159
3160 if (enqd_len + trb_buff_len > full_len)
3161 trb_buff_len = full_len - enqd_len;
3162
3163
3164 if (first_trb) {
3165 first_trb = false;
3166 if (start_cycle == 0)
3167 field |= TRB_CYCLE;
3168 } else
3169 field |= ring->cycle_state;
3170
3171
3172
3173
3174 if (enqd_len + trb_buff_len < full_len) {
3175 field |= TRB_CHAIN;
3176 if (trb_is_link(ring->enqueue + 1)) {
3177 if (xhci_align_td(xhci, urb, enqd_len,
3178 &trb_buff_len,
3179 ring->enq_seg)) {
3180 send_addr = ring->enq_seg->bounce_dma;
3181
3182 td->bounce_seg = ring->enq_seg;
3183 }
3184 }
3185 }
3186 if (enqd_len + trb_buff_len >= full_len) {
3187 field &= ~TRB_CHAIN;
3188 field |= TRB_IOC;
3189 more_trbs_coming = false;
3190 td->last_trb = ring->enqueue;
3191 }
3192
3193
3194 if (usb_urb_dir_in(urb))
3195 field |= TRB_ISP;
3196
3197
3198 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3199 full_len, urb, more_trbs_coming);
3200
3201 length_field = TRB_LEN(trb_buff_len) |
3202 TRB_TD_SIZE(remainder) |
3203 TRB_INTR_TARGET(0);
3204
3205 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3206 lower_32_bits(send_addr),
3207 upper_32_bits(send_addr),
3208 length_field,
3209 field);
3210
3211 addr += trb_buff_len;
3212 sent_len = trb_buff_len;
3213
3214 while (sg && sent_len >= block_len) {
3215
3216 --num_sgs;
3217 sent_len -= block_len;
3218 if (num_sgs != 0) {
3219 sg = sg_next(sg);
3220 block_len = sg_dma_len(sg);
3221 addr = (u64) sg_dma_address(sg);
3222 addr += sent_len;
3223 }
3224 }
3225 block_len -= sent_len;
3226 send_addr = addr;
3227 }
3228
3229 if (need_zero_pkt) {
3230 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3231 ep_index, urb->stream_id,
3232 1, urb, 1, mem_flags);
3233 urb_priv->td[1].last_trb = ring->enqueue;
3234 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3235 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3236 }
3237
3238 check_trb_math(urb, enqd_len);
3239 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3240 start_cycle, start_trb);
3241 return 0;
3242}
3243
3244
3245int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3246 struct urb *urb, int slot_id, unsigned int ep_index)
3247{
3248 struct xhci_ring *ep_ring;
3249 int num_trbs;
3250 int ret;
3251 struct usb_ctrlrequest *setup;
3252 struct xhci_generic_trb *start_trb;
3253 int start_cycle;
3254 u32 field;
3255 struct urb_priv *urb_priv;
3256 struct xhci_td *td;
3257
3258 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3259 if (!ep_ring)
3260 return -EINVAL;
3261
3262
3263
3264
3265
3266 if (!urb->setup_packet)
3267 return -EINVAL;
3268
3269
3270 num_trbs = 2;
3271
3272
3273
3274
3275
3276 if (urb->transfer_buffer_length > 0)
3277 num_trbs++;
3278 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3279 ep_index, urb->stream_id,
3280 num_trbs, urb, 0, mem_flags);
3281 if (ret < 0)
3282 return ret;
3283
3284 urb_priv = urb->hcpriv;
3285 td = &urb_priv->td[0];
3286
3287
3288
3289
3290
3291
3292 start_trb = &ep_ring->enqueue->generic;
3293 start_cycle = ep_ring->cycle_state;
3294
3295
3296
3297 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3298 field = 0;
3299 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3300 if (start_cycle == 0)
3301 field |= 0x1;
3302
3303
3304 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3305 if (urb->transfer_buffer_length > 0) {
3306 if (setup->bRequestType & USB_DIR_IN)
3307 field |= TRB_TX_TYPE(TRB_DATA_IN);
3308 else
3309 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3310 }
3311 }
3312
3313 queue_trb(xhci, ep_ring, true,
3314 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3315 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3316 TRB_LEN(8) | TRB_INTR_TARGET(0),
3317
3318 field);
3319
3320
3321
3322 if (usb_urb_dir_in(urb))
3323 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3324 else
3325 field = TRB_TYPE(TRB_DATA);
3326
3327 if (urb->transfer_buffer_length > 0) {
3328 u32 length_field, remainder;
3329
3330 remainder = xhci_td_remainder(xhci, 0,
3331 urb->transfer_buffer_length,
3332 urb->transfer_buffer_length,
3333 urb, 1);
3334 length_field = TRB_LEN(urb->transfer_buffer_length) |
3335 TRB_TD_SIZE(remainder) |
3336 TRB_INTR_TARGET(0);
3337 if (setup->bRequestType & USB_DIR_IN)
3338 field |= TRB_DIR_IN;
3339 queue_trb(xhci, ep_ring, true,
3340 lower_32_bits(urb->transfer_dma),
3341 upper_32_bits(urb->transfer_dma),
3342 length_field,
3343 field | ep_ring->cycle_state);
3344 }
3345
3346
3347 td->last_trb = ep_ring->enqueue;
3348
3349
3350
3351 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3352 field = 0;
3353 else
3354 field = TRB_DIR_IN;
3355 queue_trb(xhci, ep_ring, false,
3356 0,
3357 0,
3358 TRB_INTR_TARGET(0),
3359
3360 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3361
3362 giveback_first_trb(xhci, slot_id, ep_index, 0,
3363 start_cycle, start_trb);
3364 return 0;
3365}
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3376 struct urb *urb, unsigned int total_packet_count)
3377{
3378 unsigned int max_burst;
3379
3380 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3381 return 0;
3382
3383 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3384 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3385}
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3396 struct urb *urb, unsigned int total_packet_count)
3397{
3398 unsigned int max_burst;
3399 unsigned int residue;
3400
3401 if (xhci->hci_version < 0x100)
3402 return 0;
3403
3404 if (urb->dev->speed >= USB_SPEED_SUPER) {
3405
3406 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3407 residue = total_packet_count % (max_burst + 1);
3408
3409
3410
3411 if (residue == 0)
3412 return max_burst;
3413 return residue - 1;
3414 }
3415 if (total_packet_count == 0)
3416 return 0;
3417 return total_packet_count - 1;
3418}
3419
3420
3421
3422
3423
3424
3425
3426
3427static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3428 struct urb *urb, int index)
3429{
3430 int start_frame, ist, ret = 0;
3431 int start_frame_id, end_frame_id, current_frame_id;
3432
3433 if (urb->dev->speed == USB_SPEED_LOW ||
3434 urb->dev->speed == USB_SPEED_FULL)
3435 start_frame = urb->start_frame + index * urb->interval;
3436 else
3437 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3448 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3449 ist <<= 3;
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464 current_frame_id = readl(&xhci->run_regs->microframe_index);
3465 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3466 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3467
3468 start_frame &= 0x7ff;
3469 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3470 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3471
3472 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3473 __func__, index, readl(&xhci->run_regs->microframe_index),
3474 start_frame_id, end_frame_id, start_frame);
3475
3476 if (start_frame_id < end_frame_id) {
3477 if (start_frame > end_frame_id ||
3478 start_frame < start_frame_id)
3479 ret = -EINVAL;
3480 } else if (start_frame_id > end_frame_id) {
3481 if ((start_frame > end_frame_id &&
3482 start_frame < start_frame_id))
3483 ret = -EINVAL;
3484 } else {
3485 ret = -EINVAL;
3486 }
3487
3488 if (index == 0) {
3489 if (ret == -EINVAL || start_frame == start_frame_id) {
3490 start_frame = start_frame_id + 1;
3491 if (urb->dev->speed == USB_SPEED_LOW ||
3492 urb->dev->speed == USB_SPEED_FULL)
3493 urb->start_frame = start_frame;
3494 else
3495 urb->start_frame = start_frame << 3;
3496 ret = 0;
3497 }
3498 }
3499
3500 if (ret) {
3501 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3502 start_frame, current_frame_id, index,
3503 start_frame_id, end_frame_id);
3504 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3505 return ret;
3506 }
3507
3508 return start_frame;
3509}
3510
3511
3512static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3513 struct urb *urb, int slot_id, unsigned int ep_index)
3514{
3515 struct xhci_ring *ep_ring;
3516 struct urb_priv *urb_priv;
3517 struct xhci_td *td;
3518 int num_tds, trbs_per_td;
3519 struct xhci_generic_trb *start_trb;
3520 bool first_trb;
3521 int start_cycle;
3522 u32 field, length_field;
3523 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3524 u64 start_addr, addr;
3525 int i, j;
3526 bool more_trbs_coming;
3527 struct xhci_virt_ep *xep;
3528 int frame_id;
3529
3530 xep = &xhci->devs[slot_id]->eps[ep_index];
3531 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3532
3533 num_tds = urb->number_of_packets;
3534 if (num_tds < 1) {
3535 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3536 return -EINVAL;
3537 }
3538 start_addr = (u64) urb->transfer_dma;
3539 start_trb = &ep_ring->enqueue->generic;
3540 start_cycle = ep_ring->cycle_state;
3541
3542 urb_priv = urb->hcpriv;
3543
3544 for (i = 0; i < num_tds; i++) {
3545 unsigned int total_pkt_count, max_pkt;
3546 unsigned int burst_count, last_burst_pkt_count;
3547 u32 sia_frame_id;
3548
3549 first_trb = true;
3550 running_total = 0;
3551 addr = start_addr + urb->iso_frame_desc[i].offset;
3552 td_len = urb->iso_frame_desc[i].length;
3553 td_remain_len = td_len;
3554 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3555 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3556
3557
3558 if (total_pkt_count == 0)
3559 total_pkt_count++;
3560 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3561 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3562 urb, total_pkt_count);
3563
3564 trbs_per_td = count_isoc_trbs_needed(urb, i);
3565
3566 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3567 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3568 if (ret < 0) {
3569 if (i == 0)
3570 return ret;
3571 goto cleanup;
3572 }
3573 td = &urb_priv->td[i];
3574
3575
3576 sia_frame_id = TRB_SIA;
3577 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3578 HCC_CFC(xhci->hcc_params)) {
3579 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3580 if (frame_id >= 0)
3581 sia_frame_id = TRB_FRAME_ID(frame_id);
3582 }
3583
3584
3585
3586
3587
3588 field = TRB_TYPE(TRB_ISOC) |
3589 TRB_TLBPC(last_burst_pkt_count) |
3590 sia_frame_id |
3591 (i ? ep_ring->cycle_state : !start_cycle);
3592
3593
3594 if (!xep->use_extended_tbc)
3595 field |= TRB_TBC(burst_count);
3596
3597
3598 for (j = 0; j < trbs_per_td; j++) {
3599 u32 remainder = 0;
3600
3601
3602 if (!first_trb)
3603 field = TRB_TYPE(TRB_NORMAL) |
3604 ep_ring->cycle_state;
3605
3606
3607 if (usb_urb_dir_in(urb))
3608 field |= TRB_ISP;
3609
3610
3611 if (j < trbs_per_td - 1) {
3612 more_trbs_coming = true;
3613 field |= TRB_CHAIN;
3614 } else {
3615 more_trbs_coming = false;
3616 td->last_trb = ep_ring->enqueue;
3617 field |= TRB_IOC;
3618
3619 if (xhci->hci_version >= 0x100 &&
3620 !(xhci->quirks & XHCI_AVOID_BEI) &&
3621 i < num_tds - 1)
3622 field |= TRB_BEI;
3623 }
3624
3625 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3626 if (trb_buff_len > td_remain_len)
3627 trb_buff_len = td_remain_len;
3628
3629
3630 remainder = xhci_td_remainder(xhci, running_total,
3631 trb_buff_len, td_len,
3632 urb, more_trbs_coming);
3633
3634 length_field = TRB_LEN(trb_buff_len) |
3635 TRB_INTR_TARGET(0);
3636
3637
3638 if (first_trb && xep->use_extended_tbc)
3639 length_field |= TRB_TD_SIZE_TBC(burst_count);
3640 else
3641 length_field |= TRB_TD_SIZE(remainder);
3642 first_trb = false;
3643
3644 queue_trb(xhci, ep_ring, more_trbs_coming,
3645 lower_32_bits(addr),
3646 upper_32_bits(addr),
3647 length_field,
3648 field);
3649 running_total += trb_buff_len;
3650
3651 addr += trb_buff_len;
3652 td_remain_len -= trb_buff_len;
3653 }
3654
3655
3656 if (running_total != td_len) {
3657 xhci_err(xhci, "ISOC TD length unmatch\n");
3658 ret = -EINVAL;
3659 goto cleanup;
3660 }
3661 }
3662
3663
3664 if (HCC_CFC(xhci->hcc_params))
3665 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3666
3667 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3668 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3669 usb_amd_quirk_pll_disable();
3670 }
3671 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3672
3673 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3674 start_cycle, start_trb);
3675 return 0;
3676cleanup:
3677
3678
3679 for (i--; i >= 0; i--)
3680 list_del_init(&urb_priv->td[i].td_list);
3681
3682
3683
3684
3685
3686
3687 urb_priv->td[0].last_trb = ep_ring->enqueue;
3688
3689 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3690
3691
3692 ep_ring->enqueue = urb_priv->td[0].first_trb;
3693 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3694 ep_ring->cycle_state = start_cycle;
3695 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3696 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3697 return ret;
3698}
3699
3700
3701
3702
3703
3704
3705
3706
3707int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3708 struct urb *urb, int slot_id, unsigned int ep_index)
3709{
3710 struct xhci_virt_device *xdev;
3711 struct xhci_ring *ep_ring;
3712 struct xhci_ep_ctx *ep_ctx;
3713 int start_frame;
3714 int num_tds, num_trbs, i;
3715 int ret;
3716 struct xhci_virt_ep *xep;
3717 int ist;
3718
3719 xdev = xhci->devs[slot_id];
3720 xep = &xhci->devs[slot_id]->eps[ep_index];
3721 ep_ring = xdev->eps[ep_index].ring;
3722 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3723
3724 num_trbs = 0;
3725 num_tds = urb->number_of_packets;
3726 for (i = 0; i < num_tds; i++)
3727 num_trbs += count_isoc_trbs_needed(urb, i);
3728
3729
3730
3731
3732 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3733 num_trbs, mem_flags);
3734 if (ret)
3735 return ret;
3736
3737
3738
3739
3740
3741 check_interval(xhci, urb, ep_ctx);
3742
3743
3744 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3745 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3746 urb->start_frame = xep->next_frame_id;
3747 goto skip_start_over;
3748 }
3749 }
3750
3751 start_frame = readl(&xhci->run_regs->microframe_index);
3752 start_frame &= 0x3fff;
3753
3754
3755
3756
3757 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3758 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3759 ist <<= 3;
3760 start_frame += ist + XHCI_CFC_DELAY;
3761 start_frame = roundup(start_frame, 8);
3762
3763
3764
3765
3766
3767 if (urb->dev->speed == USB_SPEED_LOW ||
3768 urb->dev->speed == USB_SPEED_FULL) {
3769 start_frame = roundup(start_frame, urb->interval << 3);
3770 urb->start_frame = start_frame >> 3;
3771 } else {
3772 start_frame = roundup(start_frame, urb->interval);
3773 urb->start_frame = start_frame;
3774 }
3775
3776skip_start_over:
3777 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3778
3779 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3780}
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3793 u32 field1, u32 field2,
3794 u32 field3, u32 field4, bool command_must_succeed)
3795{
3796 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3797 int ret;
3798
3799 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3800 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3801 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3802 return -ESHUTDOWN;
3803 }
3804
3805 if (!command_must_succeed)
3806 reserved_trbs++;
3807
3808 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3809 reserved_trbs, GFP_ATOMIC);
3810 if (ret < 0) {
3811 xhci_err(xhci, "ERR: No room for command on command ring\n");
3812 if (command_must_succeed)
3813 xhci_err(xhci, "ERR: Reserved TRB counting for "
3814 "unfailable commands failed.\n");
3815 return ret;
3816 }
3817
3818 cmd->command_trb = xhci->cmd_ring->enqueue;
3819
3820
3821 if (list_empty(&xhci->cmd_list)) {
3822 xhci->current_cmd = cmd;
3823 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3824 }
3825
3826 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3827
3828 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3829 field4 | xhci->cmd_ring->cycle_state);
3830 return 0;
3831}
3832
3833
3834int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3835 u32 trb_type, u32 slot_id)
3836{
3837 return queue_command(xhci, cmd, 0, 0, 0,
3838 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3839}
3840
3841
3842int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3843 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3844{
3845 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3846 upper_32_bits(in_ctx_ptr), 0,
3847 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3848 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3849}
3850
3851int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3852 u32 field1, u32 field2, u32 field3, u32 field4)
3853{
3854 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3855}
3856
3857
3858int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3859 u32 slot_id)
3860{
3861 return queue_command(xhci, cmd, 0, 0, 0,
3862 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3863 false);
3864}
3865
3866
3867int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3868 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3869 u32 slot_id, bool command_must_succeed)
3870{
3871 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3872 upper_32_bits(in_ctx_ptr), 0,
3873 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3874 command_must_succeed);
3875}
3876
3877
3878int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3879 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3880{
3881 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3882 upper_32_bits(in_ctx_ptr), 0,
3883 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3884 command_must_succeed);
3885}
3886
3887
3888
3889
3890
3891int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3892 int slot_id, unsigned int ep_index, int suspend)
3893{
3894 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3895 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3896 u32 type = TRB_TYPE(TRB_STOP_RING);
3897 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3898
3899 return queue_command(xhci, cmd, 0, 0, 0,
3900 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3901}
3902
3903
3904void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
3905 unsigned int slot_id, unsigned int ep_index,
3906 unsigned int stream_id,
3907 struct xhci_dequeue_state *deq_state)
3908{
3909 dma_addr_t addr;
3910 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3911 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3912 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3913 u32 trb_sct = 0;
3914 u32 type = TRB_TYPE(TRB_SET_DEQ);
3915 struct xhci_virt_ep *ep;
3916 struct xhci_command *cmd;
3917 int ret;
3918
3919 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
3920 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
3921 deq_state->new_deq_seg,
3922 (unsigned long long)deq_state->new_deq_seg->dma,
3923 deq_state->new_deq_ptr,
3924 (unsigned long long)xhci_trb_virt_to_dma(
3925 deq_state->new_deq_seg, deq_state->new_deq_ptr),
3926 deq_state->new_cycle_state);
3927
3928 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3929 deq_state->new_deq_ptr);
3930 if (addr == 0) {
3931 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3932 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3933 deq_state->new_deq_seg, deq_state->new_deq_ptr);
3934 return;
3935 }
3936 ep = &xhci->devs[slot_id]->eps[ep_index];
3937 if ((ep->ep_state & SET_DEQ_PENDING)) {
3938 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3939 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3940 return;
3941 }
3942
3943
3944 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
3945 if (!cmd) {
3946 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
3947 return;
3948 }
3949
3950 ep->queued_deq_seg = deq_state->new_deq_seg;
3951 ep->queued_deq_ptr = deq_state->new_deq_ptr;
3952 if (stream_id)
3953 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
3954 ret = queue_command(xhci, cmd,
3955 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
3956 upper_32_bits(addr), trb_stream_id,
3957 trb_slot_id | trb_ep_index | type, false);
3958 if (ret < 0) {
3959 xhci_free_command(xhci, cmd);
3960 return;
3961 }
3962
3963
3964
3965
3966
3967
3968 ep->ep_state |= SET_DEQ_PENDING;
3969}
3970
3971int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
3972 int slot_id, unsigned int ep_index)
3973{
3974 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3975 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3976 u32 type = TRB_TYPE(TRB_RESET_EP);
3977
3978 return queue_command(xhci, cmd, 0, 0, 0,
3979 trb_slot_id | trb_ep_index | type, false);
3980}
3981