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11#define DSS_SUBSYS_NAME "HDMIWP"
12
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/platform_device.h>
17#include <video/omapfb_dss.h>
18
19#include "dss.h"
20#include "hdmi.h"
21
22void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
23{
24#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
25
26 DUMPREG(HDMI_WP_REVISION);
27 DUMPREG(HDMI_WP_SYSCONFIG);
28 DUMPREG(HDMI_WP_IRQSTATUS_RAW);
29 DUMPREG(HDMI_WP_IRQSTATUS);
30 DUMPREG(HDMI_WP_IRQENABLE_SET);
31 DUMPREG(HDMI_WP_IRQENABLE_CLR);
32 DUMPREG(HDMI_WP_IRQWAKEEN);
33 DUMPREG(HDMI_WP_PWR_CTRL);
34 DUMPREG(HDMI_WP_DEBOUNCE);
35 DUMPREG(HDMI_WP_VIDEO_CFG);
36 DUMPREG(HDMI_WP_VIDEO_SIZE);
37 DUMPREG(HDMI_WP_VIDEO_TIMING_H);
38 DUMPREG(HDMI_WP_VIDEO_TIMING_V);
39 DUMPREG(HDMI_WP_CLK);
40 DUMPREG(HDMI_WP_AUDIO_CFG);
41 DUMPREG(HDMI_WP_AUDIO_CFG2);
42 DUMPREG(HDMI_WP_AUDIO_CTRL);
43 DUMPREG(HDMI_WP_AUDIO_DATA);
44}
45
46u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
47{
48 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
49}
50
51void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
52{
53 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
54
55 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
56}
57
58void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
59{
60 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
61}
62
63void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
64{
65 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
66}
67
68
69int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
70{
71
72 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
73 return 0;
74
75
76 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
77
78
79 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
80 != val) {
81 DSSERR("Failed to set PHY power mode to %d\n", val);
82 return -ETIMEDOUT;
83 }
84
85 return 0;
86}
87
88
89int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
90{
91
92 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
93
94
95 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
96 != val) {
97 DSSERR("Failed to set PLL_PWR_STATUS\n");
98 return -ETIMEDOUT;
99 }
100
101 return 0;
102}
103
104int hdmi_wp_video_start(struct hdmi_wp_data *wp)
105{
106 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
107
108 return 0;
109}
110
111void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
112{
113 int i;
114
115 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);
116
117 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
118
119 for (i = 0; i < 50; ++i) {
120 u32 v;
121
122 msleep(20);
123
124 v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
125 if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
126 return;
127 }
128
129 DSSERR("no HDMI FRAMEDONE when disabling output\n");
130}
131
132void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
133 struct hdmi_video_format *video_fmt)
134{
135 u32 l = 0;
136
137 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
138 10, 8);
139
140 l |= FLD_VAL(video_fmt->y_res, 31, 16);
141 l |= FLD_VAL(video_fmt->x_res, 15, 0);
142 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
143}
144
145void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
146 struct omap_video_timings *timings)
147{
148 u32 r;
149 bool vsync_pol, hsync_pol;
150 DSSDBG("Enter hdmi_wp_video_config_interface\n");
151
152 vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
153 hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
154
155 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
156 r = FLD_MOD(r, vsync_pol, 7, 7);
157 r = FLD_MOD(r, hsync_pol, 6, 6);
158 r = FLD_MOD(r, timings->interlace, 3, 3);
159 r = FLD_MOD(r, 1, 1, 0);
160 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
161}
162
163void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
164 struct omap_video_timings *timings)
165{
166 u32 timing_h = 0;
167 u32 timing_v = 0;
168
169 DSSDBG("Enter hdmi_wp_video_config_timing\n");
170
171 timing_h |= FLD_VAL(timings->hbp, 31, 20);
172 timing_h |= FLD_VAL(timings->hfp, 19, 8);
173 timing_h |= FLD_VAL(timings->hsw, 7, 0);
174 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
175
176 timing_v |= FLD_VAL(timings->vbp, 31, 20);
177 timing_v |= FLD_VAL(timings->vfp, 19, 8);
178 timing_v |= FLD_VAL(timings->vsw, 7, 0);
179 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
180}
181
182void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
183 struct omap_video_timings *timings, struct hdmi_config *param)
184{
185 DSSDBG("Enter hdmi_wp_video_init_format\n");
186
187 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
188 video_fmt->y_res = param->timings.y_res;
189 video_fmt->x_res = param->timings.x_res;
190 if (param->timings.interlace)
191 video_fmt->y_res /= 2;
192
193 timings->hbp = param->timings.hbp;
194 timings->hfp = param->timings.hfp;
195 timings->hsw = param->timings.hsw;
196 timings->vbp = param->timings.vbp;
197 timings->vfp = param->timings.vfp;
198 timings->vsw = param->timings.vsw;
199 timings->vsync_level = param->timings.vsync_level;
200 timings->hsync_level = param->timings.hsync_level;
201 timings->interlace = param->timings.interlace;
202}
203
204void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
205 struct hdmi_audio_format *aud_fmt)
206{
207 u32 r;
208
209 DSSDBG("Enter hdmi_wp_audio_config_format\n");
210
211 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
212 if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
213 omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
214 omapdss_get_version() == OMAPDSS_VER_OMAP4) {
215 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
216 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
217 }
218 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
219 r = FLD_MOD(r, aud_fmt->type, 4, 4);
220 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
221 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
222 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
223 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
224 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
225}
226
227void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
228 struct hdmi_audio_dma *aud_dma)
229{
230 u32 r;
231
232 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
233
234 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
235 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
236 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
237 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
238
239 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
240 r = FLD_MOD(r, aud_dma->mode, 9, 9);
241 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
242 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
243}
244
245int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
246{
247 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
248
249 return 0;
250}
251
252int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
253{
254 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
255
256 return 0;
257}
258
259int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)
260{
261 struct resource *res;
262
263 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
264 if (!res) {
265 DSSERR("can't get WP mem resource\n");
266 return -EINVAL;
267 }
268 wp->phys_base = res->start;
269
270 wp->base = devm_ioremap_resource(&pdev->dev, res);
271 if (IS_ERR(wp->base)) {
272 DSSERR("can't ioremap HDMI WP\n");
273 return PTR_ERR(wp->base);
274 }
275
276 return 0;
277}
278
279phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
280{
281 return wp->phys_base + HDMI_WP_AUDIO_DATA;
282}
283
