1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#ifndef _INTEL_IOMMU_H_
23#define _INTEL_IOMMU_H_
24
25#include <linux/types.h>
26#include <linux/iova.h>
27#include <linux/io.h>
28#include <linux/idr.h>
29#include <linux/dma_remapping.h>
30#include <linux/mmu_notifier.h>
31#include <linux/list.h>
32#include <linux/iommu.h>
33#include <asm/cacheflush.h>
34#include <asm/iommu.h>
35
36
37
38
39
40#define DMAR_VER_REG 0x0
41#define DMAR_CAP_REG 0x8
42#define DMAR_ECAP_REG 0x10
43#define DMAR_GCMD_REG 0x18
44#define DMAR_GSTS_REG 0x1c
45#define DMAR_RTADDR_REG 0x20
46#define DMAR_CCMD_REG 0x28
47#define DMAR_FSTS_REG 0x34
48#define DMAR_FECTL_REG 0x38
49#define DMAR_FEDATA_REG 0x3c
50#define DMAR_FEADDR_REG 0x40
51#define DMAR_FEUADDR_REG 0x44
52#define DMAR_AFLOG_REG 0x58
53#define DMAR_PMEN_REG 0x64
54#define DMAR_PLMBASE_REG 0x68
55#define DMAR_PLMLIMIT_REG 0x6c
56#define DMAR_PHMBASE_REG 0x70
57#define DMAR_PHMLIMIT_REG 0x78
58#define DMAR_IQH_REG 0x80
59#define DMAR_IQT_REG 0x88
60#define DMAR_IQ_SHIFT 4
61#define DMAR_IQA_REG 0x90
62#define DMAR_ICS_REG 0x9c
63#define DMAR_IRTA_REG 0xb8
64#define DMAR_PQH_REG 0xc0
65#define DMAR_PQT_REG 0xc8
66#define DMAR_PQA_REG 0xd0
67#define DMAR_PRS_REG 0xdc
68#define DMAR_PECTL_REG 0xe0
69#define DMAR_PEDATA_REG 0xe4
70#define DMAR_PEADDR_REG 0xe8
71#define DMAR_PEUADDR_REG 0xec
72
73#define OFFSET_STRIDE (9)
74
75#ifdef CONFIG_64BIT
76#define dmar_readq(a) readq(a)
77#define dmar_writeq(a,v) writeq(v,a)
78#else
79static inline u64 dmar_readq(void __iomem *addr)
80{
81 u32 lo, hi;
82 lo = readl(addr);
83 hi = readl(addr + 4);
84 return (((u64) hi) << 32) + lo;
85}
86
87static inline void dmar_writeq(void __iomem *addr, u64 val)
88{
89 writel((u32)val, addr);
90 writel((u32)(val >> 32), addr + 4);
91}
92#endif
93
94#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
95#define DMAR_VER_MINOR(v) ((v) & 0x0f)
96
97
98
99
100#define cap_pi_support(c) (((c) >> 59) & 1)
101#define cap_read_drain(c) (((c) >> 55) & 1)
102#define cap_write_drain(c) (((c) >> 54) & 1)
103#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
104#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
105#define cap_pgsel_inv(c) (((c) >> 39) & 1)
106
107#define cap_super_page_val(c) (((c) >> 34) & 0xf)
108#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
109 * OFFSET_STRIDE) + 21)
110
111#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
112#define cap_max_fault_reg_offset(c) \
113 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
114
115#define cap_zlr(c) (((c) >> 22) & 1)
116#define cap_isoch(c) (((c) >> 23) & 1)
117#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
118#define cap_sagaw(c) (((c) >> 8) & 0x1f)
119#define cap_caching_mode(c) (((c) >> 7) & 1)
120#define cap_phmr(c) (((c) >> 6) & 1)
121#define cap_plmr(c) (((c) >> 5) & 1)
122#define cap_rwbf(c) (((c) >> 4) & 1)
123#define cap_afl(c) (((c) >> 3) & 1)
124#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
125
126
127
128
129#define ecap_pasid(e) ((e >> 40) & 0x1)
130#define ecap_pss(e) ((e >> 35) & 0x1f)
131#define ecap_eafs(e) ((e >> 34) & 0x1)
132#define ecap_nwfs(e) ((e >> 33) & 0x1)
133#define ecap_srs(e) ((e >> 31) & 0x1)
134#define ecap_ers(e) ((e >> 30) & 0x1)
135#define ecap_prs(e) ((e >> 29) & 0x1)
136#define ecap_broken_pasid(e) ((e >> 28) & 0x1)
137#define ecap_dis(e) ((e >> 27) & 0x1)
138#define ecap_nest(e) ((e >> 26) & 0x1)
139#define ecap_mts(e) ((e >> 25) & 0x1)
140#define ecap_ecs(e) ((e >> 24) & 0x1)
141#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
142#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
143#define ecap_coherent(e) ((e) & 0x1)
144#define ecap_qis(e) ((e) & 0x2)
145#define ecap_pass_through(e) ((e >> 6) & 0x1)
146#define ecap_eim_support(e) ((e >> 4) & 0x1)
147#define ecap_ir_support(e) ((e >> 3) & 0x1)
148#define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
149#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
150#define ecap_sc_support(e) ((e >> 7) & 0x1)
151
152
153#define DMA_TLB_FLUSH_GRANU_OFFSET 60
154#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
155#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
156#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
157#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
158#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
159#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
160#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
161#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
162#define DMA_TLB_IVT (((u64)1) << 63)
163#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
164#define DMA_TLB_MAX_SIZE (0x3f)
165
166
167#define DMA_CCMD_INVL_GRANU_OFFSET 61
168#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
169#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
170#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
171#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
172#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
173#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
174#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
175#define DMA_ID_TLB_ADDR(addr) (addr)
176#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
177
178
179#define DMA_PMEN_EPM (((u32)1)<<31)
180#define DMA_PMEN_PRS (((u32)1)<<0)
181
182
183#define DMA_GCMD_TE (((u32)1) << 31)
184#define DMA_GCMD_SRTP (((u32)1) << 30)
185#define DMA_GCMD_SFL (((u32)1) << 29)
186#define DMA_GCMD_EAFL (((u32)1) << 28)
187#define DMA_GCMD_WBF (((u32)1) << 27)
188#define DMA_GCMD_QIE (((u32)1) << 26)
189#define DMA_GCMD_SIRTP (((u32)1) << 24)
190#define DMA_GCMD_IRE (((u32) 1) << 25)
191#define DMA_GCMD_CFI (((u32) 1) << 23)
192
193
194#define DMA_GSTS_TES (((u32)1) << 31)
195#define DMA_GSTS_RTPS (((u32)1) << 30)
196#define DMA_GSTS_FLS (((u32)1) << 29)
197#define DMA_GSTS_AFLS (((u32)1) << 28)
198#define DMA_GSTS_WBFS (((u32)1) << 27)
199#define DMA_GSTS_QIES (((u32)1) << 26)
200#define DMA_GSTS_IRTPS (((u32)1) << 24)
201#define DMA_GSTS_IRES (((u32)1) << 25)
202#define DMA_GSTS_CFIS (((u32)1) << 23)
203
204
205#define DMA_RTADDR_RTT (((u64)1) << 11)
206
207
208#define DMA_CCMD_ICC (((u64)1) << 63)
209#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
210#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
211#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
212#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
213#define DMA_CCMD_MASK_NOBIT 0
214#define DMA_CCMD_MASK_1BIT 1
215#define DMA_CCMD_MASK_2BIT 2
216#define DMA_CCMD_MASK_3BIT 3
217#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
218#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
219
220
221#define DMA_FECTL_IM (((u32)1) << 31)
222
223
224#define DMA_FSTS_PPF ((u32)2)
225#define DMA_FSTS_PFO ((u32)1)
226#define DMA_FSTS_IQE (1 << 4)
227#define DMA_FSTS_ICE (1 << 5)
228#define DMA_FSTS_ITE (1 << 6)
229#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
230
231
232#define DMA_FRCD_F (((u32)1) << 31)
233#define dma_frcd_type(d) ((d >> 30) & 1)
234#define dma_frcd_fault_reason(c) (c & 0xff)
235#define dma_frcd_source_id(c) (c & 0xffff)
236
237#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
238
239
240#define DMA_PRS_PPR ((u32)1)
241
242#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
243do { \
244 cycles_t start_time = get_cycles(); \
245 while (1) { \
246 sts = op(iommu->reg + offset); \
247 if (cond) \
248 break; \
249 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
250 panic("DMAR hardware is malfunctioning\n"); \
251 cpu_relax(); \
252 } \
253} while (0)
254
255#define QI_LENGTH 256
256
257enum {
258 QI_FREE,
259 QI_IN_USE,
260 QI_DONE,
261 QI_ABORT
262};
263
264#define QI_CC_TYPE 0x1
265#define QI_IOTLB_TYPE 0x2
266#define QI_DIOTLB_TYPE 0x3
267#define QI_IEC_TYPE 0x4
268#define QI_IWD_TYPE 0x5
269#define QI_EIOTLB_TYPE 0x6
270#define QI_PC_TYPE 0x7
271#define QI_DEIOTLB_TYPE 0x8
272#define QI_PGRP_RESP_TYPE 0x9
273#define QI_PSTRM_RESP_TYPE 0xa
274
275#define QI_IEC_SELECTIVE (((u64)1) << 4)
276#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
277#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
278
279#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
280#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
281
282#define QI_IOTLB_DID(did) (((u64)did) << 16)
283#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
284#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
285#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
286#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
287#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
288#define QI_IOTLB_AM(am) (((u8)am))
289
290#define QI_CC_FM(fm) (((u64)fm) << 48)
291#define QI_CC_SID(sid) (((u64)sid) << 32)
292#define QI_CC_DID(did) (((u64)did) << 16)
293#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
294
295#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
296#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
297#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
298#define QI_DEV_IOTLB_SIZE 1
299#define QI_DEV_IOTLB_MAX_INVS 32
300
301#define QI_PC_PASID(pasid) (((u64)pasid) << 32)
302#define QI_PC_DID(did) (((u64)did) << 16)
303#define QI_PC_GRAN(gran) (((u64)gran) << 4)
304
305#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
306#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
307
308#define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
309#define QI_EIOTLB_GL(gl) (((u64)gl) << 7)
310#define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
311#define QI_EIOTLB_AM(am) (((u64)am))
312#define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
313#define QI_EIOTLB_DID(did) (((u64)did) << 16)
314#define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
315
316#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
317#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
318#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
319#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
320#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
321#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
322#define QI_DEV_EIOTLB_MAX_INVS 32
323
324#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
325#define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
326#define QI_PGRP_RESP_CODE(res) ((u64)(res))
327#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
328#define QI_PGRP_DID(did) (((u64)(did)) << 16)
329#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
330
331#define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
332#define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
333#define QI_PSTRM_RESP_CODE(res) ((u64)(res))
334#define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
335#define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
336#define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
337#define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
338
339#define QI_RESP_SUCCESS 0x0
340#define QI_RESP_INVALID 0x1
341#define QI_RESP_FAILURE 0xf
342
343#define QI_GRAN_ALL_ALL 0
344#define QI_GRAN_NONG_ALL 1
345#define QI_GRAN_NONG_PASID 2
346#define QI_GRAN_PSI_PASID 3
347
348struct qi_desc {
349 u64 low, high;
350};
351
352struct q_inval {
353 raw_spinlock_t q_lock;
354 struct qi_desc *desc;
355 int *desc_status;
356 int free_head;
357 int free_tail;
358 int free_cnt;
359};
360
361#ifdef CONFIG_IRQ_REMAP
362
363#define INTR_REMAP_PAGE_ORDER 8
364#define INTR_REMAP_TABLE_REG_SIZE 0xf
365#define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
366
367#define INTR_REMAP_TABLE_ENTRIES 65536
368
369struct irq_domain;
370
371struct ir_table {
372 struct irte *base;
373 unsigned long *bitmap;
374};
375#endif
376
377struct iommu_flush {
378 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
379 u8 fm, u64 type);
380 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
381 unsigned int size_order, u64 type);
382};
383
384enum {
385 SR_DMAR_FECTL_REG,
386 SR_DMAR_FEDATA_REG,
387 SR_DMAR_FEADDR_REG,
388 SR_DMAR_FEUADDR_REG,
389 MAX_SR_DMAR_REGS
390};
391
392#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
393#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
394
395struct pasid_entry;
396struct pasid_state_entry;
397struct page_req_dsc;
398
399struct intel_iommu {
400 void __iomem *reg;
401 u64 reg_phys;
402 u64 reg_size;
403 u64 cap;
404 u64 ecap;
405 u32 gcmd;
406 raw_spinlock_t register_lock;
407 int seq_id;
408 int agaw;
409 int msagaw;
410 unsigned int irq, pr_irq;
411 u16 segment;
412 unsigned char name[13];
413
414#ifdef CONFIG_INTEL_IOMMU
415 unsigned long *domain_ids;
416 struct dmar_domain ***domains;
417 spinlock_t lock;
418 struct root_entry *root_entry;
419
420 struct iommu_flush flush;
421#endif
422#ifdef CONFIG_INTEL_IOMMU_SVM
423
424
425
426
427
428 struct pasid_entry *pasid_table;
429 struct pasid_state_entry *pasid_state_table;
430 struct page_req_dsc *prq;
431 unsigned char prq_name[16];
432 struct idr pasid_idr;
433 u32 pasid_max;
434#endif
435 struct q_inval *qi;
436 u32 *iommu_state;
437
438#ifdef CONFIG_IRQ_REMAP
439 struct ir_table *ir_table;
440 struct irq_domain *ir_domain;
441 struct irq_domain *ir_msi_domain;
442#endif
443 struct iommu_device iommu;
444 int node;
445 u32 flags;
446};
447
448static inline void __iommu_flush_cache(
449 struct intel_iommu *iommu, void *addr, int size)
450{
451 if (!ecap_coherent(iommu->ecap))
452 clflush_cache_range(addr, size);
453}
454
455extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
456extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
457
458extern int dmar_enable_qi(struct intel_iommu *iommu);
459extern void dmar_disable_qi(struct intel_iommu *iommu);
460extern int dmar_reenable_qi(struct intel_iommu *iommu);
461extern void qi_global_iec(struct intel_iommu *iommu);
462
463extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
464 u8 fm, u64 type);
465extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
466 unsigned int size_order, u64 type);
467extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
468 u64 addr, unsigned mask);
469
470extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
471
472extern int dmar_ir_support(void);
473
474#ifdef CONFIG_INTEL_IOMMU_SVM
475extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
476extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
477extern int intel_svm_enable_prq(struct intel_iommu *iommu);
478extern int intel_svm_finish_prq(struct intel_iommu *iommu);
479
480struct svm_dev_ops;
481
482struct intel_svm_dev {
483 struct list_head list;
484 struct rcu_head rcu;
485 struct device *dev;
486 struct svm_dev_ops *ops;
487 int users;
488 u16 did;
489 u16 dev_iotlb:1;
490 u16 sid, qdep;
491};
492
493struct intel_svm {
494 struct mmu_notifier notifier;
495 struct mm_struct *mm;
496 struct intel_iommu *iommu;
497 int flags;
498 int pasid;
499 struct list_head devs;
500};
501
502extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev);
503extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
504#endif
505
506extern const struct attribute_group *intel_iommu_groups[];
507
508#endif
509