linux/sound/soc/intel/haswell/sst-haswell-ipc.c
<<
>>
Prefs
   1/*
   2 *  Intel SST Haswell/Broadwell IPC Support
   3 *
   4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License version
   8 * 2 as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 */
  16
  17#include <linux/types.h>
  18#include <linux/kernel.h>
  19#include <linux/list.h>
  20#include <linux/device.h>
  21#include <linux/wait.h>
  22#include <linux/spinlock.h>
  23#include <linux/workqueue.h>
  24#include <linux/export.h>
  25#include <linux/slab.h>
  26#include <linux/delay.h>
  27#include <linux/sched.h>
  28#include <linux/platform_device.h>
  29#include <linux/firmware.h>
  30#include <linux/dma-mapping.h>
  31#include <linux/debugfs.h>
  32#include <linux/pm_runtime.h>
  33#include <sound/asound.h>
  34
  35#include "sst-haswell-ipc.h"
  36#include "../common/sst-dsp.h"
  37#include "../common/sst-dsp-priv.h"
  38#include "../common/sst-ipc.h"
  39
  40/* Global Message - Generic */
  41#define IPC_GLB_TYPE_SHIFT      24
  42#define IPC_GLB_TYPE_MASK       (0x1f << IPC_GLB_TYPE_SHIFT)
  43#define IPC_GLB_TYPE(x)         (x << IPC_GLB_TYPE_SHIFT)
  44
  45/* Global Message - Reply */
  46#define IPC_GLB_REPLY_SHIFT     0
  47#define IPC_GLB_REPLY_MASK      (0x1f << IPC_GLB_REPLY_SHIFT)
  48#define IPC_GLB_REPLY_TYPE(x)   (x << IPC_GLB_REPLY_TYPE_SHIFT)
  49
  50/* Stream Message - Generic */
  51#define IPC_STR_TYPE_SHIFT      20
  52#define IPC_STR_TYPE_MASK       (0xf << IPC_STR_TYPE_SHIFT)
  53#define IPC_STR_TYPE(x)         (x << IPC_STR_TYPE_SHIFT)
  54#define IPC_STR_ID_SHIFT        16
  55#define IPC_STR_ID_MASK         (0xf << IPC_STR_ID_SHIFT)
  56#define IPC_STR_ID(x)           (x << IPC_STR_ID_SHIFT)
  57
  58/* Stream Message - Reply */
  59#define IPC_STR_REPLY_SHIFT     0
  60#define IPC_STR_REPLY_MASK      (0x1f << IPC_STR_REPLY_SHIFT)
  61
  62/* Stream Stage Message - Generic */
  63#define IPC_STG_TYPE_SHIFT      12
  64#define IPC_STG_TYPE_MASK       (0xf << IPC_STG_TYPE_SHIFT)
  65#define IPC_STG_TYPE(x)         (x << IPC_STG_TYPE_SHIFT)
  66#define IPC_STG_ID_SHIFT        10
  67#define IPC_STG_ID_MASK         (0x3 << IPC_STG_ID_SHIFT)
  68#define IPC_STG_ID(x)           (x << IPC_STG_ID_SHIFT)
  69
  70/* Stream Stage Message - Reply */
  71#define IPC_STG_REPLY_SHIFT     0
  72#define IPC_STG_REPLY_MASK      (0x1f << IPC_STG_REPLY_SHIFT)
  73
  74/* Debug Log Message - Generic */
  75#define IPC_LOG_OP_SHIFT        20
  76#define IPC_LOG_OP_MASK         (0xf << IPC_LOG_OP_SHIFT)
  77#define IPC_LOG_OP_TYPE(x)      (x << IPC_LOG_OP_SHIFT)
  78#define IPC_LOG_ID_SHIFT        16
  79#define IPC_LOG_ID_MASK         (0xf << IPC_LOG_ID_SHIFT)
  80#define IPC_LOG_ID(x)           (x << IPC_LOG_ID_SHIFT)
  81
  82/* Module Message */
  83#define IPC_MODULE_OPERATION_SHIFT      20
  84#define IPC_MODULE_OPERATION_MASK       (0xf << IPC_MODULE_OPERATION_SHIFT)
  85#define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT)
  86
  87#define IPC_MODULE_ID_SHIFT     16
  88#define IPC_MODULE_ID_MASK      (0xf << IPC_MODULE_ID_SHIFT)
  89#define IPC_MODULE_ID(x)        (x << IPC_MODULE_ID_SHIFT)
  90
  91/* IPC message timeout (msecs) */
  92#define IPC_TIMEOUT_MSECS       300
  93#define IPC_BOOT_MSECS          200
  94#define IPC_MSG_WAIT            0
  95#define IPC_MSG_NOWAIT          1
  96
  97/* Firmware Ready Message */
  98#define IPC_FW_READY            (0x1 << 29)
  99#define IPC_STATUS_MASK         (0x3 << 30)
 100
 101#define IPC_EMPTY_LIST_SIZE     8
 102#define IPC_MAX_STREAMS         4
 103
 104/* Mailbox */
 105#define IPC_MAX_MAILBOX_BYTES   256
 106
 107#define INVALID_STREAM_HW_ID    0xffffffff
 108
 109/* Global Message - Types and Replies */
 110enum ipc_glb_type {
 111        IPC_GLB_GET_FW_VERSION = 0,             /* Retrieves firmware version */
 112        IPC_GLB_PERFORMANCE_MONITOR = 1,        /* Performance monitoring actions */
 113        IPC_GLB_ALLOCATE_STREAM = 3,            /* Request to allocate new stream */
 114        IPC_GLB_FREE_STREAM = 4,                /* Request to free stream */
 115        IPC_GLB_GET_FW_CAPABILITIES = 5,        /* Retrieves firmware capabilities */
 116        IPC_GLB_STREAM_MESSAGE = 6,             /* Message directed to stream or its stages */
 117        /* Request to store firmware context during D0->D3 transition */
 118        IPC_GLB_REQUEST_DUMP = 7,
 119        /* Request to restore firmware context during D3->D0 transition */
 120        IPC_GLB_RESTORE_CONTEXT = 8,
 121        IPC_GLB_GET_DEVICE_FORMATS = 9,         /* Set device format */
 122        IPC_GLB_SET_DEVICE_FORMATS = 10,        /* Get device format */
 123        IPC_GLB_SHORT_REPLY = 11,
 124        IPC_GLB_ENTER_DX_STATE = 12,
 125        IPC_GLB_GET_MIXER_STREAM_INFO = 13,     /* Request mixer stream params */
 126        IPC_GLB_DEBUG_LOG_MESSAGE = 14,         /* Message to or from the debug logger. */
 127        IPC_GLB_MODULE_OPERATION = 15,          /* Message to loadable fw module */
 128        IPC_GLB_REQUEST_TRANSFER = 16,          /* < Request Transfer for host */
 129        IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17,      /* Maximum message number */
 130};
 131
 132enum ipc_glb_reply {
 133        IPC_GLB_REPLY_SUCCESS = 0,              /* The operation was successful. */
 134        IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1,  /* Invalid parameter was passed. */
 135        IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
 136        IPC_GLB_REPLY_OUT_OF_RESOURCES = 3,     /* No resources to satisfy the request. */
 137        IPC_GLB_REPLY_BUSY = 4,                 /* The system or resource is busy. */
 138        IPC_GLB_REPLY_PENDING = 5,              /* The action was scheduled for processing.  */
 139        IPC_GLB_REPLY_FAILURE = 6,              /* Critical error happened. */
 140        IPC_GLB_REPLY_INVALID_REQUEST = 7,      /* Request can not be completed. */
 141        IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8,  /* Processing stage was uninitialized. */
 142        IPC_GLB_REPLY_NOT_FOUND = 9,            /* Required resource can not be found. */
 143        IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10,  /* Source was not started. */
 144};
 145
 146enum ipc_module_operation {
 147        IPC_MODULE_NOTIFICATION = 0,
 148        IPC_MODULE_ENABLE = 1,
 149        IPC_MODULE_DISABLE = 2,
 150        IPC_MODULE_GET_PARAMETER = 3,
 151        IPC_MODULE_SET_PARAMETER = 4,
 152        IPC_MODULE_GET_INFO = 5,
 153        IPC_MODULE_MAX_MESSAGE
 154};
 155
 156/* Stream Message - Types */
 157enum ipc_str_operation {
 158        IPC_STR_RESET = 0,
 159        IPC_STR_PAUSE = 1,
 160        IPC_STR_RESUME = 2,
 161        IPC_STR_STAGE_MESSAGE = 3,
 162        IPC_STR_NOTIFICATION = 4,
 163        IPC_STR_MAX_MESSAGE
 164};
 165
 166/* Stream Stage Message Types */
 167enum ipc_stg_operation {
 168        IPC_STG_GET_VOLUME = 0,
 169        IPC_STG_SET_VOLUME,
 170        IPC_STG_SET_WRITE_POSITION,
 171        IPC_STG_SET_FX_ENABLE,
 172        IPC_STG_SET_FX_DISABLE,
 173        IPC_STG_SET_FX_GET_PARAM,
 174        IPC_STG_SET_FX_SET_PARAM,
 175        IPC_STG_SET_FX_GET_INFO,
 176        IPC_STG_MUTE_LOOPBACK,
 177        IPC_STG_MAX_MESSAGE
 178};
 179
 180/* Stream Stage Message Types For Notification*/
 181enum ipc_stg_operation_notify {
 182        IPC_POSITION_CHANGED = 0,
 183        IPC_STG_GLITCH,
 184        IPC_STG_MAX_NOTIFY
 185};
 186
 187enum ipc_glitch_type {
 188        IPC_GLITCH_UNDERRUN = 1,
 189        IPC_GLITCH_DECODER_ERROR,
 190        IPC_GLITCH_DOUBLED_WRITE_POS,
 191        IPC_GLITCH_MAX
 192};
 193
 194/* Debug Control */
 195enum ipc_debug_operation {
 196        IPC_DEBUG_ENABLE_LOG = 0,
 197        IPC_DEBUG_DISABLE_LOG = 1,
 198        IPC_DEBUG_REQUEST_LOG_DUMP = 2,
 199        IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
 200        IPC_DEBUG_MAX_DEBUG_LOG
 201};
 202
 203/* Firmware Ready */
 204struct sst_hsw_ipc_fw_ready {
 205        u32 inbox_offset;
 206        u32 outbox_offset;
 207        u32 inbox_size;
 208        u32 outbox_size;
 209        u32 fw_info_size;
 210        u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
 211} __attribute__((packed));
 212
 213struct sst_hsw_stream;
 214struct sst_hsw;
 215
 216/* Stream infomation */
 217struct sst_hsw_stream {
 218        /* configuration */
 219        struct sst_hsw_ipc_stream_alloc_req request;
 220        struct sst_hsw_ipc_stream_alloc_reply reply;
 221        struct sst_hsw_ipc_stream_free_req free_req;
 222
 223        /* Mixer info */
 224        u32 mute_volume[SST_HSW_NO_CHANNELS];
 225        u32 mute[SST_HSW_NO_CHANNELS];
 226
 227        /* runtime info */
 228        struct sst_hsw *hsw;
 229        int host_id;
 230        bool commited;
 231        bool running;
 232
 233        /* Notification work */
 234        struct work_struct notify_work;
 235        u32 header;
 236
 237        /* Position info from DSP */
 238        struct sst_hsw_ipc_stream_set_position wpos;
 239        struct sst_hsw_ipc_stream_get_position rpos;
 240        struct sst_hsw_ipc_stream_glitch_position glitch;
 241
 242        /* Volume info */
 243        struct sst_hsw_ipc_volume_req vol_req;
 244
 245        /* driver callback */
 246        u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
 247        void *pdata;
 248
 249        /* record the fw read position when playback */
 250        snd_pcm_uframes_t old_position;
 251        bool play_silence;
 252        struct list_head node;
 253};
 254
 255/* FW log ring information */
 256struct sst_hsw_log_stream {
 257        dma_addr_t dma_addr;
 258        unsigned char *dma_area;
 259        unsigned char *ring_descr;
 260        int pages;
 261        int size;
 262
 263        /* Notification work */
 264        struct work_struct notify_work;
 265        wait_queue_head_t readers_wait_q;
 266        struct mutex rw_mutex;
 267
 268        u32 last_pos;
 269        u32 curr_pos;
 270        u32 reader_pos;
 271
 272        /* fw log config */
 273        u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
 274
 275        struct sst_hsw *hsw;
 276};
 277
 278/* SST Haswell IPC data */
 279struct sst_hsw {
 280        struct device *dev;
 281        struct sst_dsp *dsp;
 282        struct platform_device *pdev_pcm;
 283
 284        /* FW config */
 285        struct sst_hsw_ipc_fw_ready fw_ready;
 286        struct sst_hsw_ipc_fw_version version;
 287        bool fw_done;
 288        struct sst_fw *sst_fw;
 289
 290        /* stream */
 291        struct list_head stream_list;
 292
 293        /* global mixer */
 294        struct sst_hsw_ipc_stream_info_reply mixer_info;
 295        enum sst_hsw_volume_curve curve_type;
 296        u32 curve_duration;
 297        u32 mute[SST_HSW_NO_CHANNELS];
 298        u32 mute_volume[SST_HSW_NO_CHANNELS];
 299
 300        /* DX */
 301        struct sst_hsw_ipc_dx_reply dx;
 302        void *dx_context;
 303        dma_addr_t dx_context_paddr;
 304        enum sst_hsw_device_id dx_dev;
 305        enum sst_hsw_device_mclk dx_mclk;
 306        enum sst_hsw_device_mode dx_mode;
 307        u32 dx_clock_divider;
 308
 309        /* boot */
 310        wait_queue_head_t boot_wait;
 311        bool boot_complete;
 312        bool shutdown;
 313
 314        /* IPC messaging */
 315        struct sst_generic_ipc ipc;
 316
 317        /* FW log stream */
 318        struct sst_hsw_log_stream log_stream;
 319
 320        /* flags bit field to track module state when resume from RTD3,
 321         * each bit represent state (enabled/disabled) of single module */
 322        u32 enabled_modules_rtd3;
 323
 324        /* buffer to store parameter lines */
 325        u32 param_idx_w;        /* write index */
 326        u32 param_idx_r;        /* read index */
 327        u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
 328};
 329
 330#define CREATE_TRACE_POINTS
 331#include <trace/events/hswadsp.h>
 332
 333static inline u32 msg_get_global_type(u32 msg)
 334{
 335        return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
 336}
 337
 338static inline u32 msg_get_global_reply(u32 msg)
 339{
 340        return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
 341}
 342
 343static inline u32 msg_get_stream_type(u32 msg)
 344{
 345        return (msg & IPC_STR_TYPE_MASK) >>  IPC_STR_TYPE_SHIFT;
 346}
 347
 348static inline u32 msg_get_stage_type(u32 msg)
 349{
 350        return (msg & IPC_STG_TYPE_MASK) >>  IPC_STG_TYPE_SHIFT;
 351}
 352
 353static inline u32 msg_get_stream_id(u32 msg)
 354{
 355        return (msg & IPC_STR_ID_MASK) >>  IPC_STR_ID_SHIFT;
 356}
 357
 358static inline u32 msg_get_notify_reason(u32 msg)
 359{
 360        return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
 361}
 362
 363static inline u32 msg_get_module_operation(u32 msg)
 364{
 365        return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
 366}
 367
 368static inline u32 msg_get_module_id(u32 msg)
 369{
 370        return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
 371}
 372
 373u32 create_channel_map(enum sst_hsw_channel_config config)
 374{
 375        switch (config) {
 376        case SST_HSW_CHANNEL_CONFIG_MONO:
 377                return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
 378        case SST_HSW_CHANNEL_CONFIG_STEREO:
 379                return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
 380                        | (SST_HSW_CHANNEL_RIGHT << 4));
 381        case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
 382                return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
 383                        | (SST_HSW_CHANNEL_RIGHT << 4)
 384                        | (SST_HSW_CHANNEL_LFE << 8 ));
 385        case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
 386                return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
 387                        | (SST_HSW_CHANNEL_CENTER << 4)
 388                        | (SST_HSW_CHANNEL_RIGHT << 8));
 389        case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
 390                return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 391                        | (SST_HSW_CHANNEL_CENTER << 4)
 392                        | (SST_HSW_CHANNEL_RIGHT << 8)
 393                        | (SST_HSW_CHANNEL_LFE << 12));
 394        case SST_HSW_CHANNEL_CONFIG_QUATRO:
 395                return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 396                        | (SST_HSW_CHANNEL_RIGHT << 4)
 397                        | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
 398                        | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
 399        case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
 400                return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 401                        | (SST_HSW_CHANNEL_CENTER << 4)
 402                        | (SST_HSW_CHANNEL_RIGHT << 8)
 403                        | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
 404        case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
 405                return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
 406                        | (SST_HSW_CHANNEL_CENTER << 4)
 407                        | (SST_HSW_CHANNEL_RIGHT << 8)
 408                        | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
 409                        | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
 410        case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
 411                return (0xFF000000 | SST_HSW_CHANNEL_CENTER
 412                        | (SST_HSW_CHANNEL_LEFT << 4)
 413                        | (SST_HSW_CHANNEL_RIGHT << 8)
 414                        | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
 415                        | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
 416                        | (SST_HSW_CHANNEL_LFE << 20));
 417        case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
 418                return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
 419                        | (SST_HSW_CHANNEL_LEFT << 4));
 420        default:
 421                return 0xFFFFFFFF;
 422        }
 423}
 424
 425static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
 426        int stream_id)
 427{
 428        struct sst_hsw_stream *stream;
 429
 430        list_for_each_entry(stream, &hsw->stream_list, node) {
 431                if (stream->reply.stream_hw_id == stream_id)
 432                        return stream;
 433        }
 434
 435        return NULL;
 436}
 437
 438static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
 439{
 440        struct sst_hsw_ipc_fw_ready fw_ready;
 441        u32 offset;
 442        u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
 443        char *tmp[5], *pinfo;
 444        int i = 0;
 445
 446        offset = (header & 0x1FFFFFFF) << 3;
 447
 448        dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
 449                header, offset);
 450
 451        /* copy data from the DSP FW ready offset */
 452        sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
 453
 454        sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
 455                fw_ready.inbox_size, fw_ready.outbox_offset,
 456                fw_ready.outbox_size);
 457
 458        hsw->boot_complete = true;
 459        wake_up(&hsw->boot_wait);
 460
 461        dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
 462                fw_ready.inbox_offset, fw_ready.inbox_size);
 463        dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
 464                fw_ready.outbox_offset, fw_ready.outbox_size);
 465        if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
 466                fw_ready.fw_info[fw_ready.fw_info_size] = 0;
 467                dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
 468
 469                /* log the FW version info got from the mailbox here. */
 470                memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
 471                pinfo = &fw_info[0];
 472                for (i = 0; i < ARRAY_SIZE(tmp); i++)
 473                        tmp[i] = strsep(&pinfo, " ");
 474                dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
 475                        "version: %s.%s, build %s, source commit id: %s\n",
 476                        tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
 477        }
 478}
 479
 480static void hsw_notification_work(struct work_struct *work)
 481{
 482        struct sst_hsw_stream *stream = container_of(work,
 483                        struct sst_hsw_stream, notify_work);
 484        struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
 485        struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
 486        struct sst_hsw *hsw = stream->hsw;
 487        u32 reason;
 488
 489        reason = msg_get_notify_reason(stream->header);
 490
 491        switch (reason) {
 492        case IPC_STG_GLITCH:
 493                trace_ipc_notification("DSP stream under/overrun",
 494                        stream->reply.stream_hw_id);
 495                sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
 496
 497                dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
 498                        glitch->glitch_type, glitch->present_pos,
 499                        glitch->write_pos);
 500                break;
 501
 502        case IPC_POSITION_CHANGED:
 503                trace_ipc_notification("DSP stream position changed for",
 504                        stream->reply.stream_hw_id);
 505                sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
 506
 507                if (stream->notify_position)
 508                        stream->notify_position(stream, stream->pdata);
 509
 510                break;
 511        default:
 512                dev_err(hsw->dev, "error: unknown notification 0x%x\n",
 513                        stream->header);
 514                break;
 515        }
 516
 517        /* tell DSP that notification has been handled */
 518        sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
 519                SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
 520
 521        /* unmask busy interrupt */
 522        sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
 523}
 524
 525static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
 526{
 527        struct sst_hsw_stream *stream;
 528        u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
 529        u32 stream_id = msg_get_stream_id(header);
 530        u32 stream_msg = msg_get_stream_type(header);
 531
 532        stream = get_stream_by_id(hsw, stream_id);
 533        if (stream == NULL)
 534                return;
 535
 536        switch (stream_msg) {
 537        case IPC_STR_STAGE_MESSAGE:
 538        case IPC_STR_NOTIFICATION:
 539                break;
 540        case IPC_STR_RESET:
 541                trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
 542                break;
 543        case IPC_STR_PAUSE:
 544                stream->running = false;
 545                trace_ipc_notification("stream paused",
 546                        stream->reply.stream_hw_id);
 547                break;
 548        case IPC_STR_RESUME:
 549                stream->running = true;
 550                trace_ipc_notification("stream running",
 551                        stream->reply.stream_hw_id);
 552                break;
 553        }
 554}
 555
 556static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
 557{
 558        struct ipc_message *msg;
 559        u32 reply = msg_get_global_reply(header);
 560
 561        trace_ipc_reply("processing -->", header);
 562
 563        msg = sst_ipc_reply_find_msg(&hsw->ipc, header);
 564        if (msg == NULL) {
 565                trace_ipc_error("error: can't find message header", header);
 566                return -EIO;
 567        }
 568
 569        /* first process the header */
 570        switch (reply) {
 571        case IPC_GLB_REPLY_PENDING:
 572                trace_ipc_pending_reply("received", header);
 573                msg->pending = true;
 574                hsw->ipc.pending = true;
 575                return 1;
 576        case IPC_GLB_REPLY_SUCCESS:
 577                if (msg->pending) {
 578                        trace_ipc_pending_reply("completed", header);
 579                        sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
 580                                msg->rx_size);
 581                        hsw->ipc.pending = false;
 582                } else {
 583                        /* copy data from the DSP */
 584                        sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
 585                                msg->rx_size);
 586                }
 587                break;
 588        /* these will be rare - but useful for debug */
 589        case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
 590                trace_ipc_error("error: unknown message type", header);
 591                msg->errno = -EBADMSG;
 592                break;
 593        case IPC_GLB_REPLY_OUT_OF_RESOURCES:
 594                trace_ipc_error("error: out of resources", header);
 595                msg->errno = -ENOMEM;
 596                break;
 597        case IPC_GLB_REPLY_BUSY:
 598                trace_ipc_error("error: reply busy", header);
 599                msg->errno = -EBUSY;
 600                break;
 601        case IPC_GLB_REPLY_FAILURE:
 602                trace_ipc_error("error: reply failure", header);
 603                msg->errno = -EINVAL;
 604                break;
 605        case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
 606                trace_ipc_error("error: stage uninitialized", header);
 607                msg->errno = -EINVAL;
 608                break;
 609        case IPC_GLB_REPLY_NOT_FOUND:
 610                trace_ipc_error("error: reply not found", header);
 611                msg->errno = -EINVAL;
 612                break;
 613        case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
 614                trace_ipc_error("error: source not started", header);
 615                msg->errno = -EINVAL;
 616                break;
 617        case IPC_GLB_REPLY_INVALID_REQUEST:
 618                trace_ipc_error("error: invalid request", header);
 619                msg->errno = -EINVAL;
 620                break;
 621        case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
 622                trace_ipc_error("error: invalid parameter", header);
 623                msg->errno = -EINVAL;
 624                break;
 625        default:
 626                trace_ipc_error("error: unknown reply", header);
 627                msg->errno = -EINVAL;
 628                break;
 629        }
 630
 631        /* update any stream states */
 632        if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
 633                hsw_stream_update(hsw, msg);
 634
 635        /* wake up and return the error if we have waiters on this message ? */
 636        list_del(&msg->list);
 637        sst_ipc_tx_msg_reply_complete(&hsw->ipc, msg);
 638
 639        return 1;
 640}
 641
 642static int hsw_module_message(struct sst_hsw *hsw, u32 header)
 643{
 644        u32 operation, module_id;
 645        int handled = 0;
 646
 647        operation = msg_get_module_operation(header);
 648        module_id = msg_get_module_id(header);
 649        dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
 650                        header);
 651        dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
 652                        operation, module_id);
 653
 654        switch (operation) {
 655        case IPC_MODULE_NOTIFICATION:
 656                dev_dbg(hsw->dev, "module notification received");
 657                handled = 1;
 658                break;
 659        default:
 660                handled = hsw_process_reply(hsw, header);
 661                break;
 662        }
 663
 664        return handled;
 665}
 666
 667static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
 668{
 669        u32 stream_msg, stream_id, stage_type;
 670        struct sst_hsw_stream *stream;
 671        int handled = 0;
 672
 673        stream_msg = msg_get_stream_type(header);
 674        stream_id = msg_get_stream_id(header);
 675        stage_type = msg_get_stage_type(header);
 676
 677        stream = get_stream_by_id(hsw, stream_id);
 678        if (stream == NULL)
 679                return handled;
 680
 681        stream->header = header;
 682
 683        switch (stream_msg) {
 684        case IPC_STR_STAGE_MESSAGE:
 685                dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
 686                        header);
 687                break;
 688        case IPC_STR_NOTIFICATION:
 689                schedule_work(&stream->notify_work);
 690                break;
 691        default:
 692                /* handle pending message complete request */
 693                handled = hsw_process_reply(hsw, header);
 694                break;
 695        }
 696
 697        return handled;
 698}
 699
 700static int hsw_log_message(struct sst_hsw *hsw, u32 header)
 701{
 702        u32 operation = (header & IPC_LOG_OP_MASK) >>  IPC_LOG_OP_SHIFT;
 703        struct sst_hsw_log_stream *stream = &hsw->log_stream;
 704        int ret = 1;
 705
 706        if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
 707                dev_err(hsw->dev,
 708                        "error: log msg not implemented 0x%8.8x\n", header);
 709                return 0;
 710        }
 711
 712        mutex_lock(&stream->rw_mutex);
 713        stream->last_pos = stream->curr_pos;
 714        sst_dsp_inbox_read(
 715                hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
 716        mutex_unlock(&stream->rw_mutex);
 717
 718        schedule_work(&stream->notify_work);
 719
 720        return ret;
 721}
 722
 723static int hsw_process_notification(struct sst_hsw *hsw)
 724{
 725        struct sst_dsp *sst = hsw->dsp;
 726        u32 type, header;
 727        int handled = 1;
 728
 729        header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
 730        type = msg_get_global_type(header);
 731
 732        trace_ipc_request("processing -->", header);
 733
 734        /* FW Ready is a special case */
 735        if (!hsw->boot_complete && header & IPC_FW_READY) {
 736                hsw_fw_ready(hsw, header);
 737                return handled;
 738        }
 739
 740        switch (type) {
 741        case IPC_GLB_GET_FW_VERSION:
 742        case IPC_GLB_ALLOCATE_STREAM:
 743        case IPC_GLB_FREE_STREAM:
 744        case IPC_GLB_GET_FW_CAPABILITIES:
 745        case IPC_GLB_REQUEST_DUMP:
 746        case IPC_GLB_GET_DEVICE_FORMATS:
 747        case IPC_GLB_SET_DEVICE_FORMATS:
 748        case IPC_GLB_ENTER_DX_STATE:
 749        case IPC_GLB_GET_MIXER_STREAM_INFO:
 750        case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
 751        case IPC_GLB_RESTORE_CONTEXT:
 752        case IPC_GLB_SHORT_REPLY:
 753                dev_err(hsw->dev, "error: message type %d header 0x%x\n",
 754                        type, header);
 755                break;
 756        case IPC_GLB_STREAM_MESSAGE:
 757                handled = hsw_stream_message(hsw, header);
 758                break;
 759        case IPC_GLB_DEBUG_LOG_MESSAGE:
 760                handled = hsw_log_message(hsw, header);
 761                break;
 762        case IPC_GLB_MODULE_OPERATION:
 763                handled = hsw_module_message(hsw, header);
 764                break;
 765        default:
 766                dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
 767                        type, header);
 768                break;
 769        }
 770
 771        return handled;
 772}
 773
 774static irqreturn_t hsw_irq_thread(int irq, void *context)
 775{
 776        struct sst_dsp *sst = (struct sst_dsp *) context;
 777        struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
 778        struct sst_generic_ipc *ipc = &hsw->ipc;
 779        u32 ipcx, ipcd;
 780        unsigned long flags;
 781
 782        spin_lock_irqsave(&sst->spinlock, flags);
 783
 784        ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
 785        ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
 786
 787        /* reply message from DSP */
 788        if (ipcx & SST_IPCX_DONE) {
 789
 790                /* Handle Immediate reply from DSP Core */
 791                hsw_process_reply(hsw, ipcx);
 792
 793                /* clear DONE bit - tell DSP we have completed */
 794                sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
 795                        SST_IPCX_DONE, 0);
 796
 797                /* unmask Done interrupt */
 798                sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 799                        SST_IMRX_DONE, 0);
 800        }
 801
 802        /* new message from DSP */
 803        if (ipcd & SST_IPCD_BUSY) {
 804
 805                /* Handle Notification and Delayed reply from DSP Core */
 806                hsw_process_notification(hsw);
 807
 808                /* clear BUSY bit and set DONE bit - accept new messages */
 809                sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
 810                        SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
 811
 812                /* unmask busy interrupt */
 813                sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 814                        SST_IMRX_BUSY, 0);
 815        }
 816
 817        spin_unlock_irqrestore(&sst->spinlock, flags);
 818
 819        /* continue to send any remaining messages... */
 820        schedule_work(&ipc->kwork);
 821
 822        return IRQ_HANDLED;
 823}
 824
 825int sst_hsw_fw_get_version(struct sst_hsw *hsw,
 826        struct sst_hsw_ipc_fw_version *version)
 827{
 828        int ret;
 829
 830        ret = sst_ipc_tx_message_wait(&hsw->ipc,
 831                IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
 832                NULL, 0, version, sizeof(*version));
 833        if (ret < 0)
 834                dev_err(hsw->dev, "error: get version failed\n");
 835
 836        return ret;
 837}
 838
 839/* Mixer Controls */
 840int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 841        u32 stage_id, u32 channel, u32 *volume)
 842{
 843        if (channel > 1)
 844                return -EINVAL;
 845
 846        sst_dsp_read(hsw->dsp, volume,
 847                stream->reply.volume_register_address[channel],
 848                sizeof(*volume));
 849
 850        return 0;
 851}
 852
 853/* stream volume */
 854int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
 855        struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
 856{
 857        struct sst_hsw_ipc_volume_req *req;
 858        u32 header;
 859        int ret;
 860
 861        trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
 862
 863        if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
 864                return -EINVAL;
 865
 866        header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
 867                IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
 868        header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
 869        header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
 870        header |= (stage_id << IPC_STG_ID_SHIFT);
 871
 872        req = &stream->vol_req;
 873        req->target_volume = volume;
 874
 875        /* set both at same time ? */
 876        if (channel == SST_HSW_CHANNELS_ALL) {
 877                if (hsw->mute[0] && hsw->mute[1]) {
 878                        hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
 879                        return 0;
 880                } else if (hsw->mute[0])
 881                        req->channel = 1;
 882                else if (hsw->mute[1])
 883                        req->channel = 0;
 884                else
 885                        req->channel = SST_HSW_CHANNELS_ALL;
 886        } else {
 887                /* set only 1 channel */
 888                if (hsw->mute[channel]) {
 889                        hsw->mute_volume[channel] = volume;
 890                        return 0;
 891                }
 892                req->channel = channel;
 893        }
 894
 895        ret = sst_ipc_tx_message_wait(&hsw->ipc, header, req,
 896                sizeof(*req), NULL, 0);
 897        if (ret < 0) {
 898                dev_err(hsw->dev, "error: set stream volume failed\n");
 899                return ret;
 900        }
 901
 902        return 0;
 903}
 904
 905int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
 906        u32 *volume)
 907{
 908        if (channel > 1)
 909                return -EINVAL;
 910
 911        sst_dsp_read(hsw->dsp, volume,
 912                hsw->mixer_info.volume_register_address[channel],
 913                sizeof(*volume));
 914
 915        return 0;
 916}
 917
 918/* global mixer volume */
 919int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
 920        u32 volume)
 921{
 922        struct sst_hsw_ipc_volume_req req;
 923        u32 header;
 924        int ret;
 925
 926        trace_ipc_request("set mixer volume", volume);
 927
 928        if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
 929                return -EINVAL;
 930
 931        /* set both at same time ? */
 932        if (channel == SST_HSW_CHANNELS_ALL) {
 933                if (hsw->mute[0] && hsw->mute[1]) {
 934                        hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
 935                        return 0;
 936                } else if (hsw->mute[0])
 937                        req.channel = 1;
 938                else if (hsw->mute[1])
 939                        req.channel = 0;
 940                else
 941                        req.channel = SST_HSW_CHANNELS_ALL;
 942        } else {
 943                /* set only 1 channel */
 944                if (hsw->mute[channel]) {
 945                        hsw->mute_volume[channel] = volume;
 946                        return 0;
 947                }
 948                req.channel = channel;
 949        }
 950
 951        header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
 952                IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
 953        header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
 954        header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
 955        header |= (stage_id << IPC_STG_ID_SHIFT);
 956
 957        req.curve_duration = hsw->curve_duration;
 958        req.curve_type = hsw->curve_type;
 959        req.target_volume = volume;
 960
 961        ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &req,
 962                sizeof(req), NULL, 0);
 963        if (ret < 0) {
 964                dev_err(hsw->dev, "error: set mixer volume failed\n");
 965                return ret;
 966        }
 967
 968        return 0;
 969}
 970
 971/* Stream API */
 972struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
 973        u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
 974        void *data)
 975{
 976        struct sst_hsw_stream *stream;
 977        struct sst_dsp *sst = hsw->dsp;
 978        unsigned long flags;
 979
 980        stream = kzalloc(sizeof(*stream), GFP_KERNEL);
 981        if (stream == NULL)
 982                return NULL;
 983
 984        spin_lock_irqsave(&sst->spinlock, flags);
 985        stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
 986        list_add(&stream->node, &hsw->stream_list);
 987        stream->notify_position = notify_position;
 988        stream->pdata = data;
 989        stream->hsw = hsw;
 990        stream->host_id = id;
 991
 992        /* work to process notification messages */
 993        INIT_WORK(&stream->notify_work, hsw_notification_work);
 994        spin_unlock_irqrestore(&sst->spinlock, flags);
 995
 996        return stream;
 997}
 998
 999int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1000{
1001        u32 header;
1002        int ret = 0;
1003        struct sst_dsp *sst = hsw->dsp;
1004        unsigned long flags;
1005
1006        if (!stream) {
1007                dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
1008                return 0;
1009        }
1010
1011        /* dont free DSP streams that are not commited */
1012        if (!stream->commited)
1013                goto out;
1014
1015        trace_ipc_request("stream free", stream->host_id);
1016
1017        stream->free_req.stream_id = stream->reply.stream_hw_id;
1018        header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1019
1020        ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &stream->free_req,
1021                sizeof(stream->free_req), NULL, 0);
1022        if (ret < 0) {
1023                dev_err(hsw->dev, "error: free stream %d failed\n",
1024                        stream->free_req.stream_id);
1025                return -EAGAIN;
1026        }
1027
1028        trace_hsw_stream_free_req(stream, &stream->free_req);
1029
1030out:
1031        cancel_work_sync(&stream->notify_work);
1032        spin_lock_irqsave(&sst->spinlock, flags);
1033        list_del(&stream->node);
1034        kfree(stream);
1035        spin_unlock_irqrestore(&sst->spinlock, flags);
1036
1037        return ret;
1038}
1039
1040int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1041        struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1042{
1043        if (stream->commited) {
1044                dev_err(hsw->dev, "error: stream committed for set bits\n");
1045                return -EINVAL;
1046        }
1047
1048        stream->request.format.bitdepth = bits;
1049        return 0;
1050}
1051
1052int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1053        struct sst_hsw_stream *stream, int channels)
1054{
1055        if (stream->commited) {
1056                dev_err(hsw->dev, "error: stream committed for set channels\n");
1057                return -EINVAL;
1058        }
1059
1060        stream->request.format.ch_num = channels;
1061        return 0;
1062}
1063
1064int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1065        struct sst_hsw_stream *stream, int rate)
1066{
1067        if (stream->commited) {
1068                dev_err(hsw->dev, "error: stream committed for set rate\n");
1069                return -EINVAL;
1070        }
1071
1072        stream->request.format.frequency = rate;
1073        return 0;
1074}
1075
1076int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1077        struct sst_hsw_stream *stream, u32 map,
1078        enum sst_hsw_channel_config config)
1079{
1080        if (stream->commited) {
1081                dev_err(hsw->dev, "error: stream committed for set map\n");
1082                return -EINVAL;
1083        }
1084
1085        stream->request.format.map = map;
1086        stream->request.format.config = config;
1087        return 0;
1088}
1089
1090int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1091        struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1092{
1093        if (stream->commited) {
1094                dev_err(hsw->dev, "error: stream committed for set style\n");
1095                return -EINVAL;
1096        }
1097
1098        stream->request.format.style = style;
1099        return 0;
1100}
1101
1102int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1103        struct sst_hsw_stream *stream, u32 bits)
1104{
1105        if (stream->commited) {
1106                dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1107                return -EINVAL;
1108        }
1109
1110        stream->request.format.valid_bit = bits;
1111        return 0;
1112}
1113
1114/* Stream Configuration */
1115int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1116        enum sst_hsw_stream_path_id path_id,
1117        enum sst_hsw_stream_type stream_type,
1118        enum sst_hsw_stream_format format_id)
1119{
1120        if (stream->commited) {
1121                dev_err(hsw->dev, "error: stream committed for set format\n");
1122                return -EINVAL;
1123        }
1124
1125        stream->request.path_id = path_id;
1126        stream->request.stream_type = stream_type;
1127        stream->request.format_id = format_id;
1128
1129        trace_hsw_stream_alloc_request(stream, &stream->request);
1130
1131        return 0;
1132}
1133
1134int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1135        u32 ring_pt_address, u32 num_pages,
1136        u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1137{
1138        if (stream->commited) {
1139                dev_err(hsw->dev, "error: stream committed for buffer\n");
1140                return -EINVAL;
1141        }
1142
1143        stream->request.ringinfo.ring_pt_address = ring_pt_address;
1144        stream->request.ringinfo.num_pages = num_pages;
1145        stream->request.ringinfo.ring_size = ring_size;
1146        stream->request.ringinfo.ring_offset = ring_offset;
1147        stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1148
1149        trace_hsw_stream_buffer(stream);
1150
1151        return 0;
1152}
1153
1154int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1155        struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
1156{
1157        struct sst_hsw_module_map *map = &stream->request.map;
1158        struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1159        struct sst_module *module = runtime->module;
1160
1161        if (stream->commited) {
1162                dev_err(hsw->dev, "error: stream committed for set module\n");
1163                return -EINVAL;
1164        }
1165
1166        /* only support initial module atm */
1167        map->module_entries_count = 1;
1168        map->module_entries[0].module_id = module->id;
1169        map->module_entries[0].entry_point = module->entry;
1170
1171        stream->request.persistent_mem.offset =
1172                sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1173        stream->request.persistent_mem.size = module->persistent_size;
1174
1175        stream->request.scratch_mem.offset =
1176                sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1177        stream->request.scratch_mem.size = dsp->scratch_size;
1178
1179        dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1180                runtime->id);
1181        dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1182                stream->request.persistent_mem.offset,
1183                stream->request.persistent_mem.size);
1184        dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1185                stream->request.scratch_mem.offset,
1186                stream->request.scratch_mem.size);
1187
1188        return 0;
1189}
1190
1191int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1192{
1193        struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1194        struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1195        u32 header;
1196        int ret;
1197
1198        if (!stream) {
1199                dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1200                return 0;
1201        }
1202
1203        if (stream->commited) {
1204                dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1205                return 0;
1206        }
1207
1208        trace_ipc_request("stream alloc", stream->host_id);
1209
1210        header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1211
1212        ret = sst_ipc_tx_message_wait(&hsw->ipc, header, str_req,
1213                sizeof(*str_req), reply, sizeof(*reply));
1214        if (ret < 0) {
1215                dev_err(hsw->dev, "error: stream commit failed\n");
1216                return ret;
1217        }
1218
1219        stream->commited = 1;
1220        trace_hsw_stream_alloc_reply(stream);
1221
1222        return 0;
1223}
1224
1225snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
1226        struct sst_hsw_stream *stream)
1227{
1228        return stream->old_position;
1229}
1230
1231void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
1232        struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
1233{
1234        stream->old_position = val;
1235}
1236
1237bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
1238        struct sst_hsw_stream *stream)
1239{
1240        return stream->play_silence;
1241}
1242
1243void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
1244        struct sst_hsw_stream *stream, bool val)
1245{
1246        stream->play_silence = val;
1247}
1248
1249/* Stream Information - these calls could be inline but we want the IPC
1250 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1251int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1252{
1253        struct sst_hsw_ipc_stream_info_reply *reply;
1254        u32 header;
1255        int ret;
1256
1257        reply = &hsw->mixer_info;
1258        header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1259
1260        trace_ipc_request("get global mixer info", 0);
1261
1262        ret = sst_ipc_tx_message_wait(&hsw->ipc, header, NULL, 0,
1263                reply, sizeof(*reply));
1264        if (ret < 0) {
1265                dev_err(hsw->dev, "error: get stream info failed\n");
1266                return ret;
1267        }
1268
1269        trace_hsw_mixer_info_reply(reply);
1270
1271        return 0;
1272}
1273
1274/* Send stream command */
1275static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1276        int stream_id, int wait)
1277{
1278        u32 header;
1279
1280        header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1281        header |= (stream_id << IPC_STR_ID_SHIFT);
1282
1283        if (wait)
1284                return sst_ipc_tx_message_wait(&hsw->ipc, header,
1285                        NULL, 0, NULL, 0);
1286        else
1287                return sst_ipc_tx_message_nowait(&hsw->ipc, header, NULL, 0);
1288}
1289
1290/* Stream ALSA trigger operations */
1291int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1292        int wait)
1293{
1294        int ret;
1295
1296        if (!stream) {
1297                dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1298                return 0;
1299        }
1300
1301        trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1302
1303        ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1304                stream->reply.stream_hw_id, wait);
1305        if (ret < 0)
1306                dev_err(hsw->dev, "error: failed to pause stream %d\n",
1307                        stream->reply.stream_hw_id);
1308
1309        return ret;
1310}
1311
1312int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1313        int wait)
1314{
1315        int ret;
1316
1317        if (!stream) {
1318                dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1319                return 0;
1320        }
1321
1322        trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1323
1324        ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1325                stream->reply.stream_hw_id, wait);
1326        if (ret < 0)
1327                dev_err(hsw->dev, "error: failed to resume stream %d\n",
1328                        stream->reply.stream_hw_id);
1329
1330        return ret;
1331}
1332
1333int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1334{
1335        int ret, tries = 10;
1336
1337        if (!stream) {
1338                dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1339                return 0;
1340        }
1341
1342        /* dont reset streams that are not commited */
1343        if (!stream->commited)
1344                return 0;
1345
1346        /* wait for pause to complete before we reset the stream */
1347        while (stream->running && --tries)
1348                msleep(1);
1349        if (!tries) {
1350                dev_err(hsw->dev, "error: reset stream %d still running\n",
1351                        stream->reply.stream_hw_id);
1352                return -EINVAL;
1353        }
1354
1355        trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1356
1357        ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1358                stream->reply.stream_hw_id, 1);
1359        if (ret < 0)
1360                dev_err(hsw->dev, "error: failed to reset stream %d\n",
1361                        stream->reply.stream_hw_id);
1362        return ret;
1363}
1364
1365/* Stream pointer positions */
1366u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
1367        struct sst_hsw_stream *stream)
1368{
1369        u32 rpos;
1370
1371        sst_dsp_read(hsw->dsp, &rpos,
1372                stream->reply.read_position_register_address, sizeof(rpos));
1373
1374        return rpos;
1375}
1376
1377/* Stream presentation (monotonic) positions */
1378u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1379        struct sst_hsw_stream *stream)
1380{
1381        u64 ppos;
1382
1383        sst_dsp_read(hsw->dsp, &ppos,
1384                stream->reply.presentation_position_register_address,
1385                sizeof(ppos));
1386
1387        return ppos;
1388}
1389
1390/* physical BE config */
1391int sst_hsw_device_set_config(struct sst_hsw *hsw,
1392        enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1393        enum sst_hsw_device_mode mode, u32 clock_divider)
1394{
1395        struct sst_hsw_ipc_device_config_req config;
1396        u32 header;
1397        int ret;
1398
1399        trace_ipc_request("set device config", dev);
1400
1401        hsw->dx_dev = config.ssp_interface = dev;
1402        hsw->dx_mclk = config.clock_frequency = mclk;
1403        hsw->dx_mode = config.mode = mode;
1404        hsw->dx_clock_divider = config.clock_divider = clock_divider;
1405        if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1406                config.channels = 4;
1407        else
1408                config.channels = 2;
1409
1410        trace_hsw_device_config_req(&config);
1411
1412        header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1413
1414        ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &config,
1415                sizeof(config), NULL, 0);
1416        if (ret < 0)
1417                dev_err(hsw->dev, "error: set device formats failed\n");
1418
1419        return ret;
1420}
1421EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1422
1423/* DX Config */
1424int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1425        enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1426{
1427        u32 header, state_;
1428        int ret, item;
1429
1430        header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1431        state_ = state;
1432
1433        trace_ipc_request("PM enter Dx state", state);
1434
1435        ret = sst_ipc_tx_message_wait(&hsw->ipc, header, &state_,
1436                sizeof(state_), dx, sizeof(*dx));
1437        if (ret < 0) {
1438                dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1439                return ret;
1440        }
1441
1442        for (item = 0; item < dx->entries_no; item++) {
1443                dev_dbg(hsw->dev,
1444                        "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1445                        item, dx->mem_info[item].offset,
1446                        dx->mem_info[item].size,
1447                        dx->mem_info[item].source);
1448        }
1449        dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1450                dx->entries_no, state);
1451
1452        return ret;
1453}
1454
1455struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1456        int mod_id, int offset)
1457{
1458        struct sst_dsp *dsp = hsw->dsp;
1459        struct sst_module *module;
1460        struct sst_module_runtime *runtime;
1461        int err;
1462
1463        module = sst_module_get_from_id(dsp, mod_id);
1464        if (module == NULL) {
1465                dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1466                        mod_id);
1467                return NULL;
1468        }
1469
1470        runtime = sst_module_runtime_new(module, mod_id, NULL);
1471        if (runtime == NULL) {
1472                dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1473                        mod_id);
1474                return NULL;
1475        }
1476
1477        err = sst_module_runtime_alloc_blocks(runtime, offset);
1478        if (err < 0) {
1479                dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1480                        mod_id);
1481                sst_module_runtime_free(runtime);
1482                return NULL;
1483        }
1484
1485        dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1486                mod_id);
1487        return runtime;
1488}
1489
1490void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1491{
1492        sst_module_runtime_free_blocks(runtime);
1493        sst_module_runtime_free(runtime);
1494}
1495
1496#ifdef CONFIG_PM
1497static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1498{
1499        struct sst_dsp *sst = hsw->dsp;
1500        u32 item, offset, size;
1501        int ret = 0;
1502
1503        trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1504
1505        if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1506                dev_err(hsw->dev,
1507                        "error: number of FW context regions greater than %d\n",
1508                        SST_HSW_MAX_DX_REGIONS);
1509                memset(&hsw->dx, 0, sizeof(hsw->dx));
1510                return -EINVAL;
1511        }
1512
1513        ret = sst_dsp_dma_get_channel(sst, 0);
1514        if (ret < 0) {
1515                dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1516                return ret;
1517        }
1518
1519        /* set on-demond mode on engine 0 channel 3 */
1520        sst_dsp_shim_update_bits(sst, SST_HMDC,
1521                        SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1522                        SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1523
1524        for (item = 0; item < hsw->dx.entries_no; item++) {
1525                if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1526                        && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1527                        && hsw->dx.mem_info[item].offset <
1528                        DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1529
1530                        offset = hsw->dx.mem_info[item].offset
1531                                        - DSP_DRAM_ADDR_OFFSET;
1532                        size = (hsw->dx.mem_info[item].size + 3) & (~3);
1533
1534                        ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1535                                sst->addr.lpe_base + offset, size);
1536                        if (ret < 0) {
1537                                dev_err(hsw->dev,
1538                                        "error: FW context dump failed\n");
1539                                memset(&hsw->dx, 0, sizeof(hsw->dx));
1540                                goto out;
1541                        }
1542                }
1543        }
1544
1545out:
1546        sst_dsp_dma_put_channel(sst);
1547        return ret;
1548}
1549
1550static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1551{
1552        struct sst_dsp *sst = hsw->dsp;
1553        u32 item, offset, size;
1554        int ret;
1555
1556        for (item = 0; item < hsw->dx.entries_no; item++) {
1557                if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1558                        && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1559                        && hsw->dx.mem_info[item].offset <
1560                        DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1561
1562                        offset = hsw->dx.mem_info[item].offset
1563                                        - DSP_DRAM_ADDR_OFFSET;
1564                        size = (hsw->dx.mem_info[item].size + 3) & (~3);
1565
1566                        ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1567                                hsw->dx_context_paddr + offset, size);
1568                        if (ret < 0) {
1569                                dev_err(hsw->dev,
1570                                        "error: FW context restore failed\n");
1571                                return ret;
1572                        }
1573                }
1574        }
1575
1576        return 0;
1577}
1578
1579int sst_hsw_dsp_load(struct sst_hsw *hsw)
1580{
1581        struct sst_dsp *dsp = hsw->dsp;
1582        struct sst_fw *sst_fw, *t;
1583        int ret;
1584
1585        dev_dbg(hsw->dev, "loading audio DSP....");
1586
1587        ret = sst_dsp_wake(dsp);
1588        if (ret < 0) {
1589                dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1590                return -ENODEV;
1591        }
1592
1593        ret = sst_dsp_dma_get_channel(dsp, 0);
1594        if (ret < 0) {
1595                dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1596                return ret;
1597        }
1598
1599        list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
1600                ret = sst_fw_reload(sst_fw);
1601                if (ret < 0) {
1602                        dev_err(hsw->dev, "error: SST FW reload failed\n");
1603                        sst_dsp_dma_put_channel(dsp);
1604                        return -ENOMEM;
1605                }
1606        }
1607        ret = sst_block_alloc_scratch(hsw->dsp);
1608        if (ret < 0)
1609                return -EINVAL;
1610
1611        sst_dsp_dma_put_channel(dsp);
1612        return 0;
1613}
1614
1615static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1616{
1617        struct sst_dsp *dsp = hsw->dsp;
1618        int ret;
1619
1620        dev_dbg(hsw->dev, "restoring audio DSP....");
1621
1622        ret = sst_dsp_dma_get_channel(dsp, 0);
1623        if (ret < 0) {
1624                dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1625                return ret;
1626        }
1627
1628        ret = sst_hsw_dx_state_restore(hsw);
1629        if (ret < 0) {
1630                dev_err(hsw->dev, "error: SST FW context restore failed\n");
1631                sst_dsp_dma_put_channel(dsp);
1632                return -ENOMEM;
1633        }
1634        sst_dsp_dma_put_channel(dsp);
1635
1636        /* wait for DSP boot completion */
1637        sst_dsp_boot(dsp);
1638
1639        return ret;
1640}
1641
1642int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1643{
1644        int ret;
1645
1646        dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1647
1648        ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1649        if (ret < 0)
1650                return ret;
1651
1652        sst_dsp_stall(hsw->dsp);
1653
1654        ret = sst_hsw_dx_state_dump(hsw);
1655        if (ret < 0)
1656                return ret;
1657
1658        sst_ipc_drop_all(&hsw->ipc);
1659
1660        return 0;
1661}
1662
1663int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1664{
1665        struct sst_fw *sst_fw, *t;
1666        struct sst_dsp *dsp = hsw->dsp;
1667
1668        list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
1669                sst_fw_unload(sst_fw);
1670        }
1671        sst_block_free_scratch(dsp);
1672
1673        hsw->boot_complete = false;
1674
1675        sst_dsp_sleep(dsp);
1676
1677        return 0;
1678}
1679
1680int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1681{
1682        struct device *dev = hsw->dev;
1683        int ret;
1684
1685        dev_dbg(dev, "audio dsp runtime resume\n");
1686
1687        if (hsw->boot_complete)
1688                return 1; /* tell caller no action is required */
1689
1690        ret = sst_hsw_dsp_restore(hsw);
1691        if (ret < 0)
1692                dev_err(dev, "error: audio DSP boot failure\n");
1693
1694        sst_hsw_init_module_state(hsw);
1695
1696        ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1697                msecs_to_jiffies(IPC_BOOT_MSECS));
1698        if (ret == 0) {
1699                dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1700                        sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1701                        sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
1702                return -EIO;
1703        }
1704
1705        /* Set ADSP SSP port settings - sadly the FW does not store SSP port
1706           settings as part of the PM context. */
1707        ret = sst_hsw_device_set_config(hsw, hsw->dx_dev, hsw->dx_mclk,
1708                                        hsw->dx_mode, hsw->dx_clock_divider);
1709        if (ret < 0)
1710                dev_err(dev, "error: SSP re-initialization failed\n");
1711
1712        return ret;
1713}
1714#endif
1715
1716struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1717{
1718        return hsw->dsp;
1719}
1720
1721void sst_hsw_init_module_state(struct sst_hsw *hsw)
1722{
1723        struct sst_module *module;
1724        enum sst_hsw_module_id id;
1725
1726        /* the base fw contains several modules */
1727        for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
1728                module = sst_module_get_from_id(hsw->dsp, id);
1729                if (module) {
1730                        /* module waves is active only after being enabled */
1731                        if (id == SST_HSW_MODULE_WAVES)
1732                                module->state = SST_MODULE_STATE_INITIALIZED;
1733                        else
1734                                module->state = SST_MODULE_STATE_ACTIVE;
1735                }
1736        }
1737}
1738
1739bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
1740{
1741        struct sst_module *module;
1742
1743        module = sst_module_get_from_id(hsw->dsp, module_id);
1744        if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
1745                return false;
1746        else
1747                return true;
1748}
1749
1750bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
1751{
1752        struct sst_module *module;
1753
1754        module = sst_module_get_from_id(hsw->dsp, module_id);
1755        if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
1756                return true;
1757        else
1758                return false;
1759}
1760
1761void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1762{
1763        hsw->enabled_modules_rtd3 |= (1 << module_id);
1764}
1765
1766void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1767{
1768        hsw->enabled_modules_rtd3 &= ~(1 << module_id);
1769}
1770
1771bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
1772{
1773        return hsw->enabled_modules_rtd3 & (1 << module_id);
1774}
1775
1776void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
1777{
1778        hsw->param_idx_w = 0;
1779        hsw->param_idx_r = 0;
1780        memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
1781}
1782
1783int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
1784{
1785        /* save line to the first available position of param buffer */
1786        if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
1787                dev_warn(hsw->dev, "warning: param buffer overflow!\n");
1788                return -EPERM;
1789        }
1790        memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
1791        hsw->param_idx_w++;
1792        return 0;
1793}
1794
1795int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
1796{
1797        u8 id = 0;
1798
1799        /* read the first matching line from param buffer */
1800        while (hsw->param_idx_r < WAVES_PARAM_LINES) {
1801                id = hsw->param_buf[hsw->param_idx_r][0];
1802                hsw->param_idx_r++;
1803                if (buf[0] == id) {
1804                        memcpy(buf, hsw->param_buf[hsw->param_idx_r],
1805                                WAVES_PARAM_COUNT);
1806                        break;
1807                }
1808        }
1809        if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
1810                dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
1811                hsw->param_idx_r = 0;
1812                return 0;
1813        }
1814        return 0;
1815}
1816
1817int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
1818{
1819        int ret, idx;
1820
1821        if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
1822                dev_dbg(hsw->dev, "module waves is not active\n");
1823                return 0;
1824        }
1825
1826        /* put all param lines to DSP through ipc */
1827        for (idx = 0; idx < hsw->param_idx_w; idx++) {
1828                ret = sst_hsw_module_set_param(hsw,
1829                        SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
1830                        WAVES_PARAM_COUNT, hsw->param_buf[idx]);
1831                if (ret < 0)
1832                        return ret;
1833        }
1834        return 0;
1835}
1836
1837int sst_hsw_module_load(struct sst_hsw *hsw,
1838        u32 module_id, u32 instance_id, char *name)
1839{
1840        int ret = 0;
1841        const struct firmware *fw = NULL;
1842        struct sst_fw *hsw_sst_fw;
1843        struct sst_module *module;
1844        struct device *dev = hsw->dev;
1845        struct sst_dsp *dsp = hsw->dsp;
1846
1847        dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
1848
1849        module = sst_module_get_from_id(dsp, module_id);
1850        if (module == NULL) {
1851                /* loading for the first time */
1852                if (module_id == SST_HSW_MODULE_BASE_FW) {
1853                        /* for base module: use fw requested in acpi probe */
1854                        fw = dsp->pdata->fw;
1855                        if (!fw) {
1856                                dev_err(dev, "request Base fw failed\n");
1857                                return -ENODEV;
1858                        }
1859                } else {
1860                        /* try and load any other optional modules if they are
1861                         * available. Use dev_info instead of dev_err in case
1862                         * request firmware failed */
1863                        ret = request_firmware(&fw, name, dev);
1864                        if (ret) {
1865                                dev_info(dev, "fw image %s not available(%d)\n",
1866                                                name, ret);
1867                                return ret;
1868                        }
1869                }
1870                hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
1871                if (hsw_sst_fw  == NULL) {
1872                        dev_err(dev, "error: failed to load firmware\n");
1873                        ret = -ENOMEM;
1874                        goto out;
1875                }
1876                module = sst_module_get_from_id(dsp, module_id);
1877                if (module == NULL) {
1878                        dev_err(dev, "error: no module %d in firmware %s\n",
1879                                        module_id, name);
1880                }
1881        } else
1882                dev_info(dev, "module %d (%s) already loaded\n",
1883                                module_id, name);
1884out:
1885        /* release fw, but base fw should be released by acpi driver */
1886        if (fw && module_id != SST_HSW_MODULE_BASE_FW)
1887                release_firmware(fw);
1888
1889        return ret;
1890}
1891
1892int sst_hsw_module_enable(struct sst_hsw *hsw,
1893        u32 module_id, u32 instance_id)
1894{
1895        int ret;
1896        u32 header = 0;
1897        struct sst_hsw_ipc_module_config config;
1898        struct sst_module *module;
1899        struct sst_module_runtime *runtime;
1900        struct device *dev = hsw->dev;
1901        struct sst_dsp *dsp = hsw->dsp;
1902
1903        if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1904                dev_dbg(dev, "module %d not loaded\n", module_id);
1905                return 0;
1906        }
1907
1908        if (sst_hsw_is_module_active(hsw, module_id)) {
1909                dev_info(dev, "module %d already enabled\n", module_id);
1910                return 0;
1911        }
1912
1913        module = sst_module_get_from_id(dsp, module_id);
1914        if (module == NULL) {
1915                dev_err(dev, "module %d not valid\n", module_id);
1916                return -ENXIO;
1917        }
1918
1919        runtime = sst_module_runtime_get_from_id(module, module_id);
1920        if (runtime == NULL) {
1921                dev_err(dev, "runtime %d not valid", module_id);
1922                return -ENXIO;
1923        }
1924
1925        header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1926                        IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
1927                        IPC_MODULE_ID(module_id);
1928        dev_dbg(dev, "module enable header: %x\n", header);
1929
1930        config.map.module_entries_count = 1;
1931        config.map.module_entries[0].module_id = module->id;
1932        config.map.module_entries[0].entry_point = module->entry;
1933
1934        config.persistent_mem.offset =
1935                sst_dsp_get_offset(dsp,
1936                        runtime->persistent_offset, SST_MEM_DRAM);
1937        config.persistent_mem.size = module->persistent_size;
1938
1939        config.scratch_mem.offset =
1940                sst_dsp_get_offset(dsp,
1941                        dsp->scratch_offset, SST_MEM_DRAM);
1942        config.scratch_mem.size = module->scratch_size;
1943        dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
1944                config.map.module_entries[0].module_id,
1945                config.persistent_mem.size,
1946                config.persistent_mem.offset,
1947                config.scratch_mem.size, config.scratch_mem.offset,
1948                config.map.module_entries[0].entry_point);
1949
1950        ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
1951                        &config, sizeof(config), NULL, 0);
1952        if (ret < 0)
1953                dev_err(dev, "ipc: module enable failed - %d\n", ret);
1954        else
1955                module->state = SST_MODULE_STATE_ACTIVE;
1956
1957        return ret;
1958}
1959
1960int sst_hsw_module_disable(struct sst_hsw *hsw,
1961        u32 module_id, u32 instance_id)
1962{
1963        int ret;
1964        u32 header;
1965        struct sst_module *module;
1966        struct device *dev = hsw->dev;
1967        struct sst_dsp *dsp = hsw->dsp;
1968
1969        if (!sst_hsw_is_module_loaded(hsw, module_id)) {
1970                dev_dbg(dev, "module %d not loaded\n", module_id);
1971                return 0;
1972        }
1973
1974        if (!sst_hsw_is_module_active(hsw, module_id)) {
1975                dev_info(dev, "module %d already disabled\n", module_id);
1976                return 0;
1977        }
1978
1979        module = sst_module_get_from_id(dsp, module_id);
1980        if (module == NULL) {
1981                dev_err(dev, "module %d not valid\n", module_id);
1982                return -ENXIO;
1983        }
1984
1985        header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
1986                        IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
1987                        IPC_MODULE_ID(module_id);
1988
1989        ret = sst_ipc_tx_message_wait(&hsw->ipc, header,  NULL, 0, NULL, 0);
1990        if (ret < 0)
1991                dev_err(dev, "module disable failed - %d\n", ret);
1992        else
1993                module->state = SST_MODULE_STATE_INITIALIZED;
1994
1995        return ret;
1996}
1997
1998int sst_hsw_module_set_param(struct sst_hsw *hsw,
1999        u32 module_id, u32 instance_id, u32 parameter_id,
2000        u32 param_size, char *param)
2001{
2002        int ret;
2003        unsigned char *data = NULL;
2004        u32 header = 0;
2005        u32 payload_size = 0, transfer_parameter_size = 0;
2006        dma_addr_t dma_addr = 0;
2007        struct sst_hsw_transfer_parameter *parameter;
2008        struct device *dev = hsw->dev;
2009
2010        header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2011                        IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
2012                        IPC_MODULE_ID(module_id);
2013        dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header);
2014
2015        payload_size = param_size +
2016                sizeof(struct sst_hsw_transfer_parameter) -
2017                sizeof(struct sst_hsw_transfer_list);
2018        dev_dbg(dev, "parameter size : %d\n", param_size);
2019        dev_dbg(dev, "payload size   : %d\n", payload_size);
2020
2021        if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
2022                /* short parameter, mailbox can contain data */
2023                dev_dbg(dev, "transfer parameter size : %d\n",
2024                        transfer_parameter_size);
2025
2026                transfer_parameter_size = ALIGN(payload_size, 4);
2027                dev_dbg(dev, "transfer parameter aligned size : %d\n",
2028                        transfer_parameter_size);
2029
2030                parameter = kzalloc(transfer_parameter_size, GFP_KERNEL);
2031                if (parameter == NULL)
2032                        return -ENOMEM;
2033
2034                memcpy(parameter->data, param, param_size);
2035        } else {
2036                dev_warn(dev, "transfer parameter size too large!");
2037                return 0;
2038        }
2039
2040        parameter->parameter_id = parameter_id;
2041        parameter->data_size = param_size;
2042
2043        ret = sst_ipc_tx_message_wait(&hsw->ipc, header,
2044                parameter, transfer_parameter_size , NULL, 0);
2045        if (ret < 0)
2046                dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
2047
2048        kfree(parameter);
2049
2050        if (data)
2051                dma_free_coherent(hsw->dsp->dma_dev,
2052                        param_size, (void *)data, dma_addr);
2053
2054        return ret;
2055}
2056
2057static struct sst_dsp_device hsw_dev = {
2058        .thread = hsw_irq_thread,
2059        .ops = &haswell_ops,
2060};
2061
2062static void hsw_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
2063{
2064        /* send the message */
2065        sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
2066        sst_dsp_ipc_msg_tx(ipc->dsp, msg->header);
2067}
2068
2069static void hsw_shim_dbg(struct sst_generic_ipc *ipc, const char *text)
2070{
2071        struct sst_dsp *sst = ipc->dsp;
2072        u32 isr, ipcd, imrx, ipcx;
2073
2074        ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
2075        isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
2076        ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
2077        imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
2078
2079        dev_err(ipc->dev,
2080                "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
2081                text, ipcx, isr, ipcd, imrx);
2082}
2083
2084static void hsw_tx_data_copy(struct ipc_message *msg, char *tx_data,
2085        size_t tx_size)
2086{
2087        memcpy(msg->tx_data, tx_data, tx_size);
2088}
2089
2090static u64 hsw_reply_msg_match(u64 header, u64 *mask)
2091{
2092        /* clear reply bits & status bits */
2093        header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
2094        *mask = (u64)-1;
2095
2096        return header;
2097}
2098
2099static bool hsw_is_dsp_busy(struct sst_dsp *dsp)
2100{
2101        u64 ipcx;
2102
2103        ipcx = sst_dsp_shim_read_unlocked(dsp, SST_IPCX);
2104        return (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE));
2105}
2106
2107int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2108{
2109        struct sst_hsw_ipc_fw_version version;
2110        struct sst_hsw *hsw;
2111        struct sst_generic_ipc *ipc;
2112        int ret;
2113
2114        dev_dbg(dev, "initialising Audio DSP IPC\n");
2115
2116        hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2117        if (hsw == NULL)
2118                return -ENOMEM;
2119
2120        hsw->dev = dev;
2121
2122        ipc = &hsw->ipc;
2123        ipc->dev = dev;
2124        ipc->ops.tx_msg = hsw_tx_msg;
2125        ipc->ops.shim_dbg = hsw_shim_dbg;
2126        ipc->ops.tx_data_copy = hsw_tx_data_copy;
2127        ipc->ops.reply_msg_match = hsw_reply_msg_match;
2128        ipc->ops.is_dsp_busy = hsw_is_dsp_busy;
2129
2130        ipc->tx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2131        ipc->rx_data_max_size = IPC_MAX_MAILBOX_BYTES;
2132
2133        ret = sst_ipc_init(ipc);
2134        if (ret != 0)
2135                goto ipc_init_err;
2136
2137        INIT_LIST_HEAD(&hsw->stream_list);
2138        init_waitqueue_head(&hsw->boot_wait);
2139        hsw_dev.thread_context = hsw;
2140
2141        /* init SST shim */
2142        hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2143        if (hsw->dsp == NULL) {
2144                ret = -ENODEV;
2145                goto dsp_new_err;
2146        }
2147
2148        ipc->dsp = hsw->dsp;
2149
2150        /* allocate DMA buffer for context storage */
2151        hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2152                SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2153        if (hsw->dx_context == NULL) {
2154                ret = -ENOMEM;
2155                goto dma_err;
2156        }
2157
2158        /* keep the DSP in reset state for base FW loading */
2159        sst_dsp_reset(hsw->dsp);
2160
2161        /* load base module and other modules in base firmware image */
2162        ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
2163        if (ret < 0)
2164                goto fw_err;
2165
2166        /* try to load module waves */
2167        sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin");
2168
2169        /* allocate scratch mem regions */
2170        ret = sst_block_alloc_scratch(hsw->dsp);
2171        if (ret < 0)
2172                goto boot_err;
2173
2174        /* init param buffer */
2175        sst_hsw_reset_param_buf(hsw);
2176
2177        /* wait for DSP boot completion */
2178        sst_dsp_boot(hsw->dsp);
2179        ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2180                msecs_to_jiffies(IPC_BOOT_MSECS));
2181        if (ret == 0) {
2182                ret = -EIO;
2183                dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2184                        sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2185                        sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
2186                goto boot_err;
2187        }
2188
2189        /* init module state after boot */
2190        sst_hsw_init_module_state(hsw);
2191
2192        /* get the FW version */
2193        sst_hsw_fw_get_version(hsw, &version);
2194
2195        /* get the globalmixer */
2196        ret = sst_hsw_mixer_get_info(hsw);
2197        if (ret < 0) {
2198                dev_err(hsw->dev, "error: failed to get stream info\n");
2199                goto boot_err;
2200        }
2201
2202        pdata->dsp = hsw;
2203        return 0;
2204
2205boot_err:
2206        sst_dsp_reset(hsw->dsp);
2207        sst_fw_free_all(hsw->dsp);
2208fw_err:
2209        dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2210                        hsw->dx_context, hsw->dx_context_paddr);
2211dma_err:
2212        sst_dsp_free(hsw->dsp);
2213dsp_new_err:
2214        sst_ipc_fini(ipc);
2215ipc_init_err:
2216        return ret;
2217}
2218EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2219
2220void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2221{
2222        struct sst_hsw *hsw = pdata->dsp;
2223
2224        sst_dsp_reset(hsw->dsp);
2225        sst_fw_free_all(hsw->dsp);
2226        dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2227                        hsw->dx_context, hsw->dx_context_paddr);
2228        sst_dsp_free(hsw->dsp);
2229        sst_ipc_fini(&hsw->ipc);
2230}
2231EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);
2232