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24#include <linux/types.h>
25#include <linux/platform_device.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/module.h>
29#include <linux/interrupt.h>
30#include <linux/pm_runtime.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <asm/cacheflush.h>
34#include <sound/core.h>
35#include <sound/asoundef.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/initval.h>
39#include <sound/control.h>
40#include <sound/jack.h>
41#include <drm/drm_edid.h>
42#include <drm/intel_lpe_audio.h>
43#include "intel_hdmi_audio.h"
44
45
46static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
47static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
48
49module_param_named(index, hdmi_card_index, int, 0444);
50MODULE_PARM_DESC(index,
51 "Index value for INTEL Intel HDMI Audio controller.");
52module_param_named(id, hdmi_card_id, charp, 0444);
53MODULE_PARM_DESC(id,
54 "ID string for INTEL Intel HDMI Audio controller.");
55
56
57
58
59static const int eld_speaker_allocation_bits[] = {
60 [0] = FL | FR,
61 [1] = LFE,
62 [2] = FC,
63 [3] = RL | RR,
64 [4] = RC,
65 [5] = FLC | FRC,
66 [6] = RLC | RRC,
67
68 [7] = 0,
69};
70
71
72
73
74
75
76
77static struct cea_channel_speaker_allocation channel_allocations[] = {
78
79{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
80
81{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
82
83{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
84
85{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
86
87{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
88
89{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
90
91{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
92
93{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
94
95{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
96
97{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
98{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
99{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
100{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
101{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
102{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
103{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
104{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
105{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
106{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
107{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
108{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
109{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
110{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
111{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
112{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
113{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
114{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
115{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
116{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
117{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
118{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
119{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
120};
121
122static const struct channel_map_table map_tables[] = {
123 { SNDRV_CHMAP_FL, 0x00, FL },
124 { SNDRV_CHMAP_FR, 0x01, FR },
125 { SNDRV_CHMAP_RL, 0x04, RL },
126 { SNDRV_CHMAP_RR, 0x05, RR },
127 { SNDRV_CHMAP_LFE, 0x02, LFE },
128 { SNDRV_CHMAP_FC, 0x03, FC },
129 { SNDRV_CHMAP_RLC, 0x06, RLC },
130 { SNDRV_CHMAP_RRC, 0x07, RRC },
131 {}
132};
133
134
135static const struct snd_pcm_hardware had_pcm_hardware = {
136 .info = (SNDRV_PCM_INFO_INTERLEAVED |
137 SNDRV_PCM_INFO_MMAP |
138 SNDRV_PCM_INFO_MMAP_VALID |
139 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
140 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
141 SNDRV_PCM_FMTBIT_S24_LE |
142 SNDRV_PCM_FMTBIT_S32_LE),
143 .rates = SNDRV_PCM_RATE_32000 |
144 SNDRV_PCM_RATE_44100 |
145 SNDRV_PCM_RATE_48000 |
146 SNDRV_PCM_RATE_88200 |
147 SNDRV_PCM_RATE_96000 |
148 SNDRV_PCM_RATE_176400 |
149 SNDRV_PCM_RATE_192000,
150 .rate_min = HAD_MIN_RATE,
151 .rate_max = HAD_MAX_RATE,
152 .channels_min = HAD_MIN_CHANNEL,
153 .channels_max = HAD_MAX_CHANNEL,
154 .buffer_bytes_max = HAD_MAX_BUFFER,
155 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
156 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
157 .periods_min = HAD_MIN_PERIODS,
158 .periods_max = HAD_MAX_PERIODS,
159 .fifo_size = HAD_FIFO_SIZE,
160};
161
162
163
164
165
166static struct snd_pcm_substream *
167had_substream_get(struct snd_intelhad *intelhaddata)
168{
169 struct snd_pcm_substream *substream;
170 unsigned long flags;
171
172 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
173 substream = intelhaddata->stream_info.substream;
174 if (substream)
175 intelhaddata->stream_info.substream_refcount++;
176 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
177 return substream;
178}
179
180
181
182
183static void had_substream_put(struct snd_intelhad *intelhaddata)
184{
185 unsigned long flags;
186
187 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
188 intelhaddata->stream_info.substream_refcount--;
189 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
190}
191
192
193static u32 had_read_register_raw(struct snd_intelhad *ctx, u32 reg)
194{
195 return ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
196}
197
198static void had_write_register_raw(struct snd_intelhad *ctx, u32 reg, u32 val)
199{
200 iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
201}
202
203static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
204{
205 if (!ctx->connected)
206 *val = 0;
207 else
208 *val = had_read_register_raw(ctx, reg);
209}
210
211static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
212{
213 if (ctx->connected)
214 had_write_register_raw(ctx, reg, val);
215}
216
217
218
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228
229
230
231
232static void had_enable_audio(struct snd_intelhad *intelhaddata,
233 bool enable)
234{
235
236 intelhaddata->aud_config.regx.aud_en = enable;
237 had_write_register(intelhaddata, AUD_CONFIG,
238 intelhaddata->aud_config.regval);
239}
240
241
242static void had_ack_irqs(struct snd_intelhad *ctx)
243{
244 u32 status_reg;
245
246 if (!ctx->connected)
247 return;
248 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
249 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
250 had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
251 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
252}
253
254
255static void had_reset_audio(struct snd_intelhad *intelhaddata)
256{
257 had_write_register(intelhaddata, AUD_HDMI_STATUS,
258 AUD_HDMI_STATUSG_MASK_FUNCRST);
259 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
260}
261
262
263
264
265
266static int had_prog_status_reg(struct snd_pcm_substream *substream,
267 struct snd_intelhad *intelhaddata)
268{
269 union aud_cfg cfg_val = {.regval = 0};
270 union aud_ch_status_0 ch_stat0 = {.regval = 0};
271 union aud_ch_status_1 ch_stat1 = {.regval = 0};
272
273 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
274 IEC958_AES0_NONAUDIO) >> 1;
275 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
276 IEC958_AES3_CON_CLOCK) >> 4;
277 cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id;
278
279 switch (substream->runtime->rate) {
280 case AUD_SAMPLE_RATE_32:
281 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
282 break;
283
284 case AUD_SAMPLE_RATE_44_1:
285 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
286 break;
287 case AUD_SAMPLE_RATE_48:
288 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
289 break;
290 case AUD_SAMPLE_RATE_88_2:
291 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
292 break;
293 case AUD_SAMPLE_RATE_96:
294 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
295 break;
296 case AUD_SAMPLE_RATE_176_4:
297 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
298 break;
299 case AUD_SAMPLE_RATE_192:
300 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
301 break;
302
303 default:
304
305 return -EINVAL;
306 }
307
308 had_write_register(intelhaddata,
309 AUD_CH_STATUS_0, ch_stat0.regval);
310
311 switch (substream->runtime->format) {
312 case SNDRV_PCM_FORMAT_S16_LE:
313 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
314 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
315 break;
316 case SNDRV_PCM_FORMAT_S24_LE:
317 case SNDRV_PCM_FORMAT_S32_LE:
318 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
319 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
320 break;
321 default:
322 return -EINVAL;
323 }
324
325 had_write_register(intelhaddata,
326 AUD_CH_STATUS_1, ch_stat1.regval);
327 return 0;
328}
329
330
331
332
333
334
335static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
336 struct snd_intelhad *intelhaddata)
337{
338 union aud_cfg cfg_val = {.regval = 0};
339 union aud_buf_config buf_cfg = {.regval = 0};
340 u8 channels;
341
342 had_prog_status_reg(substream, intelhaddata);
343
344 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
345 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
346 buf_cfg.regx.aud_delay = 0;
347 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
348
349 channels = substream->runtime->channels;
350 cfg_val.regx.num_ch = channels - 2;
351 if (channels <= 2)
352 cfg_val.regx.layout = LAYOUT0;
353 else
354 cfg_val.regx.layout = LAYOUT1;
355
356 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
357 cfg_val.regx.packet_mode = 1;
358
359 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
360 cfg_val.regx.left_align = 1;
361
362 cfg_val.regx.val_bit = 1;
363
364
365 if (intelhaddata->dp_output) {
366 cfg_val.regx.dp_modei = 1;
367 cfg_val.regx.set = 1;
368 }
369
370 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
371 intelhaddata->aud_config = cfg_val;
372 return 0;
373}
374
375
376
377
378static void init_channel_allocations(void)
379{
380 int i, j;
381 struct cea_channel_speaker_allocation *p;
382
383 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
384 p = channel_allocations + i;
385 p->channels = 0;
386 p->spk_mask = 0;
387 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
388 if (p->speakers[j]) {
389 p->channels++;
390 p->spk_mask |= p->speakers[j];
391 }
392 }
393}
394
395
396
397
398
399
400
401
402
403static int had_channel_allocation(struct snd_intelhad *intelhaddata,
404 int channels)
405{
406 int i;
407 int ca = 0;
408 int spk_mask = 0;
409
410
411
412
413 if (channels <= 2)
414 return 0;
415
416
417
418
419
420
421
422
423 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
424 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
425 spk_mask |= eld_speaker_allocation_bits[i];
426 }
427
428
429 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
430 if (channels == channel_allocations[i].channels &&
431 (spk_mask & channel_allocations[i].spk_mask) ==
432 channel_allocations[i].spk_mask) {
433 ca = channel_allocations[i].ca_index;
434 break;
435 }
436 }
437
438 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
439
440 return ca;
441}
442
443
444static int spk_to_chmap(int spk)
445{
446 const struct channel_map_table *t = map_tables;
447
448 for (; t->map; t++) {
449 if (t->spk_mask == spk)
450 return t->map;
451 }
452 return 0;
453}
454
455static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
456{
457 int i, c;
458 int spk_mask = 0;
459 struct snd_pcm_chmap_elem *chmap;
460 u8 eld_high, eld_high_mask = 0xF0;
461 u8 high_msb;
462
463 kfree(intelhaddata->chmap->chmap);
464 intelhaddata->chmap->chmap = NULL;
465
466 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
467 if (!chmap)
468 return;
469
470 dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
471 intelhaddata->eld[DRM_ELD_SPEAKER]);
472
473
474
475
476
477
478
479
480
481
482 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
483 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
484
485
486 for (i = 1; i < 4; i++) {
487 high_msb = eld_high & (0x80 >> i);
488 if (high_msb) {
489 intelhaddata->eld[DRM_ELD_SPEAKER] &=
490 high_msb | 0xF;
491 break;
492 }
493 }
494 }
495
496 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
497 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
498 spk_mask |= eld_speaker_allocation_bits[i];
499 }
500
501 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
502 if (spk_mask == channel_allocations[i].spk_mask) {
503 for (c = 0; c < channel_allocations[i].channels; c++) {
504 chmap->map[c] = spk_to_chmap(
505 channel_allocations[i].speakers[
506 (MAX_SPEAKERS - 1) - c]);
507 }
508 chmap->channels = channel_allocations[i].channels;
509 intelhaddata->chmap->chmap = chmap;
510 break;
511 }
512 }
513 if (i >= ARRAY_SIZE(channel_allocations))
514 kfree(chmap);
515}
516
517
518
519
520static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_info *uinfo)
522{
523 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
524 uinfo->count = HAD_MAX_CHANNEL;
525 uinfo->value.integer.min = 0;
526 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
527 return 0;
528}
529
530static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
531 struct snd_ctl_elem_value *ucontrol)
532{
533 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
534 struct snd_intelhad *intelhaddata = info->private_data;
535 int i;
536 const struct snd_pcm_chmap_elem *chmap;
537
538 memset(ucontrol->value.integer.value, 0,
539 sizeof(long) * HAD_MAX_CHANNEL);
540 mutex_lock(&intelhaddata->mutex);
541 if (!intelhaddata->chmap->chmap) {
542 mutex_unlock(&intelhaddata->mutex);
543 return 0;
544 }
545
546 chmap = intelhaddata->chmap->chmap;
547 for (i = 0; i < chmap->channels; i++)
548 ucontrol->value.integer.value[i] = chmap->map[i];
549 mutex_unlock(&intelhaddata->mutex);
550
551 return 0;
552}
553
554static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
555 struct snd_pcm *pcm)
556{
557 int err;
558
559 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
560 NULL, 0, (unsigned long)intelhaddata,
561 &intelhaddata->chmap);
562 if (err < 0)
563 return err;
564
565 intelhaddata->chmap->private_data = intelhaddata;
566 intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
567 intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
568 intelhaddata->chmap->chmap = NULL;
569 return 0;
570}
571
572
573
574
575
576static void had_prog_dip(struct snd_pcm_substream *substream,
577 struct snd_intelhad *intelhaddata)
578{
579 int i;
580 union aud_ctrl_st ctrl_state = {.regval = 0};
581 union aud_info_frame2 frame2 = {.regval = 0};
582 union aud_info_frame3 frame3 = {.regval = 0};
583 u8 checksum = 0;
584 u32 info_frame;
585 int channels;
586 int ca;
587
588 channels = substream->runtime->channels;
589
590 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
591
592 ca = had_channel_allocation(intelhaddata, channels);
593 if (intelhaddata->dp_output) {
594 info_frame = DP_INFO_FRAME_WORD1;
595 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
596 } else {
597 info_frame = HDMI_INFO_FRAME_WORD1;
598 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
599 frame3.regx.chnl_alloc = ca;
600
601
602 for (i = 0; i < BYTES_PER_WORD; i++)
603 checksum += (info_frame >> (i * 8)) & 0xff;
604 for (i = 0; i < BYTES_PER_WORD; i++)
605 checksum += (frame2.regval >> (i * 8)) & 0xff;
606 for (i = 0; i < BYTES_PER_WORD; i++)
607 checksum += (frame3.regval >> (i * 8)) & 0xff;
608
609 frame2.regx.chksum = -(checksum);
610 }
611
612 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
613 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
614 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
615
616
617 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
618 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
619
620 ctrl_state.regx.dip_freq = 1;
621 ctrl_state.regx.dip_en_sta = 1;
622 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
623}
624
625static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
626{
627 u32 maud_val;
628
629
630 if (link_rate == DP_2_7_GHZ) {
631 switch (aud_samp_freq) {
632 case AUD_SAMPLE_RATE_32:
633 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
634 break;
635
636 case AUD_SAMPLE_RATE_44_1:
637 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
638 break;
639
640 case AUD_SAMPLE_RATE_48:
641 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
642 break;
643
644 case AUD_SAMPLE_RATE_88_2:
645 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
646 break;
647
648 case AUD_SAMPLE_RATE_96:
649 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
650 break;
651
652 case AUD_SAMPLE_RATE_176_4:
653 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
654 break;
655
656 case HAD_MAX_RATE:
657 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
658 break;
659
660 default:
661 maud_val = -EINVAL;
662 break;
663 }
664 } else if (link_rate == DP_1_62_GHZ) {
665 switch (aud_samp_freq) {
666 case AUD_SAMPLE_RATE_32:
667 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
668 break;
669
670 case AUD_SAMPLE_RATE_44_1:
671 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
672 break;
673
674 case AUD_SAMPLE_RATE_48:
675 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
676 break;
677
678 case AUD_SAMPLE_RATE_88_2:
679 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
680 break;
681
682 case AUD_SAMPLE_RATE_96:
683 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
684 break;
685
686 case AUD_SAMPLE_RATE_176_4:
687 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
688 break;
689
690 case HAD_MAX_RATE:
691 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
692 break;
693
694 default:
695 maud_val = -EINVAL;
696 break;
697 }
698 } else
699 maud_val = -EINVAL;
700
701 return maud_val;
702}
703
704
705
706
707
708
709
710
711
712
713
714
715static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
716 u32 n_param, struct snd_intelhad *intelhaddata)
717{
718 u32 cts_val;
719 u64 dividend, divisor;
720
721 if (intelhaddata->dp_output) {
722
723 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
724 } else {
725
726 dividend = (u64)tmds * n_param*1000;
727 divisor = 128 * aud_samp_freq;
728 cts_val = div64_u64(dividend, divisor);
729 }
730 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
731 tmds, n_param, cts_val);
732 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
733}
734
735static int had_calculate_n_value(u32 aud_samp_freq)
736{
737 int n_val;
738
739
740 switch (aud_samp_freq) {
741 case AUD_SAMPLE_RATE_32:
742 n_val = 4096;
743 break;
744
745 case AUD_SAMPLE_RATE_44_1:
746 n_val = 6272;
747 break;
748
749 case AUD_SAMPLE_RATE_48:
750 n_val = 6144;
751 break;
752
753 case AUD_SAMPLE_RATE_88_2:
754 n_val = 12544;
755 break;
756
757 case AUD_SAMPLE_RATE_96:
758 n_val = 12288;
759 break;
760
761 case AUD_SAMPLE_RATE_176_4:
762 n_val = 25088;
763 break;
764
765 case HAD_MAX_RATE:
766 n_val = 24576;
767 break;
768
769 default:
770 n_val = -EINVAL;
771 break;
772 }
773 return n_val;
774}
775
776
777
778
779
780
781
782
783
784
785
786static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
787 struct snd_intelhad *intelhaddata)
788{
789 int n_val;
790
791 if (intelhaddata->dp_output) {
792
793
794
795
796
797
798
799
800 n_val = DP_NAUD_VAL;
801 } else
802 n_val = had_calculate_n_value(aud_samp_freq);
803
804 if (n_val < 0)
805 return n_val;
806
807 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
808 *n_param = n_val;
809 return 0;
810}
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852#define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
853#define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
854
855
856static void had_prog_bd(struct snd_pcm_substream *substream,
857 struct snd_intelhad *intelhaddata)
858{
859 int idx = intelhaddata->bd_head;
860 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
861 u32 addr = substream->runtime->dma_addr + ofs;
862
863 addr |= AUD_BUF_VALID;
864 if (!substream->runtime->no_period_wakeup)
865 addr |= AUD_BUF_INTR_EN;
866 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
867 had_write_register(intelhaddata, AUD_BUF_LEN(idx),
868 intelhaddata->period_bytes);
869
870
871 intelhaddata->bd_head++;
872 intelhaddata->bd_head %= intelhaddata->num_bds;
873 intelhaddata->pcmbuf_filled++;
874 intelhaddata->pcmbuf_filled %= substream->runtime->periods;
875}
876
877
878static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
879 int idx)
880{
881 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
882 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
883}
884
885
886static void had_init_ringbuf(struct snd_pcm_substream *substream,
887 struct snd_intelhad *intelhaddata)
888{
889 struct snd_pcm_runtime *runtime = substream->runtime;
890 int i, num_periods;
891
892 num_periods = runtime->periods;
893 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
894
895 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
896 intelhaddata->period_bytes =
897 frames_to_bytes(runtime, runtime->period_size);
898 WARN_ON(intelhaddata->period_bytes & 0x3f);
899
900 intelhaddata->bd_head = 0;
901 intelhaddata->pcmbuf_head = 0;
902 intelhaddata->pcmbuf_filled = 0;
903
904 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
905 if (i < intelhaddata->num_bds)
906 had_prog_bd(substream, intelhaddata);
907 else
908 had_invalidate_bd(intelhaddata, i);
909 }
910
911 intelhaddata->bd_head = 0;
912}
913
914
915static void had_advance_ringbuf(struct snd_pcm_substream *substream,
916 struct snd_intelhad *intelhaddata)
917{
918 int num_periods = substream->runtime->periods;
919
920
921 had_prog_bd(substream, intelhaddata);
922
923
924 intelhaddata->pcmbuf_head++;
925 intelhaddata->pcmbuf_head %= num_periods;
926}
927
928
929
930
931static int had_process_ringbuf(struct snd_pcm_substream *substream,
932 struct snd_intelhad *intelhaddata)
933{
934 int len, processed;
935 unsigned long flags;
936
937 processed = 0;
938 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
939 for (;;) {
940
941 had_read_register(intelhaddata,
942 AUD_BUF_LEN(intelhaddata->bd_head),
943 &len);
944 if (len < 0 || len > intelhaddata->period_bytes) {
945 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
946 len);
947 len = -EPIPE;
948 goto out;
949 }
950
951 if (len > 0)
952 break;
953
954
955 if (++processed >= intelhaddata->num_bds) {
956 len = -EPIPE;
957 goto out;
958 }
959 had_advance_ringbuf(substream, intelhaddata);
960 }
961
962 len = intelhaddata->period_bytes - len;
963 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
964 out:
965 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
966 return len;
967}
968
969
970static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
971{
972 struct snd_pcm_substream *substream;
973
974 substream = had_substream_get(intelhaddata);
975 if (!substream)
976 return;
977
978 if (!intelhaddata->connected) {
979 snd_pcm_stop_xrun(substream);
980 goto out;
981 }
982
983
984 if (had_process_ringbuf(substream, intelhaddata) < 0)
985 snd_pcm_stop_xrun(substream);
986 else
987 snd_pcm_period_elapsed(substream);
988
989 out:
990 had_substream_put(intelhaddata);
991}
992
993
994
995
996
997static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
998{
999 int i;
1000 u32 val;
1001
1002 for (i = 0; i < 100; i++) {
1003
1004 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
1005 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
1006 return;
1007 udelay(100);
1008 cond_resched();
1009 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
1010 }
1011 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
1012}
1013
1014
1015
1016
1017
1018static void had_do_reset(struct snd_intelhad *intelhaddata)
1019{
1020 if (!intelhaddata->need_reset || !intelhaddata->connected)
1021 return;
1022
1023
1024 had_reset_audio(intelhaddata);
1025 wait_clear_underrun_bit(intelhaddata);
1026 intelhaddata->need_reset = false;
1027}
1028
1029
1030static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1031{
1032 struct snd_pcm_substream *substream;
1033
1034
1035 substream = had_substream_get(intelhaddata);
1036 if (substream) {
1037 snd_pcm_stop_xrun(substream);
1038 had_substream_put(intelhaddata);
1039 }
1040 intelhaddata->need_reset = true;
1041}
1042
1043
1044
1045
1046static int had_pcm_open(struct snd_pcm_substream *substream)
1047{
1048 struct snd_intelhad *intelhaddata;
1049 struct snd_pcm_runtime *runtime;
1050 int retval;
1051
1052 intelhaddata = snd_pcm_substream_chip(substream);
1053 runtime = substream->runtime;
1054
1055 pm_runtime_get_sync(intelhaddata->dev);
1056
1057
1058 runtime->hw = had_pcm_hardware;
1059
1060 retval = snd_pcm_hw_constraint_integer(runtime,
1061 SNDRV_PCM_HW_PARAM_PERIODS);
1062 if (retval < 0)
1063 goto error;
1064
1065
1066
1067
1068 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1069 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1070 if (retval < 0)
1071 goto error;
1072
1073 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1074 if (retval < 0)
1075 goto error;
1076
1077
1078 spin_lock_irq(&intelhaddata->had_spinlock);
1079 intelhaddata->stream_info.substream = substream;
1080 intelhaddata->stream_info.substream_refcount++;
1081 spin_unlock_irq(&intelhaddata->had_spinlock);
1082
1083 return retval;
1084 error:
1085 pm_runtime_mark_last_busy(intelhaddata->dev);
1086 pm_runtime_put_autosuspend(intelhaddata->dev);
1087 return retval;
1088}
1089
1090
1091
1092
1093static int had_pcm_close(struct snd_pcm_substream *substream)
1094{
1095 struct snd_intelhad *intelhaddata;
1096
1097 intelhaddata = snd_pcm_substream_chip(substream);
1098
1099
1100 spin_lock_irq(&intelhaddata->had_spinlock);
1101 intelhaddata->stream_info.substream = NULL;
1102 intelhaddata->stream_info.substream_refcount--;
1103 while (intelhaddata->stream_info.substream_refcount > 0) {
1104 spin_unlock_irq(&intelhaddata->had_spinlock);
1105 cpu_relax();
1106 spin_lock_irq(&intelhaddata->had_spinlock);
1107 }
1108 spin_unlock_irq(&intelhaddata->had_spinlock);
1109
1110 pm_runtime_mark_last_busy(intelhaddata->dev);
1111 pm_runtime_put_autosuspend(intelhaddata->dev);
1112 return 0;
1113}
1114
1115
1116
1117
1118static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1119 struct snd_pcm_hw_params *hw_params)
1120{
1121 struct snd_intelhad *intelhaddata;
1122 unsigned long addr;
1123 int pages, buf_size, retval;
1124
1125 intelhaddata = snd_pcm_substream_chip(substream);
1126 buf_size = params_buffer_bytes(hw_params);
1127 retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1128 if (retval < 0)
1129 return retval;
1130 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1131 __func__, buf_size);
1132
1133 addr = (unsigned long) substream->runtime->dma_area;
1134 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE;
1135 retval = set_memory_uc(addr, pages);
1136 if (retval) {
1137 dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n",
1138 retval);
1139 return retval;
1140 }
1141 memset(substream->runtime->dma_area, 0, buf_size);
1142
1143 return retval;
1144}
1145
1146
1147
1148
1149static int had_pcm_hw_free(struct snd_pcm_substream *substream)
1150{
1151 struct snd_intelhad *intelhaddata;
1152 unsigned long addr;
1153 u32 pages;
1154
1155 intelhaddata = snd_pcm_substream_chip(substream);
1156 had_do_reset(intelhaddata);
1157
1158
1159 if (substream->runtime->dma_area != NULL) {
1160 addr = (unsigned long) substream->runtime->dma_area;
1161 pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) /
1162 PAGE_SIZE;
1163 set_memory_wb(addr, pages);
1164 return snd_pcm_lib_free_pages(substream);
1165 }
1166 return 0;
1167}
1168
1169
1170
1171
1172static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1173{
1174 int retval = 0;
1175 struct snd_intelhad *intelhaddata;
1176
1177 intelhaddata = snd_pcm_substream_chip(substream);
1178
1179 spin_lock(&intelhaddata->had_spinlock);
1180 switch (cmd) {
1181 case SNDRV_PCM_TRIGGER_START:
1182 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1183 case SNDRV_PCM_TRIGGER_RESUME:
1184
1185 had_ack_irqs(intelhaddata);
1186 had_enable_audio(intelhaddata, true);
1187 break;
1188
1189 case SNDRV_PCM_TRIGGER_STOP:
1190 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1191
1192 had_enable_audio(intelhaddata, false);
1193 intelhaddata->need_reset = true;
1194 break;
1195
1196 default:
1197 retval = -EINVAL;
1198 }
1199 spin_unlock(&intelhaddata->had_spinlock);
1200 return retval;
1201}
1202
1203
1204
1205
1206static int had_pcm_prepare(struct snd_pcm_substream *substream)
1207{
1208 int retval;
1209 u32 disp_samp_freq, n_param;
1210 u32 link_rate = 0;
1211 struct snd_intelhad *intelhaddata;
1212 struct snd_pcm_runtime *runtime;
1213
1214 intelhaddata = snd_pcm_substream_chip(substream);
1215 runtime = substream->runtime;
1216
1217 dev_dbg(intelhaddata->dev, "period_size=%d\n",
1218 (int)frames_to_bytes(runtime, runtime->period_size));
1219 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1220 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1221 (int)snd_pcm_lib_buffer_bytes(substream));
1222 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1223 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1224
1225 had_do_reset(intelhaddata);
1226
1227
1228 disp_samp_freq = intelhaddata->tmds_clock_speed;
1229
1230 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1231 if (retval) {
1232 dev_err(intelhaddata->dev,
1233 "programming N value failed %#x\n", retval);
1234 goto prep_end;
1235 }
1236
1237 if (intelhaddata->dp_output)
1238 link_rate = intelhaddata->link_rate;
1239
1240 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1241 n_param, intelhaddata);
1242
1243 had_prog_dip(substream, intelhaddata);
1244
1245 retval = had_init_audio_ctrl(substream, intelhaddata);
1246
1247
1248 had_init_ringbuf(substream, intelhaddata);
1249
1250
1251
1252
1253
1254
1255 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1256
1257prep_end:
1258 return retval;
1259}
1260
1261
1262
1263
1264static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1265{
1266 struct snd_intelhad *intelhaddata;
1267 int len;
1268
1269 intelhaddata = snd_pcm_substream_chip(substream);
1270
1271 if (!intelhaddata->connected)
1272 return SNDRV_PCM_POS_XRUN;
1273
1274 len = had_process_ringbuf(substream, intelhaddata);
1275 if (len < 0)
1276 return SNDRV_PCM_POS_XRUN;
1277 len = bytes_to_frames(substream->runtime, len);
1278
1279 len %= substream->runtime->buffer_size;
1280 return len;
1281}
1282
1283
1284
1285
1286static int had_pcm_mmap(struct snd_pcm_substream *substream,
1287 struct vm_area_struct *vma)
1288{
1289 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1290 return remap_pfn_range(vma, vma->vm_start,
1291 substream->dma_buffer.addr >> PAGE_SHIFT,
1292 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1293}
1294
1295
1296
1297
1298static const struct snd_pcm_ops had_pcm_ops = {
1299 .open = had_pcm_open,
1300 .close = had_pcm_close,
1301 .ioctl = snd_pcm_lib_ioctl,
1302 .hw_params = had_pcm_hw_params,
1303 .hw_free = had_pcm_hw_free,
1304 .prepare = had_pcm_prepare,
1305 .trigger = had_pcm_trigger,
1306 .pointer = had_pcm_pointer,
1307 .mmap = had_pcm_mmap,
1308};
1309
1310
1311static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1312{
1313 struct snd_pcm_substream *substream;
1314 int retval = 0;
1315 u32 disp_samp_freq, n_param;
1316 u32 link_rate = 0;
1317
1318 substream = had_substream_get(intelhaddata);
1319 if (!substream)
1320 return 0;
1321
1322
1323 had_enable_audio(intelhaddata, false);
1324
1325
1326 disp_samp_freq = intelhaddata->tmds_clock_speed;
1327
1328 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1329 if (retval) {
1330 dev_err(intelhaddata->dev,
1331 "programming N value failed %#x\n", retval);
1332 goto out;
1333 }
1334
1335 if (intelhaddata->dp_output)
1336 link_rate = intelhaddata->link_rate;
1337
1338 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1339 n_param, intelhaddata);
1340
1341
1342 had_enable_audio(intelhaddata, true);
1343
1344out:
1345 had_substream_put(intelhaddata);
1346 return retval;
1347}
1348
1349
1350static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1351{
1352 struct snd_pcm_substream *substream;
1353
1354 spin_lock_irq(&intelhaddata->had_spinlock);
1355 if (intelhaddata->connected) {
1356 dev_dbg(intelhaddata->dev, "Device already connected\n");
1357 spin_unlock_irq(&intelhaddata->had_spinlock);
1358 return;
1359 }
1360
1361 intelhaddata->connected = true;
1362 dev_dbg(intelhaddata->dev,
1363 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1364 __func__, __LINE__);
1365 spin_unlock_irq(&intelhaddata->had_spinlock);
1366
1367 had_build_channel_allocation_map(intelhaddata);
1368
1369
1370 substream = had_substream_get(intelhaddata);
1371 if (substream) {
1372 snd_pcm_stop_xrun(substream);
1373 had_substream_put(intelhaddata);
1374 }
1375
1376 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
1377}
1378
1379
1380static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1381{
1382 struct snd_pcm_substream *substream;
1383
1384 spin_lock_irq(&intelhaddata->had_spinlock);
1385 if (!intelhaddata->connected) {
1386 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1387 spin_unlock_irq(&intelhaddata->had_spinlock);
1388 return;
1389
1390 }
1391
1392
1393 had_enable_audio(intelhaddata, false);
1394
1395 intelhaddata->connected = false;
1396 dev_dbg(intelhaddata->dev,
1397 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1398 __func__, __LINE__);
1399 spin_unlock_irq(&intelhaddata->had_spinlock);
1400
1401 kfree(intelhaddata->chmap->chmap);
1402 intelhaddata->chmap->chmap = NULL;
1403
1404
1405 substream = had_substream_get(intelhaddata);
1406 if (substream) {
1407 snd_pcm_stop_xrun(substream);
1408 had_substream_put(intelhaddata);
1409 }
1410
1411 snd_jack_report(intelhaddata->jack, 0);
1412}
1413
1414
1415
1416
1417
1418static int had_iec958_info(struct snd_kcontrol *kcontrol,
1419 struct snd_ctl_elem_info *uinfo)
1420{
1421 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1422 uinfo->count = 1;
1423 return 0;
1424}
1425
1426static int had_iec958_get(struct snd_kcontrol *kcontrol,
1427 struct snd_ctl_elem_value *ucontrol)
1428{
1429 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1430
1431 mutex_lock(&intelhaddata->mutex);
1432 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1433 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1434 ucontrol->value.iec958.status[2] =
1435 (intelhaddata->aes_bits >> 16) & 0xff;
1436 ucontrol->value.iec958.status[3] =
1437 (intelhaddata->aes_bits >> 24) & 0xff;
1438 mutex_unlock(&intelhaddata->mutex);
1439 return 0;
1440}
1441
1442static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1443 struct snd_ctl_elem_value *ucontrol)
1444{
1445 ucontrol->value.iec958.status[0] = 0xff;
1446 ucontrol->value.iec958.status[1] = 0xff;
1447 ucontrol->value.iec958.status[2] = 0xff;
1448 ucontrol->value.iec958.status[3] = 0xff;
1449 return 0;
1450}
1451
1452static int had_iec958_put(struct snd_kcontrol *kcontrol,
1453 struct snd_ctl_elem_value *ucontrol)
1454{
1455 unsigned int val;
1456 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1457 int changed = 0;
1458
1459 val = (ucontrol->value.iec958.status[0] << 0) |
1460 (ucontrol->value.iec958.status[1] << 8) |
1461 (ucontrol->value.iec958.status[2] << 16) |
1462 (ucontrol->value.iec958.status[3] << 24);
1463 mutex_lock(&intelhaddata->mutex);
1464 if (intelhaddata->aes_bits != val) {
1465 intelhaddata->aes_bits = val;
1466 changed = 1;
1467 }
1468 mutex_unlock(&intelhaddata->mutex);
1469 return changed;
1470}
1471
1472static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1473 struct snd_ctl_elem_info *uinfo)
1474{
1475 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1476 uinfo->count = HDMI_MAX_ELD_BYTES;
1477 return 0;
1478}
1479
1480static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1481 struct snd_ctl_elem_value *ucontrol)
1482{
1483 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1484
1485 mutex_lock(&intelhaddata->mutex);
1486 memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1487 HDMI_MAX_ELD_BYTES);
1488 mutex_unlock(&intelhaddata->mutex);
1489 return 0;
1490}
1491
1492static const struct snd_kcontrol_new had_controls[] = {
1493 {
1494 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1495 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1496 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1497 .info = had_iec958_info,
1498 .get = had_iec958_mask_get,
1499 },
1500 {
1501 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1502 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1503 .info = had_iec958_info,
1504 .get = had_iec958_get,
1505 .put = had_iec958_put,
1506 },
1507 {
1508 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1509 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1510 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1511 .name = "ELD",
1512 .info = had_ctl_eld_info,
1513 .get = had_ctl_eld_get,
1514 },
1515};
1516
1517
1518
1519
1520static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1521{
1522 struct snd_intelhad *ctx = dev_id;
1523 u32 audio_stat;
1524
1525
1526 audio_stat = had_read_register_raw(ctx, AUD_HDMI_STATUS);
1527
1528 if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1529 had_write_register_raw(ctx, AUD_HDMI_STATUS,
1530 HDMI_AUDIO_UNDERRUN);
1531 had_process_buffer_underrun(ctx);
1532 }
1533
1534 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1535 had_write_register_raw(ctx, AUD_HDMI_STATUS,
1536 HDMI_AUDIO_BUFFER_DONE);
1537 had_process_buffer_done(ctx);
1538 }
1539
1540 return IRQ_HANDLED;
1541}
1542
1543
1544
1545
1546static void notify_audio_lpe(struct platform_device *pdev)
1547{
1548 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
1549
1550 schedule_work(&ctx->hdmi_audio_wq);
1551}
1552
1553
1554static void had_audio_wq(struct work_struct *work)
1555{
1556 struct snd_intelhad *ctx =
1557 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1558 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1559
1560 pm_runtime_get_sync(ctx->dev);
1561 mutex_lock(&ctx->mutex);
1562 if (!pdata->hdmi_connected) {
1563 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n",
1564 __func__);
1565 memset(ctx->eld, 0, sizeof(ctx->eld));
1566 had_process_hot_unplug(ctx);
1567 } else {
1568 struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld;
1569
1570 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1571 __func__, eld->port_id, pdata->tmds_clock_speed);
1572
1573 switch (eld->pipe_id) {
1574 case 0:
1575 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1576 break;
1577 case 1:
1578 ctx->had_config_offset = AUDIO_HDMI_CONFIG_B;
1579 break;
1580 case 2:
1581 ctx->had_config_offset = AUDIO_HDMI_CONFIG_C;
1582 break;
1583 default:
1584 dev_dbg(ctx->dev, "Invalid pipe %d\n",
1585 eld->pipe_id);
1586 break;
1587 }
1588
1589 memcpy(ctx->eld, eld->eld_data, sizeof(ctx->eld));
1590
1591 ctx->dp_output = pdata->dp_output;
1592 ctx->tmds_clock_speed = pdata->tmds_clock_speed;
1593 ctx->link_rate = pdata->link_rate;
1594
1595 had_process_hot_plug(ctx);
1596
1597
1598 had_process_mode_change(ctx);
1599 }
1600 mutex_unlock(&ctx->mutex);
1601 pm_runtime_mark_last_busy(ctx->dev);
1602 pm_runtime_put_autosuspend(ctx->dev);
1603}
1604
1605
1606
1607
1608static int had_create_jack(struct snd_intelhad *ctx)
1609{
1610 int err;
1611
1612 err = snd_jack_new(ctx->card, "HDMI/DP", SND_JACK_AVOUT, &ctx->jack,
1613 true, false);
1614 if (err < 0)
1615 return err;
1616 ctx->jack->private_data = ctx;
1617 return 0;
1618}
1619
1620
1621
1622
1623
1624static int hdmi_lpe_audio_runtime_suspend(struct device *dev)
1625{
1626 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1627 struct snd_pcm_substream *substream;
1628
1629 substream = had_substream_get(ctx);
1630 if (substream) {
1631 snd_pcm_suspend(substream);
1632 had_substream_put(ctx);
1633 }
1634
1635 return 0;
1636}
1637
1638static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
1639{
1640 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1641 int err;
1642
1643 err = hdmi_lpe_audio_runtime_suspend(dev);
1644 if (!err)
1645 snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D3hot);
1646 return err;
1647}
1648
1649static int hdmi_lpe_audio_runtime_resume(struct device *dev)
1650{
1651 pm_runtime_mark_last_busy(dev);
1652 return 0;
1653}
1654
1655static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
1656{
1657 struct snd_intelhad *ctx = dev_get_drvdata(dev);
1658
1659 hdmi_lpe_audio_runtime_resume(dev);
1660 snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D0);
1661 return 0;
1662}
1663
1664
1665static void hdmi_lpe_audio_free(struct snd_card *card)
1666{
1667 struct snd_intelhad *ctx = card->private_data;
1668
1669 cancel_work_sync(&ctx->hdmi_audio_wq);
1670
1671 if (ctx->mmio_start)
1672 iounmap(ctx->mmio_start);
1673 if (ctx->irq >= 0)
1674 free_irq(ctx->irq, ctx);
1675}
1676
1677
1678
1679
1680
1681
1682
1683static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1684{
1685 struct snd_card *card;
1686 struct snd_intelhad *ctx;
1687 struct snd_pcm *pcm;
1688 struct intel_hdmi_lpe_audio_pdata *pdata;
1689 int irq;
1690 struct resource *res_mmio;
1691 int i, ret;
1692
1693 pdata = pdev->dev.platform_data;
1694 if (!pdata) {
1695 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1696 return -EINVAL;
1697 }
1698
1699
1700 irq = platform_get_irq(pdev, 0);
1701 if (irq < 0) {
1702 dev_err(&pdev->dev, "Could not get irq resource\n");
1703 return -ENODEV;
1704 }
1705
1706 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1707 if (!res_mmio) {
1708 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1709 return -ENXIO;
1710 }
1711
1712
1713 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1714 THIS_MODULE, sizeof(*ctx), &card);
1715 if (ret)
1716 return ret;
1717
1718 ctx = card->private_data;
1719 spin_lock_init(&ctx->had_spinlock);
1720 mutex_init(&ctx->mutex);
1721 ctx->connected = false;
1722 ctx->dev = &pdev->dev;
1723 ctx->card = card;
1724 ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF;
1725 strcpy(card->driver, INTEL_HAD);
1726 strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1727 strcpy(card->longname, "Intel HDMI/DP LPE Audio");
1728
1729 ctx->irq = -1;
1730 ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5;
1731 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1732
1733 card->private_free = hdmi_lpe_audio_free;
1734
1735
1736 ctx->had_config_offset = AUDIO_HDMI_CONFIG_A;
1737
1738 platform_set_drvdata(pdev, ctx);
1739
1740 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1741 __func__, (unsigned int)res_mmio->start,
1742 (unsigned int)res_mmio->end);
1743
1744 ctx->mmio_start = ioremap_nocache(res_mmio->start,
1745 (size_t)(resource_size(res_mmio)));
1746 if (!ctx->mmio_start) {
1747 dev_err(&pdev->dev, "Could not get ioremap\n");
1748 ret = -EACCES;
1749 goto err;
1750 }
1751
1752
1753 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1754 pdev->name, ctx);
1755 if (ret < 0) {
1756 dev_err(&pdev->dev, "request_irq failed\n");
1757 goto err;
1758 }
1759
1760 ctx->irq = irq;
1761
1762 ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS,
1763 MAX_CAP_STREAMS, &pcm);
1764 if (ret)
1765 goto err;
1766
1767
1768 pcm->private_data = ctx;
1769 pcm->info_flags = 0;
1770 strncpy(pcm->name, card->shortname, strlen(card->shortname));
1771
1772 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1773
1774
1775 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1776 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1777
1778
1779
1780
1781 snd_pcm_lib_preallocate_pages_for_all(pcm,
1782 SNDRV_DMA_TYPE_DEV, NULL,
1783 HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER);
1784
1785
1786 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1787 ret = snd_ctl_add(card, snd_ctl_new1(&had_controls[i], ctx));
1788 if (ret < 0)
1789 goto err;
1790 }
1791
1792 init_channel_allocations();
1793
1794
1795 ret = had_register_chmap_ctls(ctx, pcm);
1796 if (ret < 0)
1797 goto err;
1798
1799 ret = had_create_jack(ctx);
1800 if (ret < 0)
1801 goto err;
1802
1803 ret = snd_card_register(card);
1804 if (ret)
1805 goto err;
1806
1807 spin_lock_irq(&pdata->lpe_audio_slock);
1808 pdata->notify_audio_lpe = notify_audio_lpe;
1809 pdata->notify_pending = false;
1810 spin_unlock_irq(&pdata->lpe_audio_slock);
1811
1812
1813
1814
1815
1816 pm_runtime_use_autosuspend(&pdev->dev);
1817 pm_runtime_mark_last_busy(&pdev->dev);
1818 pm_runtime_set_active(&pdev->dev);
1819
1820 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1821 schedule_work(&ctx->hdmi_audio_wq);
1822
1823 return 0;
1824
1825err:
1826 snd_card_free(card);
1827 return ret;
1828}
1829
1830
1831
1832
1833
1834
1835static int hdmi_lpe_audio_remove(struct platform_device *pdev)
1836{
1837 struct snd_intelhad *ctx = platform_get_drvdata(pdev);
1838
1839 snd_card_free(ctx->card);
1840 return 0;
1841}
1842
1843static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1844 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1845 SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend,
1846 hdmi_lpe_audio_runtime_resume, NULL)
1847};
1848
1849static struct platform_driver hdmi_lpe_audio_driver = {
1850 .driver = {
1851 .name = "hdmi-lpe-audio",
1852 .pm = &hdmi_lpe_audio_pm,
1853 },
1854 .probe = hdmi_lpe_audio_probe,
1855 .remove = hdmi_lpe_audio_remove,
1856};
1857
1858module_platform_driver(hdmi_lpe_audio_driver);
1859MODULE_ALIAS("platform:hdmi_lpe_audio");
1860
1861MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1862MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1863MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1864MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1865MODULE_DESCRIPTION("Intel HDMI Audio driver");
1866MODULE_LICENSE("GPL v2");
1867MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
1868