LXR linux/arch/arm/mach-omap2/prm-regbits-34xx.h

   1/*
   2 * OMAP3430 Power/Reset Management register bits
   3 *
   4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5 * Copyright (C) 2007-2008 Nokia Corporation
   6 *
   7 * Written by Paul Walmsley
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
  14#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
  15
  16
  17#include "prm3xxx.h"
  18
  19#define OMAP3430_ERROROFFSET_MASK                       (0xff << 24)
  20#define OMAP3430_ERRORGAIN_MASK                         (0xff << 16)
  21#define OMAP3430_INITVOLTAGE_MASK                       (0xff << 8)
  22#define OMAP3430_TIMEOUTEN_MASK                         (1 << 3)
  23#define OMAP3430_INITVDD_MASK                           (1 << 2)
  24#define OMAP3430_FORCEUPDATE_MASK                       (1 << 1)
  25#define OMAP3430_VPENABLE_MASK                          (1 << 0)
  26#define OMAP3430_SMPSWAITTIMEMIN_SHIFT                  8
  27#define OMAP3430_VSTEPMIN_SHIFT                         0
  28#define OMAP3430_SMPSWAITTIMEMAX_SHIFT                  8
  29#define OMAP3430_VSTEPMAX_SHIFT                         0
  30#define OMAP3430_VDDMAX_SHIFT                           24
  31#define OMAP3430_VDDMIN_SHIFT                           16
  32#define OMAP3430_TIMEOUT_SHIFT                          0
  33#define OMAP3430_VPVOLTAGE_MASK                         (0xff << 0)
  34#define OMAP3430_EN_PER_SHIFT                           7
  35#define OMAP3430_LOGICSTATEST_MASK                      (1 << 2)
  36#define OMAP3430_LASTLOGICSTATEENTERED_MASK             (1 << 2)
  37#define OMAP3430_LASTPOWERSTATEENTERED_MASK             (0x3 << 0)
  38#define OMAP3430_GRPSEL_MCBSP5_MASK                     (1 << 10)
  39#define OMAP3430_GRPSEL_MCBSP1_MASK                     (1 << 9)
  40#define OMAP3630_GRPSEL_UART4_MASK                      (1 << 18)
  41#define OMAP3430_GRPSEL_GPIO6_MASK                      (1 << 17)
  42#define OMAP3430_GRPSEL_GPIO5_MASK                      (1 << 16)
  43#define OMAP3430_GRPSEL_GPIO4_MASK                      (1 << 15)
  44#define OMAP3430_GRPSEL_GPIO3_MASK                      (1 << 14)
  45#define OMAP3430_GRPSEL_GPIO2_MASK                      (1 << 13)
  46#define OMAP3430_GRPSEL_UART3_MASK                      (1 << 11)
  47#define OMAP3430_GRPSEL_GPT8_MASK                       (1 << 9)
  48#define OMAP3430_GRPSEL_GPT7_MASK                       (1 << 8)
  49#define OMAP3430_GRPSEL_GPT6_MASK                       (1 << 7)
  50#define OMAP3430_GRPSEL_GPT5_MASK                       (1 << 6)
  51#define OMAP3430_GRPSEL_MCBSP4_MASK                     (1 << 2)
  52#define OMAP3430_GRPSEL_MCBSP3_MASK                     (1 << 1)
  53#define OMAP3430_GRPSEL_MCBSP2_MASK                     (1 << 0)
  54#define OMAP3430_GRPSEL_GPIO1_MASK                      (1 << 3)
  55#define OMAP3430_GRPSEL_GPT12_MASK                      (1 << 1)
  56#define OMAP3430_GRPSEL_GPT1_MASK                       (1 << 0)
  57#define OMAP3430_RST3_IVA2_MASK                         (1 << 2)
  58#define OMAP3430_RST2_IVA2_MASK                         (1 << 1)
  59#define OMAP3430_RST1_IVA2_MASK                         (1 << 0)
  60#define OMAP3430_L2FLATMEMONSTATE_MASK                  (0x3 << 22)
  61#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK          (0x3 << 20)
  62#define OMAP3430_L1FLATMEMONSTATE_MASK                  (0x3 << 18)
  63#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK          (0x3 << 16)
  64#define OMAP3430_L2FLATMEMRETSTATE_MASK                 (1 << 11)
  65#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK         (1 << 10)
  66#define OMAP3430_L1FLATMEMRETSTATE_MASK                 (1 << 9)
  67#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK         (1 << 8)
  68#define OMAP3430_L2FLATMEMSTATEST_MASK                  (0x3 << 10)
  69#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK          (0x3 << 8)
  70#define OMAP3430_L1FLATMEMSTATEST_MASK                  (0x3 << 6)
  71#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK          (0x3 << 4)
  72#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK                 (0x3 << 10)
  73#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK         (0x3 << 8)
  74#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT            25
  75#define OMAP3430_VP2_TRANXDONE_ST_MASK                  (1 << 21)
  76#define OMAP3430_VP1_TRANXDONE_ST_MASK                  (1 << 15)
  77#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT   8
  78#define OMAP3430_MPU_DPLL_ST_SHIFT                      7
  79#define OMAP3430_PERIPH_DPLL_ST_SHIFT                   6
  80#define OMAP3430_CORE_DPLL_ST_SHIFT                     5
  81#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT              25
  82#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT     8
  83#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT                        7
  84#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT                     6
  85#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT                       5
  86#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT              5
  87#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT             2
  88#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK         (1 << 1)
  89#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK              (1 << 0)
  90#define OMAP3430_LASTMEM2STATEENTERED_MASK              (0x3 << 6)
  91#define OMAP3430_LASTMEM1STATEENTERED_MASK              (0x3 << 4)
  92#define OMAP3430_EN_IO_CHAIN_MASK                       (1 << 16)
  93#define OMAP3430_EN_IO_MASK                             (1 << 8)
  94#define OMAP3430_EN_GPIO1_MASK                          (1 << 3)
  95#define OMAP3430_ST_IO_CHAIN_MASK                       (1 << 16)
  96#define OMAP3430_ST_IO_MASK                             (1 << 8)
  97#define OMAP3430_SYS_CLKIN_SEL_SHIFT                    0
  98#define OMAP3430_SYS_CLKIN_SEL_WIDTH                    3
  99#define OMAP3430_CLKOUT_EN_SHIFT                        7
 100#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK                (1 << 0)
 101#define OMAP3430ES2_SAVEANDRESTORE_SHIFT                4
 102#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT               16
 103#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK                (0x7f << 16)
 104#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT               0
 105#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK                (0x7f << 0)
 106#define OMAP3430_VOLRA1_MASK                            (0xff << 16)
 107#define OMAP3430_VOLRA0_MASK                            (0xff << 0)
 108#define OMAP3430_CMDRA1_MASK                            (0xff << 16)
 109#define OMAP3430_CMDRA0_MASK                            (0xff << 0)
 110#define OMAP3430_VC_CMD_ON_SHIFT                        24
 111#define OMAP3430_VC_CMD_ON_MASK                         (0xFF << 24)
 112#define OMAP3430_VC_CMD_ONLP_SHIFT                      16
 113#define OMAP3430_VC_CMD_RET_SHIFT                       8
 114#define OMAP3430_VC_CMD_OFF_SHIFT                       0
 115#define OMAP3430_SREN_MASK                              (1 << 4)
 116#define OMAP3430_HSEN_MASK                              (1 << 3)
 117#define OMAP3430_MCODE_MASK                             (0x7 << 0)
 118#define OMAP3430_VALID_MASK                             (1 << 24)
 119#define OMAP3430_DATA_SHIFT                             16
 120#define OMAP3430_REGADDR_SHIFT                          8
 121#define OMAP3430_SLAVEADDR_SHIFT                        0
 122#define OMAP3430_ICECRUSHER_RST_SHIFT                   10
 123#define OMAP3430_ICEPICK_RST_SHIFT                      9
 124#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT         8
 125#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT         7
 126#define OMAP3430_EXTERNAL_WARM_RST_SHIFT                6
 127#define OMAP3430_SECURE_WD_RST_SHIFT                    5
 128#define OMAP3430_MPU_WD_RST_SHIFT                       4
 129#define OMAP3430_SECURITY_VIOL_RST_SHIFT                3
 130#define OMAP3430_GLOBAL_SW_RST_SHIFT                    1
 131#define OMAP3430_GLOBAL_COLD_RST_SHIFT                  0
 132#define OMAP3430_GLOBAL_COLD_RST_MASK                   (1 << 0)
 133#define OMAP3430_PRM_VOLTCTRL_SEL_VMODE                 (1 << 4)
 134#define OMAP3430_PRM_VOLTCTRL_SEL_OFF                   (1 << 3)
 135#define OMAP3430_PRM_VOLTCTRL_AUTO_OFF                  (1 << 2)
 136#define OMAP3430_PRM_VOLTCTRL_AUTO_RET                  (1 << 1)
 137#define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP                (1 << 0)
 138#define OMAP3430_SETUP_TIME2_MASK                       (0xffff << 16)
 139#define OMAP3430_SETUP_TIME1_MASK                       (0xffff << 0)
 140#define OMAP3430_PRM_POLCTRL_OFFMODE_POL                (1 << 3)
 141#define OMAP3430_PRM_POLCTRL_CLKOUT_POL                 (1 << 2)
 142#define OMAP3430_PRM_POLCTRL_CLKREQ_POL                 (1 << 1)
 143#define OMAP3430_PRM_POLCTRL_EXTVOL_POL                 (1 << 0)
 144#endif
 145