LXR linux/arch/blackfin/include/asm/dpmc.h

   1/*
   2 * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
   3 *
   4 * Copyright (C) 2004-2009 Analog Device Inc.
   5 *
   6 * Licensed under the GPL-2
   7 */
   8
   9#ifndef _BLACKFIN_DPMC_H_
  10#define _BLACKFIN_DPMC_H_
  11
  12#ifdef __ASSEMBLY__
  13#define PM_REG0  R7
  14#define PM_REG1  R6
  15#define PM_REG2  R5
  16#define PM_REG3  R4
  17#define PM_REG4  R3
  18#define PM_REG5  R2
  19#define PM_REG6  R1
  20#define PM_REG7  R0
  21#define PM_REG8  P5
  22#define PM_REG9  P4
  23#define PM_REG10 P3
  24#define PM_REG11 P2
  25#define PM_REG12 P1
  26#define PM_REG13 P0
  27
  28#define PM_REGSET0  R7:7
  29#define PM_REGSET1  R7:6
  30#define PM_REGSET2  R7:5
  31#define PM_REGSET3  R7:4
  32#define PM_REGSET4  R7:3
  33#define PM_REGSET5  R7:2
  34#define PM_REGSET6  R7:1
  35#define PM_REGSET7  R7:0
  36#define PM_REGSET8  R7:0, P5:5
  37#define PM_REGSET9  R7:0, P5:4
  38#define PM_REGSET10 R7:0, P5:3
  39#define PM_REGSET11 R7:0, P5:2
  40#define PM_REGSET12 R7:0, P5:1
  41#define PM_REGSET13 R7:0, P5:0
  42
  43#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
  44#define _PM_POP(n, x, w, base)  w[FP + ((x) - (base))] = PM_REG##n;
  45#define PM_PUSH_SYNC(n)         [--sp] = (PM_REGSET##n);
  46#define PM_POP_SYNC(n)          (PM_REGSET##n) = [sp++];
  47#define PM_PUSH(n, x)           PM_REG##n = [FP++];
  48#define PM_POP(n, x)            [FP--] = PM_REG##n;
  49#define PM_CORE_PUSH(n, x)      _PM_PUSH(n, x, , COREMMR_BASE)
  50#define PM_CORE_POP(n, x)       _PM_POP(n, x, , COREMMR_BASE)
  51#define PM_SYS_PUSH(n, x)       _PM_PUSH(n, x, , SYSMMR_BASE)
  52#define PM_SYS_POP(n, x)        _PM_POP(n, x, , SYSMMR_BASE)
  53#define PM_SYS_PUSH16(n, x)     _PM_PUSH(n, x, w, SYSMMR_BASE)
  54#define PM_SYS_POP16(n, x)      _PM_POP(n, x, w, SYSMMR_BASE)
  55
  56        .macro bfin_init_pm_bench_cycles
  57#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
  58        R4 = 0;
  59        CYCLES = R4;
  60        CYCLES2 = R4;
  61        R4 = SYSCFG;
  62        BITSET(R4, 1);
  63        SYSCFG = R4;
  64#endif
  65        .endm
  66
  67        .macro bfin_cpu_reg_save
  68        /*
  69         * Save the core regs early so we can blow them away when
  70         * saving/restoring MMR states
  71         */
  72        [--sp] = (R7:0, P5:0);
  73        [--sp] = fp;
  74        [--sp] = usp;
  75
  76        [--sp] = i0;
  77        [--sp] = i1;
  78        [--sp] = i2;
  79        [--sp] = i3;
  80
  81        [--sp] = m0;
  82        [--sp] = m1;
  83        [--sp] = m2;
  84        [--sp] = m3;
  85
  86        [--sp] = l0;
  87        [--sp] = l1;
  88        [--sp] = l2;
  89        [--sp] = l3;
  90
  91        [--sp] = b0;
  92        [--sp] = b1;
  93        [--sp] = b2;
  94        [--sp] = b3;
  95        [--sp] = a0.x;
  96        [--sp] = a0.w;
  97        [--sp] = a1.x;
  98        [--sp] = a1.w;
  99
 100        [--sp] = LC0;
 101        [--sp] = LC1;
 102        [--sp] = LT0;
 103        [--sp] = LT1;
 104        [--sp] = LB0;
 105        [--sp] = LB1;
 106
 107        /* We can't push RETI directly as that'll change IPEND[4] */
 108        r7 = RETI;
 109        [--sp] = RETS;
 110        [--sp] = ASTAT;
 111#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
 112        [--sp] = CYCLES;
 113        [--sp] = CYCLES2;
 114#endif
 115        [--sp] = SYSCFG;
 116        [--sp] = RETX;
 117        [--sp] = SEQSTAT;
 118        [--sp] = r7;
 119
 120        /* Save first func arg in M3 */
 121        M3 = R0;
 122        .endm
 123
 124        .macro bfin_cpu_reg_restore
 125        /* Restore Core Registers */
 126        RETI = [sp++];
 127        SEQSTAT = [sp++];
 128        RETX = [sp++];
 129        SYSCFG = [sp++];
 130#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
 131        CYCLES2 = [sp++];
 132        CYCLES = [sp++];
 133#endif
 134        ASTAT = [sp++];
 135        RETS = [sp++];
 136
 137        LB1 = [sp++];
 138        LB0 = [sp++];
 139        LT1 = [sp++];
 140        LT0 = [sp++];
 141        LC1 = [sp++];
 142        LC0 = [sp++];
 143
 144        a1.w = [sp++];
 145        a1.x = [sp++];
 146        a0.w = [sp++];
 147        a0.x = [sp++];
 148        b3 = [sp++];
 149        b2 = [sp++];
 150        b1 = [sp++];
 151        b0 = [sp++];
 152
 153        l3 = [sp++];
 154        l2 = [sp++];
 155        l1 = [sp++];
 156        l0 = [sp++];
 157
 158        m3 = [sp++];
 159        m2 = [sp++];
 160        m1 = [sp++];
 161        m0 = [sp++];
 162
 163        i3 = [sp++];
 164        i2 = [sp++];
 165        i1 = [sp++];
 166        i0 = [sp++];
 167
 168        usp = [sp++];
 169        fp = [sp++];
 170        (R7:0, P5:0) = [sp++];
 171
 172        .endm
 173
 174        .macro bfin_sys_mmr_save
 175        /* Save system MMRs */
 176        FP.H = hi(SYSMMR_BASE);
 177        FP.L = lo(SYSMMR_BASE);
 178#ifdef SIC_IMASK0
 179        PM_SYS_PUSH(0, SIC_IMASK0)
 180        PM_SYS_PUSH(1, SIC_IMASK1)
 181# ifdef SIC_IMASK2
 182        PM_SYS_PUSH(2, SIC_IMASK2)
 183# endif
 184#else
 185# ifdef SIC_IMASK
 186        PM_SYS_PUSH(0, SIC_IMASK)
 187# endif
 188#endif
 189
 190#ifdef SIC_IAR0
 191        PM_SYS_PUSH(3, SIC_IAR0)
 192        PM_SYS_PUSH(4, SIC_IAR1)
 193        PM_SYS_PUSH(5, SIC_IAR2)
 194#endif
 195#ifdef SIC_IAR3
 196        PM_SYS_PUSH(6, SIC_IAR3)
 197#endif
 198#ifdef SIC_IAR4
 199        PM_SYS_PUSH(7, SIC_IAR4)
 200        PM_SYS_PUSH(8, SIC_IAR5)
 201        PM_SYS_PUSH(9, SIC_IAR6)
 202#endif
 203#ifdef SIC_IAR7
 204        PM_SYS_PUSH(10, SIC_IAR7)
 205#endif
 206#ifdef SIC_IAR8
 207        PM_SYS_PUSH(11, SIC_IAR8)
 208        PM_SYS_PUSH(12, SIC_IAR9)
 209        PM_SYS_PUSH(13, SIC_IAR10)
 210#endif
 211        PM_PUSH_SYNC(13)
 212#ifdef SIC_IAR11
 213        PM_SYS_PUSH(0, SIC_IAR11)
 214#endif
 215
 216#ifdef SIC_IWR
 217        PM_SYS_PUSH(1, SIC_IWR)
 218#endif
 219#ifdef SIC_IWR0
 220        PM_SYS_PUSH(1, SIC_IWR0)
 221#endif
 222#ifdef SIC_IWR1
 223        PM_SYS_PUSH(2, SIC_IWR1)
 224#endif
 225#ifdef SIC_IWR2
 226        PM_SYS_PUSH(3, SIC_IWR2)
 227#endif
 228
 229#ifdef PINT0_ASSIGN
 230        PM_SYS_PUSH(4, PINT0_MASK_SET)
 231        PM_SYS_PUSH(5, PINT1_MASK_SET)
 232        PM_SYS_PUSH(6, PINT2_MASK_SET)
 233        PM_SYS_PUSH(7, PINT3_MASK_SET)
 234        PM_SYS_PUSH(8, PINT0_ASSIGN)
 235        PM_SYS_PUSH(9, PINT1_ASSIGN)
 236        PM_SYS_PUSH(10, PINT2_ASSIGN)
 237        PM_SYS_PUSH(11, PINT3_ASSIGN)
 238        PM_SYS_PUSH(12, PINT0_INVERT_SET)
 239        PM_SYS_PUSH(13, PINT1_INVERT_SET)
 240        PM_PUSH_SYNC(13)
 241        PM_SYS_PUSH(0, PINT2_INVERT_SET)
 242        PM_SYS_PUSH(1, PINT3_INVERT_SET)
 243        PM_SYS_PUSH(2, PINT0_EDGE_SET)
 244        PM_SYS_PUSH(3, PINT1_EDGE_SET)
 245        PM_SYS_PUSH(4, PINT2_EDGE_SET)
 246        PM_SYS_PUSH(5, PINT3_EDGE_SET)
 247#endif
 248
 249#ifdef SYSCR
 250        PM_SYS_PUSH16(6, SYSCR)
 251#endif
 252
 253#ifdef EBIU_AMGCTL
 254        PM_SYS_PUSH16(7, EBIU_AMGCTL)
 255        PM_SYS_PUSH(8, EBIU_AMBCTL0)
 256        PM_SYS_PUSH(9, EBIU_AMBCTL1)
 257#endif
 258#ifdef EBIU_FCTL
 259        PM_SYS_PUSH(10, EBIU_MBSCTL)
 260        PM_SYS_PUSH(11, EBIU_MODE)
 261        PM_SYS_PUSH(12, EBIU_FCTL)
 262        PM_PUSH_SYNC(12)
 263#else
 264        PM_PUSH_SYNC(9)
 265#endif
 266        .endm
 267
 268
 269        .macro bfin_sys_mmr_restore
 270/* Restore System MMRs */
 271        FP.H = hi(SYSMMR_BASE);
 272        FP.L = lo(SYSMMR_BASE);
 273
 274#ifdef EBIU_FCTL
 275        PM_POP_SYNC(12)
 276        PM_SYS_POP(12, EBIU_FCTL)
 277        PM_SYS_POP(11, EBIU_MODE)
 278        PM_SYS_POP(10, EBIU_MBSCTL)
 279#else
 280        PM_POP_SYNC(9)
 281#endif
 282
 283#ifdef EBIU_AMGCTL
 284        PM_SYS_POP(9, EBIU_AMBCTL1)
 285        PM_SYS_POP(8, EBIU_AMBCTL0)
 286        PM_SYS_POP16(7, EBIU_AMGCTL)
 287#endif
 288
 289#ifdef SYSCR
 290        PM_SYS_POP16(6, SYSCR)
 291#endif
 292
 293#ifdef PINT0_ASSIGN
 294        PM_SYS_POP(5, PINT3_EDGE_SET)
 295        PM_SYS_POP(4, PINT2_EDGE_SET)
 296        PM_SYS_POP(3, PINT1_EDGE_SET)
 297        PM_SYS_POP(2, PINT0_EDGE_SET)
 298        PM_SYS_POP(1, PINT3_INVERT_SET)
 299        PM_SYS_POP(0, PINT2_INVERT_SET)
 300        PM_POP_SYNC(13)
 301        PM_SYS_POP(13, PINT1_INVERT_SET)
 302        PM_SYS_POP(12, PINT0_INVERT_SET)
 303        PM_SYS_POP(11, PINT3_ASSIGN)
 304        PM_SYS_POP(10, PINT2_ASSIGN)
 305        PM_SYS_POP(9, PINT1_ASSIGN)
 306        PM_SYS_POP(8, PINT0_ASSIGN)
 307        PM_SYS_POP(7, PINT3_MASK_SET)
 308        PM_SYS_POP(6, PINT2_MASK_SET)
 309        PM_SYS_POP(5, PINT1_MASK_SET)
 310        PM_SYS_POP(4, PINT0_MASK_SET)
 311#endif
 312
 313#ifdef SIC_IWR2
 314        PM_SYS_POP(3, SIC_IWR2)
 315#endif
 316#ifdef SIC_IWR1
 317        PM_SYS_POP(2, SIC_IWR1)
 318#endif
 319#ifdef SIC_IWR0
 320        PM_SYS_POP(1, SIC_IWR0)
 321#endif
 322#ifdef SIC_IWR
 323        PM_SYS_POP(1, SIC_IWR)
 324#endif
 325
 326#ifdef SIC_IAR11
 327        PM_SYS_POP(0, SIC_IAR11)
 328#endif
 329        PM_POP_SYNC(13)
 330#ifdef SIC_IAR8
 331        PM_SYS_POP(13, SIC_IAR10)
 332        PM_SYS_POP(12, SIC_IAR9)
 333        PM_SYS_POP(11, SIC_IAR8)
 334#endif
 335#ifdef SIC_IAR7
 336        PM_SYS_POP(10, SIC_IAR7)
 337#endif
 338#ifdef SIC_IAR6
 339        PM_SYS_POP(9, SIC_IAR6)
 340        PM_SYS_POP(8, SIC_IAR5)
 341        PM_SYS_POP(7, SIC_IAR4)
 342#endif
 343#ifdef SIC_IAR3
 344        PM_SYS_POP(6, SIC_IAR3)
 345#endif
 346#ifdef SIC_IAR0
 347        PM_SYS_POP(5, SIC_IAR2)
 348        PM_SYS_POP(4, SIC_IAR1)
 349        PM_SYS_POP(3, SIC_IAR0)
 350#endif
 351#ifdef SIC_IMASK0
 352# ifdef SIC_IMASK2
 353        PM_SYS_POP(2, SIC_IMASK2)
 354# endif
 355        PM_SYS_POP(1, SIC_IMASK1)
 356        PM_SYS_POP(0, SIC_IMASK0)
 357#else
 358# ifdef SIC_IMASK
 359        PM_SYS_POP(0, SIC_IMASK)
 360# endif
 361#endif
 362        .endm
 363
 364        .macro bfin_core_mmr_save
 365        /* Save Core MMRs */
 366        I0.H = hi(COREMMR_BASE);
 367        I0.L = lo(COREMMR_BASE);
 368        I1 = I0;
 369        I2 = I0;
 370        I3 = I0;
 371        B0 = I0;
 372        B1 = I0;
 373        B2 = I0;
 374        B3 = I0;
 375        I1.L = lo(DCPLB_ADDR0);
 376        I2.L = lo(DCPLB_DATA0);
 377        I3.L = lo(ICPLB_ADDR0);
 378        B0.L = lo(ICPLB_DATA0);
 379        B1.L = lo(EVT2);
 380        B2.L = lo(IMASK);
 381        B3.L = lo(TCNTL);
 382
 383        /* Event Vectors */
 384        FP = B1;
 385        PM_PUSH(0, EVT2)
 386        PM_PUSH(1, EVT3)
 387        FP += 4;        /* EVT4 */
 388        PM_PUSH(2, EVT5)
 389        PM_PUSH(3, EVT6)
 390        PM_PUSH(4, EVT7)
 391        PM_PUSH(5, EVT8)
 392        PM_PUSH_SYNC(5)
 393
 394        PM_PUSH(0, EVT9)
 395        PM_PUSH(1, EVT10)
 396        PM_PUSH(2, EVT11)
 397        PM_PUSH(3, EVT12)
 398        PM_PUSH(4, EVT13)
 399        PM_PUSH(5, EVT14)
 400        PM_PUSH(6, EVT15)
 401
 402        /* CEC */
 403        FP = B2;
 404        PM_PUSH(7, IMASK)
 405        FP += 4;        /* IPEND */
 406        PM_PUSH(8, ILAT)
 407        PM_PUSH(9, IPRIO)
 408
 409        /* Core Timer */
 410        FP = B3;
 411        PM_PUSH(10, TCNTL)
 412        PM_PUSH(11, TPERIOD)
 413        PM_PUSH(12, TSCALE)
 414        PM_PUSH(13, TCOUNT)
 415        PM_PUSH_SYNC(13)
 416
 417        /* Misc non-contiguous registers */
 418        FP = I0;
 419        PM_CORE_PUSH(0, DMEM_CONTROL);
 420        PM_CORE_PUSH(1, IMEM_CONTROL);
 421        PM_CORE_PUSH(2, TBUFCTL);
 422        PM_PUSH_SYNC(2)
 423
 424        /* DCPLB Addr */
 425        FP = I1;
 426        PM_PUSH(0, DCPLB_ADDR0)
 427        PM_PUSH(1, DCPLB_ADDR1)
 428        PM_PUSH(2, DCPLB_ADDR2)
 429        PM_PUSH(3, DCPLB_ADDR3)
 430        PM_PUSH(4, DCPLB_ADDR4)
 431        PM_PUSH(5, DCPLB_ADDR5)
 432        PM_PUSH(6, DCPLB_ADDR6)
 433        PM_PUSH(7, DCPLB_ADDR7)
 434        PM_PUSH(8, DCPLB_ADDR8)
 435        PM_PUSH(9, DCPLB_ADDR9)
 436        PM_PUSH(10, DCPLB_ADDR10)
 437        PM_PUSH(11, DCPLB_ADDR11)
 438        PM_PUSH(12, DCPLB_ADDR12)
 439        PM_PUSH(13, DCPLB_ADDR13)
 440        PM_PUSH_SYNC(13)
 441        PM_PUSH(0, DCPLB_ADDR14)
 442        PM_PUSH(1, DCPLB_ADDR15)
 443
 444        /* DCPLB Data */
 445        FP = I2;
 446        PM_PUSH(2, DCPLB_DATA0)
 447        PM_PUSH(3, DCPLB_DATA1)
 448        PM_PUSH(4, DCPLB_DATA2)
 449        PM_PUSH(5, DCPLB_DATA3)
 450        PM_PUSH(6, DCPLB_DATA4)
 451        PM_PUSH(7, DCPLB_DATA5)
 452        PM_PUSH(8, DCPLB_DATA6)
 453        PM_PUSH(9, DCPLB_DATA7)
 454        PM_PUSH(10, DCPLB_DATA8)
 455        PM_PUSH(11, DCPLB_DATA9)
 456        PM_PUSH(12, DCPLB_DATA10)
 457        PM_PUSH(13, DCPLB_DATA11)
 458        PM_PUSH_SYNC(13)
 459        PM_PUSH(0, DCPLB_DATA12)
 460        PM_PUSH(1, DCPLB_DATA13)
 461        PM_PUSH(2, DCPLB_DATA14)
 462        PM_PUSH(3, DCPLB_DATA15)
 463
 464        /* ICPLB Addr */
 465        FP = I3;
 466        PM_PUSH(4, ICPLB_ADDR0)
 467        PM_PUSH(5, ICPLB_ADDR1)
 468        PM_PUSH(6, ICPLB_ADDR2)
 469        PM_PUSH(7, ICPLB_ADDR3)
 470        PM_PUSH(8, ICPLB_ADDR4)
 471        PM_PUSH(9, ICPLB_ADDR5)
 472        PM_PUSH(10, ICPLB_ADDR6)
 473        PM_PUSH(11, ICPLB_ADDR7)
 474        PM_PUSH(12, ICPLB_ADDR8)
 475        PM_PUSH(13, ICPLB_ADDR9)
 476        PM_PUSH_SYNC(13)
 477        PM_PUSH(0, ICPLB_ADDR10)
 478        PM_PUSH(1, ICPLB_ADDR11)
 479        PM_PUSH(2, ICPLB_ADDR12)
 480        PM_PUSH(3, ICPLB_ADDR13)
 481        PM_PUSH(4, ICPLB_ADDR14)
 482        PM_PUSH(5, ICPLB_ADDR15)
 483
 484        /* ICPLB Data */
 485        FP = B0;
 486        PM_PUSH(6, ICPLB_DATA0)
 487        PM_PUSH(7, ICPLB_DATA1)
 488        PM_PUSH(8, ICPLB_DATA2)
 489        PM_PUSH(9, ICPLB_DATA3)
 490        PM_PUSH(10, ICPLB_DATA4)
 491        PM_PUSH(11, ICPLB_DATA5)
 492        PM_PUSH(12, ICPLB_DATA6)
 493        PM_PUSH(13, ICPLB_DATA7)
 494        PM_PUSH_SYNC(13)
 495        PM_PUSH(0, ICPLB_DATA8)
 496        PM_PUSH(1, ICPLB_DATA9)
 497        PM_PUSH(2, ICPLB_DATA10)
 498        PM_PUSH(3, ICPLB_DATA11)
 499        PM_PUSH(4, ICPLB_DATA12)
 500        PM_PUSH(5, ICPLB_DATA13)
 501        PM_PUSH(6, ICPLB_DATA14)
 502        PM_PUSH(7, ICPLB_DATA15)
 503        PM_PUSH_SYNC(7)
 504        .endm
 505
 506        .macro bfin_core_mmr_restore
 507        /* Restore Core MMRs */
 508        I0.H = hi(COREMMR_BASE);
 509        I0.L = lo(COREMMR_BASE);
 510        I1 = I0;
 511        I2 = I0;
 512        I3 = I0;
 513        B0 = I0;
 514        B1 = I0;
 515        B2 = I0;
 516        B3 = I0;
 517        I1.L = lo(DCPLB_ADDR15);
 518        I2.L = lo(DCPLB_DATA15);
 519        I3.L = lo(ICPLB_ADDR15);
 520        B0.L = lo(ICPLB_DATA15);
 521        B1.L = lo(EVT15);
 522        B2.L = lo(IPRIO);
 523        B3.L = lo(TCOUNT);
 524
 525        /* ICPLB Data */
 526        FP = B0;
 527        PM_POP_SYNC(7)
 528        PM_POP(7, ICPLB_DATA15)
 529        PM_POP(6, ICPLB_DATA14)
 530        PM_POP(5, ICPLB_DATA13)
 531        PM_POP(4, ICPLB_DATA12)
 532        PM_POP(3, ICPLB_DATA11)
 533        PM_POP(2, ICPLB_DATA10)
 534        PM_POP(1, ICPLB_DATA9)
 535        PM_POP(0, ICPLB_DATA8)
 536        PM_POP_SYNC(13)
 537        PM_POP(13, ICPLB_DATA7)
 538        PM_POP(12, ICPLB_DATA6)
 539        PM_POP(11, ICPLB_DATA5)
 540        PM_POP(10, ICPLB_DATA4)
 541        PM_POP(9, ICPLB_DATA3)
 542        PM_POP(8, ICPLB_DATA2)
 543        PM_POP(7, ICPLB_DATA1)
 544        PM_POP(6, ICPLB_DATA0)
 545
 546        /* ICPLB Addr */
 547        FP = I3;
 548        PM_POP(5, ICPLB_ADDR15)
 549        PM_POP(4, ICPLB_ADDR14)
 550        PM_POP(3, ICPLB_ADDR13)
 551        PM_POP(2, ICPLB_ADDR12)
 552        PM_POP(1, ICPLB_ADDR11)
 553        PM_POP(0, ICPLB_ADDR10)
 554        PM_POP_SYNC(13)
 555        PM_POP(13, ICPLB_ADDR9)
 556        PM_POP(12, ICPLB_ADDR8)
 557        PM_POP(11, ICPLB_ADDR7)
 558        PM_POP(10, ICPLB_ADDR6)
 559        PM_POP(9, ICPLB_ADDR5)
 560        PM_POP(8, ICPLB_ADDR4)
 561        PM_POP(7, ICPLB_ADDR3)
 562        PM_POP(6, ICPLB_ADDR2)
 563        PM_POP(5, ICPLB_ADDR1)
 564        PM_POP(4, ICPLB_ADDR0)
 565
 566        /* DCPLB Data */
 567        FP = I2;
 568        PM_POP(3, DCPLB_DATA15)
 569        PM_POP(2, DCPLB_DATA14)
 570        PM_POP(1, DCPLB_DATA13)
 571        PM_POP(0, DCPLB_DATA12)
 572        PM_POP_SYNC(13)
 573        PM_POP(13, DCPLB_DATA11)
 574        PM_POP(12, DCPLB_DATA10)
 575        PM_POP(11, DCPLB_DATA9)
 576        PM_POP(10, DCPLB_DATA8)
 577        PM_POP(9, DCPLB_DATA7)
 578        PM_POP(8, DCPLB_DATA6)
 579        PM_POP(7, DCPLB_DATA5)
 580        PM_POP(6, DCPLB_DATA4)
 581        PM_POP(5, DCPLB_DATA3)
 582        PM_POP(4, DCPLB_DATA2)
 583        PM_POP(3, DCPLB_DATA1)
 584        PM_POP(2, DCPLB_DATA0)
 585
 586        /* DCPLB Addr */
 587        FP = I1;
 588        PM_POP(1, DCPLB_ADDR15)
 589        PM_POP(0, DCPLB_ADDR14)
 590        PM_POP_SYNC(13)
 591        PM_POP(13, DCPLB_ADDR13)
 592        PM_POP(12, DCPLB_ADDR12)
 593        PM_POP(11, DCPLB_ADDR11)
 594        PM_POP(10, DCPLB_ADDR10)
 595        PM_POP(9, DCPLB_ADDR9)
 596        PM_POP(8, DCPLB_ADDR8)
 597        PM_POP(7, DCPLB_ADDR7)
 598        PM_POP(6, DCPLB_ADDR6)
 599        PM_POP(5, DCPLB_ADDR5)
 600        PM_POP(4, DCPLB_ADDR4)
 601        PM_POP(3, DCPLB_ADDR3)
 602        PM_POP(2, DCPLB_ADDR2)
 603        PM_POP(1, DCPLB_ADDR1)
 604        PM_POP(0, DCPLB_ADDR0)
 605
 606
 607        /* Misc non-contiguous registers */
 608
 609        /* icache & dcache will enable later 
 610           drop IMEM_CONTROL, DMEM_CONTROL pop
 611        */
 612        FP = I0;
 613        PM_POP_SYNC(2)
 614        PM_CORE_POP(2, TBUFCTL)
 615        PM_CORE_POP(1, IMEM_CONTROL)
 616        PM_CORE_POP(0, DMEM_CONTROL)
 617
 618        /* Core Timer */
 619        FP = B3;
 620        R0 = 0x1;
 621        [FP - 0xC] = R0;
 622
 623        PM_POP_SYNC(13)
 624        FP = B3;
 625        PM_POP(13, TCOUNT)
 626        PM_POP(12, TSCALE)
 627        PM_POP(11, TPERIOD)
 628        PM_POP(10, TCNTL)
 629
 630        /* CEC */
 631        FP = B2;
 632        PM_POP(9, IPRIO)
 633        PM_POP(8, ILAT)
 634        FP += -4;       /* IPEND */
 635        PM_POP(7, IMASK)
 636
 637        /* Event Vectors */
 638        FP = B1;
 639        PM_POP(6, EVT15)
 640        PM_POP(5, EVT14)
 641        PM_POP(4, EVT13)
 642        PM_POP(3, EVT12)
 643        PM_POP(2, EVT11)
 644        PM_POP(1, EVT10)
 645        PM_POP(0, EVT9)
 646        PM_POP_SYNC(5)
 647        PM_POP(5, EVT8)
 648        PM_POP(4, EVT7)
 649        PM_POP(3, EVT6)
 650        PM_POP(2, EVT5)
 651        FP += -4;       /* EVT4 */
 652        PM_POP(1, EVT3)
 653        PM_POP(0, EVT2)
 654        .endm
 655#endif
 656
 657#include <mach/pll.h>
 658
 659/* PLL_CTL Masks */
 660#define DF                      0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
 661#define PLL_OFF                 0x0002  /* PLL Not Powered */
 662#define STOPCK                  0x0008  /* Core Clock Off */
 663#define PDWN                    0x0020  /* Enter Deep Sleep Mode */
 664#ifdef __ADSPBF539__
 665# define IN_DELAY               0x0014  /* Add 200ps Delay To EBIU Input Latches */
 666# define OUT_DELAY              0x00C0  /* Add 200ps Delay To EBIU Output Signals */
 667#else
 668# define IN_DELAY               0x0040  /* Add 200ps Delay To EBIU Input Latches */
 669# define OUT_DELAY              0x0080  /* Add 200ps Delay To EBIU Output Signals */
 670#endif
 671#define BYPASS                  0x0100  /* Bypass the PLL */
 672#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors */
 673#define SPORT_HYST              0x8000  /* Enable Additional Hysteresis on SPORT Input Pins */
 674#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
 675
 676/* PLL_DIV Masks */
 677#define SSEL                    0x000F  /* System Select */
 678#define CSEL                    0x0030  /* Core Select */
 679#define CSEL_DIV1               0x0000  /* CCLK = VCO / 1 */
 680#define CSEL_DIV2               0x0010  /* CCLK = VCO / 2 */
 681#define CSEL_DIV4               0x0020  /* CCLK = VCO / 4 */
 682#define CSEL_DIV8               0x0030  /* CCLK = VCO / 8 */
 683
 684#define CCLK_DIV1 CSEL_DIV1
 685#define CCLK_DIV2 CSEL_DIV2
 686#define CCLK_DIV4 CSEL_DIV4
 687#define CCLK_DIV8 CSEL_DIV8
 688
 689#define SET_SSEL(x)     ((x) & 0xF)     /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
 690#define SCLK_DIV(x)     (x)             /* SCLK = VCO / x */
 691
 692/* PLL_STAT Masks */
 693#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled */
 694#define FULL_ON                 0x0002  /* Processor In Full On Mode */
 695#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled */
 696#define PLL_LOCKED              0x0020  /* PLL_LOCKCNT Has Been Reached */
 697
 698#define RTCWS                   0x0400  /* RTC/Reset Wake-Up Status */
 699#define CANWS                   0x0800  /* CAN Wake-Up Status */
 700#define USBWS                   0x2000  /* USB Wake-Up Status */
 701#define KPADWS                  0x4000  /* Keypad Wake-Up Status */
 702#define ROTWS                   0x8000  /* Rotary Wake-Up Status */
 703#define GPWS                    0x1000  /* General-Purpose Wake-Up Status */
 704
 705/* VR_CTL Masks */
 706#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
 707#define FREQ                    0x3000  /* Switching Oscillator Frequency For Regulator */
 708#define FREQ_1000               0x3000  /* Switching Frequency Is 1 MHz */
 709#else
 710#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
 711#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
 712#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
 713#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
 714#endif
 715#define HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
 716
 717#define GAIN                    0x000C  /* Voltage Level Gain */
 718#define GAIN_5                  0x0000  /* GAIN = 5 */
 719#define GAIN_10                 0x0004  /* GAIN = 1 */
 720#define GAIN_20                 0x0008  /* GAIN = 2 */
 721#define GAIN_50                 0x000C  /* GAIN = 5 */
 722
 723#define VLEV                    0x00F0  /* Internal Voltage Level */
 724#ifdef __ADSPBF52x__
 725#define VLEV_085                0x0040  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
 726#define VLEV_090                0x0050  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
 727#define VLEV_095                0x0060  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
 728#define VLEV_100                0x0070  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
 729#define VLEV_105                0x0080  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
 730#define VLEV_110                0x0090  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
 731#define VLEV_115                0x00A0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
 732#define VLEV_120                0x00B0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
 733#else
 734#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
 735#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
 736#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
 737#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
 738#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
 739#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
 740#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
 741#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
 742#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
 743#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
 744#endif
 745
 746#ifdef CONFIG_BF60x
 747#define PA15WE                  0x00000001 /* Allow Wake-Up from PA15 */
 748#define PB15WE                  0x00000002 /* Allow Wake-Up from PB15 */
 749#define PC15WE                  0x00000004 /* Allow Wake-Up from PC15 */
 750#define PD06WE                  0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
 751#define PE12WE                  0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
 752#define PG04WE                  0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
 753#define PG13WE                  0x00000040 /* Allow Wake-Up from PG13 */
 754#define USBWE                   0x00000080 /* Allow Wake-Up from (USB) */
 755#else
 756#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
 757#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate */
 758#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate */
 759#define GPWE                    0x0400  /* General-Purpose Wake-Up Enable */
 760#define MXVRWE                  0x0400  /* Enable MXVR Wakeup From Hibernate */
 761#define KPADWE                  0x1000  /* Keypad Wake-Up Enable */
 762#define ROTWE                   0x2000  /* Rotary Wake-Up Enable */
 763#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
 764#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
 765
 766#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
 767#define USBWE                   0x0200  /* Enable USB Wakeup From Hibernate */
 768#else
 769#define USBWE                   0x0800  /* Enable USB Wakeup From Hibernate */
 770#endif
 771#endif
 772
 773#ifndef __ASSEMBLY__
 774
 775void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 776void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
 777void do_hibernate(int wakeup);
 778void set_dram_srfs(void);
 779void unset_dram_srfs(void);
 780
 781#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
 782
 783#ifdef CONFIG_CPU_FREQ
 784#define CPUFREQ_CPU 0
 785#endif
 786struct bfin_dpmc_platform_data {
 787        const unsigned int *tuple_tab;
 788        unsigned short tabsize;
 789        unsigned short vr_settling_time; /* in us */
 790};
 791
 792#endif
 793
 794#endif  /*_BLACKFIN_DPMC_H_*/
 795