1#ifndef __cris_defs_asm_h
2#define __cris_defs_asm_h
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17#ifndef REG_FIELD
18#define REG_FIELD( scope, reg, field, value ) \
19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
20#define REG_FIELD_X_( value, shift ) ((value) << shift)
21#endif
22
23#ifndef REG_STATE
24#define REG_STATE( scope, reg, field, symbolic_value ) \
25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
26#define REG_STATE_X_( k, shift ) (k << shift)
27#endif
28
29#ifndef REG_MASK
30#define REG_MASK( scope, reg, field ) \
31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
33#endif
34
35#ifndef REG_LSB
36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
37#endif
38
39#ifndef REG_BIT
40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
41#endif
42
43#ifndef REG_ADDR
44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
45#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
46#endif
47
48#ifndef REG_ADDR_VECT
49#define REG_ADDR_VECT( scope, inst, reg, index ) \
50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
51 STRIDE_##scope##_##reg )
52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
53 ((inst) + offs + (index) * stride)
54#endif
55
56
57#define reg_cris_rw_gc_cfg___ic___lsb 0
58#define reg_cris_rw_gc_cfg___ic___width 1
59#define reg_cris_rw_gc_cfg___ic___bit 0
60#define reg_cris_rw_gc_cfg___dc___lsb 1
61#define reg_cris_rw_gc_cfg___dc___width 1
62#define reg_cris_rw_gc_cfg___dc___bit 1
63#define reg_cris_rw_gc_cfg___im___lsb 2
64#define reg_cris_rw_gc_cfg___im___width 1
65#define reg_cris_rw_gc_cfg___im___bit 2
66#define reg_cris_rw_gc_cfg___dm___lsb 3
67#define reg_cris_rw_gc_cfg___dm___width 1
68#define reg_cris_rw_gc_cfg___dm___bit 3
69#define reg_cris_rw_gc_cfg___gb___lsb 4
70#define reg_cris_rw_gc_cfg___gb___width 1
71#define reg_cris_rw_gc_cfg___gb___bit 4
72#define reg_cris_rw_gc_cfg___gk___lsb 5
73#define reg_cris_rw_gc_cfg___gk___width 1
74#define reg_cris_rw_gc_cfg___gk___bit 5
75#define reg_cris_rw_gc_cfg___gp___lsb 6
76#define reg_cris_rw_gc_cfg___gp___width 1
77#define reg_cris_rw_gc_cfg___gp___bit 6
78#define reg_cris_rw_gc_cfg_offset 0
79
80
81#define reg_cris_rw_gc_ccs_offset 4
82
83
84#define reg_cris_rw_gc_srs___srs___lsb 0
85#define reg_cris_rw_gc_srs___srs___width 8
86#define reg_cris_rw_gc_srs_offset 8
87
88
89#define reg_cris_rw_gc_nrp_offset 12
90
91
92#define reg_cris_rw_gc_exs_offset 16
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95#define reg_cris_rw_gc_eda_offset 20
96
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98#define reg_cris_rw_gc_r0_offset 32
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101#define reg_cris_rw_gc_r1_offset 36
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104#define reg_cris_rw_gc_r2_offset 40
105
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107#define reg_cris_rw_gc_r3_offset 44
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111#define regk_cris_no 0x00000000
112#define regk_cris_rw_gc_cfg_default 0x00000000
113#define regk_cris_yes 0x00000001
114#endif
115