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12#include <linux/interrupt.h>
13#include <linux/delay.h>
14#include <linux/sched.h>
15#include <linux/sched/clock.h>
16#include <linux/sched_clock.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/timecounter.h>
22#include <asm/cpuinfo.h>
23
24static void __iomem *timer_baseaddr;
25
26static unsigned int freq_div_hz;
27static unsigned int timer_clock_freq;
28
29#define TCSR0 (0x00)
30#define TLR0 (0x04)
31#define TCR0 (0x08)
32#define TCSR1 (0x10)
33#define TLR1 (0x14)
34#define TCR1 (0x18)
35
36#define TCSR_MDT (1<<0)
37#define TCSR_UDT (1<<1)
38#define TCSR_GENT (1<<2)
39#define TCSR_CAPT (1<<3)
40#define TCSR_ARHT (1<<4)
41#define TCSR_LOAD (1<<5)
42#define TCSR_ENIT (1<<6)
43#define TCSR_ENT (1<<7)
44#define TCSR_TINT (1<<8)
45#define TCSR_PWMA (1<<9)
46#define TCSR_ENALL (1<<10)
47
48static unsigned int (*read_fn)(void __iomem *);
49static void (*write_fn)(u32, void __iomem *);
50
51static void timer_write32(u32 val, void __iomem *addr)
52{
53 iowrite32(val, addr);
54}
55
56static unsigned int timer_read32(void __iomem *addr)
57{
58 return ioread32(addr);
59}
60
61static void timer_write32_be(u32 val, void __iomem *addr)
62{
63 iowrite32be(val, addr);
64}
65
66static unsigned int timer_read32_be(void __iomem *addr)
67{
68 return ioread32be(addr);
69}
70
71static inline void xilinx_timer0_stop(void)
72{
73 write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
74 timer_baseaddr + TCSR0);
75}
76
77static inline void xilinx_timer0_start_periodic(unsigned long load_val)
78{
79 if (!load_val)
80 load_val = 1;
81
82 write_fn(load_val, timer_baseaddr + TLR0);
83
84
85 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
86
87
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91
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96
97
98
99
100 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
101 timer_baseaddr + TCSR0);
102}
103
104static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
105{
106 if (!load_val)
107 load_val = 1;
108
109 write_fn(load_val, timer_baseaddr + TLR0);
110
111
112 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
113
114 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
115 timer_baseaddr + TCSR0);
116}
117
118static int xilinx_timer_set_next_event(unsigned long delta,
119 struct clock_event_device *dev)
120{
121 pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
122 xilinx_timer0_start_oneshot(delta);
123 return 0;
124}
125
126static int xilinx_timer_shutdown(struct clock_event_device *evt)
127{
128 pr_info("%s\n", __func__);
129 xilinx_timer0_stop();
130 return 0;
131}
132
133static int xilinx_timer_set_periodic(struct clock_event_device *evt)
134{
135 pr_info("%s\n", __func__);
136 xilinx_timer0_start_periodic(freq_div_hz);
137 return 0;
138}
139
140static struct clock_event_device clockevent_xilinx_timer = {
141 .name = "xilinx_clockevent",
142 .features = CLOCK_EVT_FEAT_ONESHOT |
143 CLOCK_EVT_FEAT_PERIODIC,
144 .shift = 8,
145 .rating = 300,
146 .set_next_event = xilinx_timer_set_next_event,
147 .set_state_shutdown = xilinx_timer_shutdown,
148 .set_state_periodic = xilinx_timer_set_periodic,
149};
150
151static inline void timer_ack(void)
152{
153 write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
154}
155
156static irqreturn_t timer_interrupt(int irq, void *dev_id)
157{
158 struct clock_event_device *evt = &clockevent_xilinx_timer;
159#ifdef CONFIG_HEART_BEAT
160 microblaze_heartbeat();
161#endif
162 timer_ack();
163 evt->event_handler(evt);
164 return IRQ_HANDLED;
165}
166
167static struct irqaction timer_irqaction = {
168 .handler = timer_interrupt,
169 .flags = IRQF_TIMER,
170 .name = "timer",
171 .dev_id = &clockevent_xilinx_timer,
172};
173
174static __init int xilinx_clockevent_init(void)
175{
176 clockevent_xilinx_timer.mult =
177 div_sc(timer_clock_freq, NSEC_PER_SEC,
178 clockevent_xilinx_timer.shift);
179 clockevent_xilinx_timer.max_delta_ns =
180 clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer);
181 clockevent_xilinx_timer.min_delta_ns =
182 clockevent_delta2ns(1, &clockevent_xilinx_timer);
183 clockevent_xilinx_timer.cpumask = cpumask_of(0);
184 clockevents_register_device(&clockevent_xilinx_timer);
185
186 return 0;
187}
188
189static u64 xilinx_clock_read(void)
190{
191 return read_fn(timer_baseaddr + TCR1);
192}
193
194static u64 xilinx_read(struct clocksource *cs)
195{
196
197 return (u64)xilinx_clock_read();
198}
199
200static struct timecounter xilinx_tc = {
201 .cc = NULL,
202};
203
204static u64 xilinx_cc_read(const struct cyclecounter *cc)
205{
206 return xilinx_read(NULL);
207}
208
209static struct cyclecounter xilinx_cc = {
210 .read = xilinx_cc_read,
211 .mask = CLOCKSOURCE_MASK(32),
212 .shift = 8,
213};
214
215static int __init init_xilinx_timecounter(void)
216{
217 xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
218 xilinx_cc.shift);
219
220 timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock());
221
222 return 0;
223}
224
225static struct clocksource clocksource_microblaze = {
226 .name = "xilinx_clocksource",
227 .rating = 300,
228 .read = xilinx_read,
229 .mask = CLOCKSOURCE_MASK(32),
230 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
231};
232
233static int __init xilinx_clocksource_init(void)
234{
235 int ret;
236
237 ret = clocksource_register_hz(&clocksource_microblaze,
238 timer_clock_freq);
239 if (ret) {
240 pr_err("failed to register clocksource");
241 return ret;
242 }
243
244
245 write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
246 timer_baseaddr + TCSR1);
247
248 write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
249
250
251 return init_xilinx_timecounter();
252}
253
254static int __init xilinx_timer_init(struct device_node *timer)
255{
256 struct clk *clk;
257 static int initialized;
258 u32 irq;
259 u32 timer_num = 1;
260 int ret;
261
262 if (initialized)
263 return -EINVAL;
264
265 initialized = 1;
266
267 timer_baseaddr = of_iomap(timer, 0);
268 if (!timer_baseaddr) {
269 pr_err("ERROR: invalid timer base address\n");
270 return -ENXIO;
271 }
272
273 write_fn = timer_write32;
274 read_fn = timer_read32;
275
276 write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
277 if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
278 write_fn = timer_write32_be;
279 read_fn = timer_read32_be;
280 }
281
282 irq = irq_of_parse_and_map(timer, 0);
283 if (irq <= 0) {
284 pr_err("Failed to parse and map irq");
285 return -EINVAL;
286 }
287
288 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
289 if (timer_num) {
290 pr_err("Please enable two timers in HW\n");
291 return -EINVAL;
292 }
293
294 pr_info("%s: irq=%d\n", timer->full_name, irq);
295
296 clk = of_clk_get(timer, 0);
297 if (IS_ERR(clk)) {
298 pr_err("ERROR: timer CCF input clock not found\n");
299
300 of_property_read_u32(timer, "clock-frequency",
301 &timer_clock_freq);
302 } else {
303 timer_clock_freq = clk_get_rate(clk);
304 }
305
306 if (!timer_clock_freq) {
307 pr_err("ERROR: Using CPU clock frequency\n");
308 timer_clock_freq = cpuinfo.cpu_clock_freq;
309 }
310
311 freq_div_hz = timer_clock_freq / HZ;
312
313 ret = setup_irq(irq, &timer_irqaction);
314 if (ret) {
315 pr_err("Failed to setup IRQ");
316 return ret;
317 }
318
319#ifdef CONFIG_HEART_BEAT
320 microblaze_setup_heartbeat();
321#endif
322
323 ret = xilinx_clocksource_init();
324 if (ret)
325 return ret;
326
327 ret = xilinx_clockevent_init();
328 if (ret)
329 return ret;
330
331 sched_clock_register(xilinx_clock_read, 32, timer_clock_freq);
332
333 return 0;
334}
335
336CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
337 xilinx_timer_init);
338
