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12#ifndef _ASM_NILE4_H
13#define _ASM_NILE4_H
14
15#define NILE4_BASE 0xbfa00000
16#define NILE4_SIZE 0x00200000
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22
23#define NILE4_SDRAM0 0x0000
24#define NILE4_SDRAM1 0x0008
25#define NILE4_DCS2 0x0010
26#define NILE4_DCS3 0x0018
27#define NILE4_DCS4 0x0020
28#define NILE4_DCS5 0x0028
29#define NILE4_DCS6 0x0030
30#define NILE4_DCS7 0x0038
31#define NILE4_DCS8 0x0040
32#define NILE4_PCIW0 0x0060
33#define NILE4_PCIW1 0x0068
34#define NILE4_INTCS 0x0070
35
36#define NILE4_BOOTCS 0x0078
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42
43#define NILE4_CPUSTAT 0x0080
44#define NILE4_INTCTRL 0x0088
45#define NILE4_INTSTAT0 0x0090
46#define NILE4_INTSTAT1 0x0098
47
48#define NILE4_INTCLR 0x00A0
49#define NILE4_INTPPES 0x00A8
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55
56#define NILE4_MEMCTRL 0x00C0
57#define NILE4_ACSTIME 0x00C8
58#define NILE4_CHKERR 0x00D0
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64
65#define NILE4_PCICTRL 0x00E0
66#define NILE4_PCIARB 0x00E8
67#define NILE4_PCIINIT0 0x00F0
68#define NILE4_PCIINIT1 0x00F8
69#define NILE4_PCIERR 0x00B8
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75
76#define NILE4_LCNFG 0x0100
77#define NILE4_LCST2 0x0110
78#define NILE4_LCST3 0x0118
79#define NILE4_LCST4 0x0120
80#define NILE4_LCST5 0x0128
81#define NILE4_LCST6 0x0130
82#define NILE4_LCST7 0x0138
83#define NILE4_LCST8 0x0140
84#define NILE4_DCSFN 0x0150
85
86#define NILE4_DCSIO 0x0158
87#define NILE4_BCST 0x0178
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93
94#define NILE4_DMACTRL0 0x0180
95#define NILE4_DMASRCA0 0x0188
96#define NILE4_DMADESA0 0x0190
97#define NILE4_DMACTRL1 0x0198
98#define NILE4_DMASRCA1 0x01A0
99#define NILE4_DMADESA1 0x01A8
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105
106#define NILE4_T0CTRL 0x01C0
107#define NILE4_T0CNTR 0x01C8
108#define NILE4_T1CTRL 0x01D0
109#define NILE4_T1CNTR 0x01D8
110#define NILE4_T2CTRL 0x01E0
111#define NILE4_T2CNTR 0x01E8
112#define NILE4_T3CTRL 0x01F0
113#define NILE4_T3CNTR 0x01F8
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119
120#define NILE4_PCI_BASE 0x0200
121
122#define NILE4_VID 0x0200
123#define NILE4_DID 0x0202
124#define NILE4_PCICMD 0x0204
125#define NILE4_PCISTS 0x0206
126#define NILE4_REVID 0x0208
127#define NILE4_CLASS 0x0209
128#define NILE4_CLSIZ 0x020C
129#define NILE4_MLTIM 0x020D
130#define NILE4_HTYPE 0x020E
131#define NILE4_BIST 0x020F
132#define NILE4_BARC 0x0210
133#define NILE4_BAR0 0x0218
134#define NILE4_BAR1 0x0220
135#define NILE4_CIS 0x0228
136
137#define NILE4_SSVID 0x022C
138#define NILE4_SSID 0x022E
139#define NILE4_ROM 0x0230
140
141#define NILE4_INTLIN 0x023C
142#define NILE4_INTPIN 0x023D
143#define NILE4_MINGNT 0x023E
144#define NILE4_MAXLAT 0x023F
145#define NILE4_BAR2 0x0240
146#define NILE4_BAR3 0x0248
147#define NILE4_BAR4 0x0250
148#define NILE4_BAR5 0x0258
149#define NILE4_BAR6 0x0260
150#define NILE4_BAR7 0x0268
151#define NILE4_BAR8 0x0270
152#define NILE4_BARB 0x0278
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158
159#define NILE4_UART_BASE 0x0300
160
161#define NILE4_UARTRBR 0x0300
162#define NILE4_UARTTHR 0x0300
163#define NILE4_UARTIER 0x0308
164#define NILE4_UARTDLL 0x0300
165#define NILE4_UARTDLM 0x0308
166#define NILE4_UARTIIR 0x0310
167#define NILE4_UARTFCR 0x0310
168#define NILE4_UARTLCR 0x0318
169#define NILE4_UARTMCR 0x0320
170#define NILE4_UARTLSR 0x0328
171#define NILE4_UARTMSR 0x0330
172#define NILE4_UARTSCR 0x0338
173
174#define NILE4_UART_BASE_BAUD 520833
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180
181#define NILE4_INT_CPCE 0
182#define NILE4_INT_CNTD 1
183#define NILE4_INT_MCE 2
184#define NILE4_INT_DMA 3
185#define NILE4_INT_UART 4
186#define NILE4_INT_WDOG 5
187#define NILE4_INT_GPT 6
188#define NILE4_INT_LBRTD 7
189#define NILE4_INT_INTA 8
190#define NILE4_INT_INTB 9
191#define NILE4_INT_INTC 10
192#define NILE4_INT_INTD 11
193#define NILE4_INT_INTE 12
194#define NILE4_INT_RESV 13
195#define NILE4_INT_PCIS 14
196#define NILE4_INT_PCIE 15
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202
203static inline void nile4_sync(void)
204{
205 volatile u32 *p = (volatile u32 *)0xbfc00000;
206 (void)(*p);
207}
208
209static inline void nile4_out32(u32 offset, u32 val)
210{
211 *(volatile u32 *)(NILE4_BASE+offset) = val;
212 nile4_sync();
213}
214
215static inline u32 nile4_in32(u32 offset)
216{
217 u32 val = *(volatile u32 *)(NILE4_BASE+offset);
218 nile4_sync();
219 return val;
220}
221
222static inline void nile4_out16(u32 offset, u16 val)
223{
224 *(volatile u16 *)(NILE4_BASE+offset) = val;
225 nile4_sync();
226}
227
228static inline u16 nile4_in16(u32 offset)
229{
230 u16 val = *(volatile u16 *)(NILE4_BASE+offset);
231 nile4_sync();
232 return val;
233}
234
235static inline void nile4_out8(u32 offset, u8 val)
236{
237 *(volatile u8 *)(NILE4_BASE+offset) = val;
238 nile4_sync();
239}
240
241static inline u8 nile4_in8(u32 offset)
242{
243 u8 val = *(volatile u8 *)(NILE4_BASE+offset);
244 nile4_sync();
245 return val;
246}
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253extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
254 int on_memory_bus, int visible);
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261#define NILE4_PCICMD_IACK 0
262#define NILE4_PCICMD_IO 1
263#define NILE4_PCICMD_MEM 3
264#define NILE4_PCICMD_CFG 5
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272
273#define NILE4_PCI_IO_BASE 0xa6000000
274#define NILE4_PCI_MEM_BASE 0xa8000000
275#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
276#define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE
277
278
279extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
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285
286#define NUM_I8259_INTERRUPTS 16
287#define NUM_NILE4_INTERRUPTS 16
288
289#define IRQ_I8259_CASCADE NILE4_INT_INTE
290#define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS)
291#define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS)
292#define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS)
293
294extern void nile4_map_irq(int nile4_irq, int cpu_irq);
295extern void nile4_map_irq_all(int cpu_irq);
296extern void nile4_enable_irq(unsigned int nile4_irq);
297extern void nile4_disable_irq(unsigned int nile4_irq);
298extern void nile4_disable_irq_all(void);
299extern u16 nile4_get_irq_stat(int cpu_irq);
300extern void nile4_enable_irq_output(int cpu_irq);
301extern void nile4_disable_irq_output(int cpu_irq);
302extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
303extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
304extern void nile4_clear_irq(int nile4_irq);
305extern void nile4_clear_irq_mask(u32 mask);
306extern u8 nile4_i8259_iack(void);
307extern void nile4_dump_irq_status(void);
308
309#endif
310