LXR linux/arch/powerpc/include/asm/pgtable-be-types.h

   1#ifndef _ASM_POWERPC_PGTABLE_BE_TYPES_H
   2#define _ASM_POWERPC_PGTABLE_BE_TYPES_H
   3
   4#include <asm/cmpxchg.h>
   5
   6/* PTE level */
   7typedef struct { __be64 pte; } pte_t;
   8#define __pte(x)        ((pte_t) { cpu_to_be64(x) })
   9#define __pte_raw(x)    ((pte_t) { (x) })
  10static inline unsigned long pte_val(pte_t x)
  11{
  12        return be64_to_cpu(x.pte);
  13}
  14
  15static inline __be64 pte_raw(pte_t x)
  16{
  17        return x.pte;
  18}
  19
  20/* PMD level */
  21#ifdef CONFIG_PPC64
  22typedef struct { __be64 pmd; } pmd_t;
  23#define __pmd(x)        ((pmd_t) { cpu_to_be64(x) })
  24#define __pmd_raw(x)    ((pmd_t) { (x) })
  25static inline unsigned long pmd_val(pmd_t x)
  26{
  27        return be64_to_cpu(x.pmd);
  28}
  29
  30static inline __be64 pmd_raw(pmd_t x)
  31{
  32        return x.pmd;
  33}
  34
  35/*
  36 * 64 bit hash always use 4 level table. Everybody else use 4 level
  37 * only for 4K page size.
  38 */
  39#if defined(CONFIG_PPC_BOOK3S_64) || !defined(CONFIG_PPC_64K_PAGES)
  40typedef struct { __be64 pud; } pud_t;
  41#define __pud(x)        ((pud_t) { cpu_to_be64(x) })
  42#define __pud_raw(x)    ((pud_t) { (x) })
  43static inline unsigned long pud_val(pud_t x)
  44{
  45        return be64_to_cpu(x.pud);
  46}
  47
  48static inline __be64 pud_raw(pud_t x)
  49{
  50        return x.pud;
  51}
  52
  53#endif /* CONFIG_PPC_BOOK3S_64 || !CONFIG_PPC_64K_PAGES */
  54#endif /* CONFIG_PPC64 */
  55
  56/* PGD level */
  57typedef struct { __be64 pgd; } pgd_t;
  58#define __pgd(x)        ((pgd_t) { cpu_to_be64(x) })
  59#define __pgd_raw(x)    ((pgd_t) { (x) })
  60static inline unsigned long pgd_val(pgd_t x)
  61{
  62        return be64_to_cpu(x.pgd);
  63}
  64
  65static inline __be64 pgd_raw(pgd_t x)
  66{
  67        return x.pgd;
  68}
  69
  70/* Page protection bits */
  71typedef struct { unsigned long pgprot; } pgprot_t;
  72#define pgprot_val(x)   ((x).pgprot)
  73#define __pgprot(x)     ((pgprot_t) { (x) })
  74
  75/*
  76 * With hash config 64k pages additionally define a bigger "real PTE" type that
  77 * gathers the "second half" part of the PTE for pseudo 64k pages
  78 */
  79#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)
  80typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
  81#else
  82typedef struct { pte_t pte; } real_pte_t;
  83#endif
  84
  85static inline bool pte_xchg(pte_t *ptep, pte_t old, pte_t new)
  86{
  87        unsigned long *p = (unsigned long *)ptep;
  88        __be64 prev;
  89
  90        prev = (__force __be64)__cmpxchg_u64(p, (__force unsigned long)pte_raw(old),
  91                                             (__force unsigned long)pte_raw(new));
  92
  93        return pte_raw(old) == prev;
  94}
  95
  96static inline bool pmd_xchg(pmd_t *pmdp, pmd_t old, pmd_t new)
  97{
  98        unsigned long *p = (unsigned long *)pmdp;
  99        __be64 prev;
 100
 101        prev = (__force __be64)__cmpxchg_u64(p, (__force unsigned long)pmd_raw(old),
 102                                             (__force unsigned long)pmd_raw(new));
 103
 104        return pmd_raw(old) == prev;
 105}
 106
 107typedef struct { __be64 pdbe; } hugepd_t;
 108#define __hugepd(x) ((hugepd_t) { cpu_to_be64(x) })
 109
 110static inline unsigned long hpd_val(hugepd_t x)
 111{
 112        return be64_to_cpu(x.pdbe);
 113}
 114
 115#endif /* _ASM_POWERPC_PGTABLE_BE_TYPES_H */
 116