linux/arch/powerpc/perf/power7-pmu.c
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   1/*
   2 * Performance counter support for POWER7 processors.
   3 *
   4 * Copyright 2009 Paul Mackerras, IBM Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version
   9 * 2 of the License, or (at your option) any later version.
  10 */
  11#include <linux/kernel.h>
  12#include <linux/perf_event.h>
  13#include <linux/string.h>
  14#include <asm/reg.h>
  15#include <asm/cputable.h>
  16
  17/*
  18 * Bits in event code for POWER7
  19 */
  20#define PM_PMC_SH       16      /* PMC number (1-based) for direct events */
  21#define PM_PMC_MSK      0xf
  22#define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
  23#define PM_UNIT_SH      12      /* TTMMUX number and setting - unit select */
  24#define PM_UNIT_MSK     0xf
  25#define PM_COMBINE_SH   11      /* Combined event bit */
  26#define PM_COMBINE_MSK  1
  27#define PM_COMBINE_MSKS 0x800
  28#define PM_L2SEL_SH     8       /* L2 event select */
  29#define PM_L2SEL_MSK    7
  30#define PM_PMCSEL_MSK   0xff
  31
  32/*
  33 * Bits in MMCR1 for POWER7
  34 */
  35#define MMCR1_TTM0SEL_SH        60
  36#define MMCR1_TTM1SEL_SH        56
  37#define MMCR1_TTM2SEL_SH        52
  38#define MMCR1_TTM3SEL_SH        48
  39#define MMCR1_TTMSEL_MSK        0xf
  40#define MMCR1_L2SEL_SH          45
  41#define MMCR1_L2SEL_MSK         7
  42#define MMCR1_PMC1_COMBINE_SH   35
  43#define MMCR1_PMC2_COMBINE_SH   34
  44#define MMCR1_PMC3_COMBINE_SH   33
  45#define MMCR1_PMC4_COMBINE_SH   32
  46#define MMCR1_PMC1SEL_SH        24
  47#define MMCR1_PMC2SEL_SH        16
  48#define MMCR1_PMC3SEL_SH        8
  49#define MMCR1_PMC4SEL_SH        0
  50#define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
  51#define MMCR1_PMCSEL_MSK        0xff
  52
  53/*
  54 * Power7 event codes.
  55 */
  56#define EVENT(_name, _code) \
  57        _name = _code,
  58
  59enum {
  60#include "power7-events-list.h"
  61};
  62#undef EVENT
  63
  64/*
  65 * Layout of constraint bits:
  66 * 6666555555555544444444443333333333222222222211111111110000000000
  67 * 3210987654321098765432109876543210987654321098765432109876543210
  68 *                                              < ><  ><><><><><><>
  69 *                                              L2  NC P6P5P4P3P2P1
  70 *
  71 * L2 - 16-18 - Required L2SEL value (select field)
  72 *
  73 * NC - number of counters
  74 *     15: NC error 0x8000
  75 *     12-14: number of events needing PMC1-4 0x7000
  76 *
  77 * P6
  78 *     11: P6 error 0x800
  79 *     10-11: Count of events needing PMC6
  80 *
  81 * P1..P5
  82 *     0-9: Count of events needing PMC1..PMC5
  83 */
  84
  85static int power7_get_constraint(u64 event, unsigned long *maskp,
  86                                 unsigned long *valp)
  87{
  88        int pmc, sh, unit;
  89        unsigned long mask = 0, value = 0;
  90
  91        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
  92        if (pmc) {
  93                if (pmc > 6)
  94                        return -1;
  95                sh = (pmc - 1) * 2;
  96                mask |= 2 << sh;
  97                value |= 1 << sh;
  98                if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
  99                        return -1;
 100        }
 101        if (pmc < 5) {
 102                /* need a counter from PMC1-4 set */
 103                mask  |= 0x8000;
 104                value |= 0x1000;
 105        }
 106
 107        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 108        if (unit == 6) {
 109                /* L2SEL must be identical across events */
 110                int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK;
 111                mask  |= 0x7 << 16;
 112                value |= l2sel << 16;
 113        }
 114
 115        *maskp = mask;
 116        *valp = value;
 117        return 0;
 118}
 119
 120#define MAX_ALT 2       /* at most 2 alternatives for any event */
 121
 122static const unsigned int event_alternatives[][MAX_ALT] = {
 123        { 0x200f2, 0x300f2 },           /* PM_INST_DISP */
 124        { 0x200f4, 0x600f4 },           /* PM_RUN_CYC */
 125        { 0x400fa, 0x500fa },           /* PM_RUN_INST_CMPL */
 126};
 127
 128/*
 129 * Scan the alternatives table for a match and return the
 130 * index into the alternatives table if found, else -1.
 131 */
 132static int find_alternative(u64 event)
 133{
 134        int i, j;
 135
 136        for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
 137                if (event < event_alternatives[i][0])
 138                        break;
 139                for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
 140                        if (event == event_alternatives[i][j])
 141                                return i;
 142        }
 143        return -1;
 144}
 145
 146static s64 find_alternative_decode(u64 event)
 147{
 148        int pmc, psel;
 149
 150        /* this only handles the 4x decode events */
 151        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 152        psel = event & PM_PMCSEL_MSK;
 153        if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
 154                return event - (1 << PM_PMC_SH) + 8;
 155        if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
 156                return event + (1 << PM_PMC_SH) - 8;
 157        return -1;
 158}
 159
 160static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 161{
 162        int i, j, nalt = 1;
 163        s64 ae;
 164
 165        alt[0] = event;
 166        nalt = 1;
 167        i = find_alternative(event);
 168        if (i >= 0) {
 169                for (j = 0; j < MAX_ALT; ++j) {
 170                        ae = event_alternatives[i][j];
 171                        if (ae && ae != event)
 172                                alt[nalt++] = ae;
 173                }
 174        } else {
 175                ae = find_alternative_decode(event);
 176                if (ae > 0)
 177                        alt[nalt++] = ae;
 178        }
 179
 180        if (flags & PPMU_ONLY_COUNT_RUN) {
 181                /*
 182                 * We're only counting in RUN state,
 183                 * so PM_CYC is equivalent to PM_RUN_CYC
 184                 * and PM_INST_CMPL === PM_RUN_INST_CMPL.
 185                 * This doesn't include alternatives that don't provide
 186                 * any extra flexibility in assigning PMCs.
 187                 */
 188                j = nalt;
 189                for (i = 0; i < nalt; ++i) {
 190                        switch (alt[i]) {
 191                        case 0x1e:      /* PM_CYC */
 192                                alt[j++] = 0x600f4;     /* PM_RUN_CYC */
 193                                break;
 194                        case 0x600f4:   /* PM_RUN_CYC */
 195                                alt[j++] = 0x1e;
 196                                break;
 197                        case 0x2:       /* PM_PPC_CMPL */
 198                                alt[j++] = 0x500fa;     /* PM_RUN_INST_CMPL */
 199                                break;
 200                        case 0x500fa:   /* PM_RUN_INST_CMPL */
 201                                alt[j++] = 0x2; /* PM_PPC_CMPL */
 202                                break;
 203                        }
 204                }
 205                nalt = j;
 206        }
 207
 208        return nalt;
 209}
 210
 211/*
 212 * Returns 1 if event counts things relating to marked instructions
 213 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 214 */
 215static int power7_marked_instr_event(u64 event)
 216{
 217        int pmc, psel;
 218        int unit;
 219
 220        pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 221        unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 222        psel = event & PM_PMCSEL_MSK & ~1;      /* trim off edge/level bit */
 223        if (pmc >= 5)
 224                return 0;
 225
 226        switch (psel >> 4) {
 227        case 2:
 228                return pmc == 2 || pmc == 4;
 229        case 3:
 230                if (psel == 0x3c)
 231                        return pmc == 1;
 232                if (psel == 0x3e)
 233                        return pmc != 2;
 234                return 1;
 235        case 4:
 236        case 5:
 237                return unit == 0xd;
 238        case 6:
 239                if (psel == 0x64)
 240                        return pmc >= 3;
 241        case 8:
 242                return unit == 0xd;
 243        }
 244        return 0;
 245}
 246
 247static int power7_compute_mmcr(u64 event[], int n_ev,
 248                               unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
 249{
 250        unsigned long mmcr1 = 0;
 251        unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
 252        unsigned int pmc, unit, combine, l2sel, psel;
 253        unsigned int pmc_inuse = 0;
 254        int i;
 255
 256        /* First pass to count resource use */
 257        for (i = 0; i < n_ev; ++i) {
 258                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 259                if (pmc) {
 260                        if (pmc > 6)
 261                                return -1;
 262                        if (pmc_inuse & (1 << (pmc - 1)))
 263                                return -1;
 264                        pmc_inuse |= 1 << (pmc - 1);
 265                }
 266        }
 267
 268        /* Second pass: assign PMCs, set all MMCR1 fields */
 269        for (i = 0; i < n_ev; ++i) {
 270                pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 271                unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 272                combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
 273                l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
 274                psel = event[i] & PM_PMCSEL_MSK;
 275                if (!pmc) {
 276                        /* Bus event or any-PMC direct event */
 277                        for (pmc = 0; pmc < 4; ++pmc) {
 278                                if (!(pmc_inuse & (1 << pmc)))
 279                                        break;
 280                        }
 281                        if (pmc >= 4)
 282                                return -1;
 283                        pmc_inuse |= 1 << pmc;
 284                } else {
 285                        /* Direct or decoded event */
 286                        --pmc;
 287                }
 288                if (pmc <= 3) {
 289                        mmcr1 |= (unsigned long) unit
 290                                << (MMCR1_TTM0SEL_SH - 4 * pmc);
 291                        mmcr1 |= (unsigned long) combine
 292                                << (MMCR1_PMC1_COMBINE_SH - pmc);
 293                        mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
 294                        if (unit == 6)  /* L2 events */
 295                                mmcr1 |= (unsigned long) l2sel
 296                                        << MMCR1_L2SEL_SH;
 297                }
 298                if (power7_marked_instr_event(event[i]))
 299                        mmcra |= MMCRA_SAMPLE_ENABLE;
 300                hwc[i] = pmc;
 301        }
 302
 303        /* Return MMCRx values */
 304        mmcr[0] = 0;
 305        if (pmc_inuse & 1)
 306                mmcr[0] = MMCR0_PMC1CE;
 307        if (pmc_inuse & 0x3e)
 308                mmcr[0] |= MMCR0_PMCjCE;
 309        mmcr[1] = mmcr1;
 310        mmcr[2] = mmcra;
 311        return 0;
 312}
 313
 314static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
 315{
 316        if (pmc <= 3)
 317                mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
 318}
 319
 320static int power7_generic_events[] = {
 321        [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 322        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_GCT_NOSLOT_CYC,
 323        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
 324        [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 325        [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 326        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
 327        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_FIN,
 328        [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED,
 329};
 330
 331#define C(x)    PERF_COUNT_HW_CACHE_##x
 332
 333/*
 334 * Table of generalized cache-related events.
 335 * 0 means not supported, -1 means nonsensical, other values
 336 * are event codes.
 337 */
 338static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 339        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 340                [C(OP_READ)] = {        0xc880,         0x400f0 },
 341                [C(OP_WRITE)] = {       0,              0x300f0 },
 342                [C(OP_PREFETCH)] = {    0xd8b8,         0       },
 343        },
 344        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 345                [C(OP_READ)] = {        0,              0x200fc },
 346                [C(OP_WRITE)] = {       -1,             -1      },
 347                [C(OP_PREFETCH)] = {    0x408a,         0       },
 348        },
 349        [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
 350                [C(OP_READ)] = {        0x16080,        0x26080 },
 351                [C(OP_WRITE)] = {       0x16082,        0x26082 },
 352                [C(OP_PREFETCH)] = {    0,              0       },
 353        },
 354        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 355                [C(OP_READ)] = {        0,              0x300fc },
 356                [C(OP_WRITE)] = {       -1,             -1      },
 357                [C(OP_PREFETCH)] = {    -1,             -1      },
 358        },
 359        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 360                [C(OP_READ)] = {        0,              0x400fc },
 361                [C(OP_WRITE)] = {       -1,             -1      },
 362                [C(OP_PREFETCH)] = {    -1,             -1      },
 363        },
 364        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 365                [C(OP_READ)] = {        0x10068,        0x400f6 },
 366                [C(OP_WRITE)] = {       -1,             -1      },
 367                [C(OP_PREFETCH)] = {    -1,             -1      },
 368        },
 369        [C(NODE)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 370                [C(OP_READ)] = {        -1,             -1      },
 371                [C(OP_WRITE)] = {       -1,             -1      },
 372                [C(OP_PREFETCH)] = {    -1,             -1      },
 373        },
 374};
 375
 376
 377GENERIC_EVENT_ATTR(cpu-cycles,                  PM_CYC);
 378GENERIC_EVENT_ATTR(stalled-cycles-frontend,     PM_GCT_NOSLOT_CYC);
 379GENERIC_EVENT_ATTR(stalled-cycles-backend,      PM_CMPLU_STALL);
 380GENERIC_EVENT_ATTR(instructions,                PM_INST_CMPL);
 381GENERIC_EVENT_ATTR(cache-references,            PM_LD_REF_L1);
 382GENERIC_EVENT_ATTR(cache-misses,                PM_LD_MISS_L1);
 383GENERIC_EVENT_ATTR(branch-instructions,         PM_BRU_FIN);
 384GENERIC_EVENT_ATTR(branch-misses,               PM_BR_MPRED);
 385
 386#define EVENT(_name, _code)     POWER_EVENT_ATTR(_name, _name);
 387#include "power7-events-list.h"
 388#undef EVENT
 389
 390#define EVENT(_name, _code)     POWER_EVENT_PTR(_name),
 391
 392static struct attribute *power7_events_attr[] = {
 393        GENERIC_EVENT_PTR(PM_CYC),
 394        GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
 395        GENERIC_EVENT_PTR(PM_CMPLU_STALL),
 396        GENERIC_EVENT_PTR(PM_INST_CMPL),
 397        GENERIC_EVENT_PTR(PM_LD_REF_L1),
 398        GENERIC_EVENT_PTR(PM_LD_MISS_L1),
 399        GENERIC_EVENT_PTR(PM_BRU_FIN),
 400        GENERIC_EVENT_PTR(PM_BR_MPRED),
 401
 402        #include "power7-events-list.h"
 403        #undef EVENT
 404        NULL
 405};
 406
 407static struct attribute_group power7_pmu_events_group = {
 408        .name = "events",
 409        .attrs = power7_events_attr,
 410};
 411
 412PMU_FORMAT_ATTR(event, "config:0-19");
 413
 414static struct attribute *power7_pmu_format_attr[] = {
 415        &format_attr_event.attr,
 416        NULL,
 417};
 418
 419static struct attribute_group power7_pmu_format_group = {
 420        .name = "format",
 421        .attrs = power7_pmu_format_attr,
 422};
 423
 424static const struct attribute_group *power7_pmu_attr_groups[] = {
 425        &power7_pmu_format_group,
 426        &power7_pmu_events_group,
 427        NULL,
 428};
 429
 430static struct power_pmu power7_pmu = {
 431        .name                   = "POWER7",
 432        .n_counter              = 6,
 433        .max_alternatives       = MAX_ALT + 1,
 434        .add_fields             = 0x1555ul,
 435        .test_adder             = 0x3000ul,
 436        .compute_mmcr           = power7_compute_mmcr,
 437        .get_constraint         = power7_get_constraint,
 438        .get_alternatives       = power7_get_alternatives,
 439        .disable_pmc            = power7_disable_pmc,
 440        .flags                  = PPMU_ALT_SIPR,
 441        .attr_groups            = power7_pmu_attr_groups,
 442        .n_generic              = ARRAY_SIZE(power7_generic_events),
 443        .generic_events         = power7_generic_events,
 444        .cache_events           = &power7_cache_events,
 445};
 446
 447static int __init init_power7_pmu(void)
 448{
 449        if (!cur_cpu_spec->oprofile_cpu_type ||
 450            strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
 451                return -ENODEV;
 452
 453        if (pvr_version_is(PVR_POWER7p))
 454                power7_pmu.flags |= PPMU_SIAR_VALID;
 455
 456        return register_power_pmu(&power7_pmu);
 457}
 458
 459early_initcall(init_power7_pmu);
 460