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15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt2701-clk.h>
22
23static const struct mtk_gate_regs disp0_cg_regs = {
24 .set_ofs = 0x0104,
25 .clr_ofs = 0x0108,
26 .sta_ofs = 0x0100,
27};
28
29static const struct mtk_gate_regs disp1_cg_regs = {
30 .set_ofs = 0x0114,
31 .clr_ofs = 0x0118,
32 .sta_ofs = 0x0110,
33};
34
35#define GATE_DISP0(_id, _name, _parent, _shift) { \
36 .id = _id, \
37 .name = _name, \
38 .parent_name = _parent, \
39 .regs = &disp0_cg_regs, \
40 .shift = _shift, \
41 .ops = &mtk_clk_gate_ops_setclr, \
42 }
43
44#define GATE_DISP1(_id, _name, _parent, _shift) { \
45 .id = _id, \
46 .name = _name, \
47 .parent_name = _parent, \
48 .regs = &disp1_cg_regs, \
49 .shift = _shift, \
50 .ops = &mtk_clk_gate_ops_setclr, \
51 }
52
53static const struct mtk_gate mm_clks[] = {
54 GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
55 GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
56 GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
57 GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3),
58 GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4),
59 GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5),
60 GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6),
61 GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7),
62 GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8),
63 GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
64 GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10),
65 GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
66 GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
67 GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
68 GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14),
69 GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "pwm_sel", 15),
70 GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16),
71 GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17),
72 GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18),
73 GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
74 GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20),
75 GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0),
76 GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsi0_lntc_dsi", 1),
77 GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
78 GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
79 GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
80 GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
81 GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
82 GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
83 GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
84 GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
85 GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
86 GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
87 GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
88};
89
90static const struct of_device_id of_match_clk_mt2701_mm[] = {
91 { .compatible = "mediatek,mt2701-mmsys", },
92 {}
93};
94
95static int clk_mt2701_mm_probe(struct platform_device *pdev)
96{
97 struct clk_onecell_data *clk_data;
98 int r;
99 struct device_node *node = pdev->dev.of_node;
100
101 clk_data = mtk_alloc_clk_data(CLK_MM_NR);
102
103 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
104 clk_data);
105
106 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
107 if (r)
108 dev_err(&pdev->dev,
109 "could not register clock provider: %s: %d\n",
110 pdev->name, r);
111
112 return r;
113}
114
115static struct platform_driver clk_mt2701_mm_drv = {
116 .probe = clk_mt2701_mm_probe,
117 .driver = {
118 .name = "clk-mt2701-mm",
119 .of_match_table = of_match_clk_mt2701_mm,
120 },
121};
122
123builtin_platform_driver(clk_mt2701_mm_drv);
124
