LXR linux/drivers/crypto/caam/regs.h

   1/*
   2 * CAAM hardware register-level view
   3 *
   4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
   5 */
   6
   7#ifndef REGS_H
   8#define REGS_H
   9
  10#include <linux/types.h>
  11#include <linux/bitops.h>
  12#include <linux/io.h>
  13
  14/*
  15 * Architecture-specific register access methods
  16 *
  17 * CAAM's bus-addressable registers are 64 bits internally.
  18 * They have been wired to be safely accessible on 32-bit
  19 * architectures, however. Registers were organized such
  20 * that (a) they can be contained in 32 bits, (b) if not, then they
  21 * can be treated as two 32-bit entities, or finally (c) if they
  22 * must be treated as a single 64-bit value, then this can safely
  23 * be done with two 32-bit cycles.
  24 *
  25 * For 32-bit operations on 64-bit values, CAAM follows the same
  26 * 64-bit register access conventions as it's predecessors, in that
  27 * writes are "triggered" by a write to the register at the numerically
  28 * higher address, thus, a full 64-bit write cycle requires a write
  29 * to the lower address, followed by a write to the higher address,
  30 * which will latch/execute the write cycle.
  31 *
  32 * For example, let's assume a SW reset of CAAM through the master
  33 * configuration register.
  34 * - SWRST is in bit 31 of MCFG.
  35 * - MCFG begins at base+0x0000.
  36 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
  37 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
  38 *
  39 * (and on Power, the convention is 0-31, 32-63, I know...)
  40 *
  41 * Assuming a 64-bit write to this MCFG to perform a software reset
  42 * would then require a write of 0 to base+0x0000, followed by a
  43 * write of 0x80000000 to base+0x0004, which would "execute" the
  44 * reset.
  45 *
  46 * Of course, since MCFG 63-32 is all zero, we could cheat and simply
  47 * write 0x8000000 to base+0x0004, and the reset would work fine.
  48 * However, since CAAM does contain some write-and-read-intended
  49 * 64-bit registers, this code defines 64-bit access methods for
  50 * the sake of internal consistency and simplicity, and so that a
  51 * clean transition to 64-bit is possible when it becomes necessary.
  52 *
  53 * There are limitations to this that the developer must recognize.
  54 * 32-bit architectures cannot enforce an atomic-64 operation,
  55 * Therefore:
  56 *
  57 * - On writes, since the HW is assumed to latch the cycle on the
  58 *   write of the higher-numeric-address word, then ordered
  59 *   writes work OK.
  60 *
  61 * - For reads, where a register contains a relevant value of more
  62 *   that 32 bits, the hardware employs logic to latch the other
  63 *   "half" of the data until read, ensuring an accurate value.
  64 *   This is of particular relevance when dealing with CAAM's
  65 *   performance counters.
  66 *
  67 */
  68
  69extern bool caam_little_end;
  70
  71#define caam_to_cpu(len)                                \
  72static inline u##len caam##len ## _to_cpu(u##len val)   \
  73{                                                       \
  74        if (caam_little_end)                            \
  75                return le##len ## _to_cpu(val);         \
  76        else                                            \
  77                return be##len ## _to_cpu(val);         \
  78}
  79
  80#define cpu_to_caam(len)                                \
  81static inline u##len cpu_to_caam##len(u##len val)       \
  82{                                                       \
  83        if (caam_little_end)                            \
  84                return cpu_to_le##len(val);             \
  85        else                                            \
  86                return cpu_to_be##len(val);             \
  87}
  88
  89caam_to_cpu(16)
  90caam_to_cpu(32)
  91caam_to_cpu(64)
  92cpu_to_caam(16)
  93cpu_to_caam(32)
  94cpu_to_caam(64)
  95
  96static inline void wr_reg32(void __iomem *reg, u32 data)
  97{
  98        if (caam_little_end)
  99                iowrite32(data, reg);
 100        else
 101                iowrite32be(data, reg);
 102}
 103
 104static inline u32 rd_reg32(void __iomem *reg)
 105{
 106        if (caam_little_end)
 107                return ioread32(reg);
 108
 109        return ioread32be(reg);
 110}
 111
 112static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
 113{
 114        if (caam_little_end)
 115                iowrite32((ioread32(reg) & ~clear) | set, reg);
 116        else
 117                iowrite32be((ioread32be(reg) & ~clear) | set, reg);
 118}
 119
 120/*
 121 * The only users of these wr/rd_reg64 functions is the Job Ring (JR).
 122 * The DMA address registers in the JR are handled differently depending on
 123 * platform:
 124 *
 125 * 1. All BE CAAM platforms and i.MX platforms (LE CAAM):
 126 *
 127 *    base + 0x0000 : most-significant 32 bits
 128 *    base + 0x0004 : least-significant 32 bits
 129 *
 130 * The 32-bit version of this core therefore has to write to base + 0x0004
 131 * to set the 32-bit wide DMA address.
 132 *
 133 * 2. All other LE CAAM platforms (LS1021A etc.)
 134 *    base + 0x0000 : least-significant 32 bits
 135 *    base + 0x0004 : most-significant 32 bits
 136 */
 137#ifdef CONFIG_64BIT
 138static inline void wr_reg64(void __iomem *reg, u64 data)
 139{
 140        if (caam_little_end)
 141                iowrite64(data, reg);
 142        else
 143                iowrite64be(data, reg);
 144}
 145
 146static inline u64 rd_reg64(void __iomem *reg)
 147{
 148        if (caam_little_end)
 149                return ioread64(reg);
 150        else
 151                return ioread64be(reg);
 152}
 153
 154#else /* CONFIG_64BIT */
 155static inline void wr_reg64(void __iomem *reg, u64 data)
 156{
 157#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
 158        if (caam_little_end) {
 159                wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
 160                wr_reg32((u32 __iomem *)(reg), data);
 161        } else
 162#endif
 163        {
 164                wr_reg32((u32 __iomem *)(reg), data >> 32);
 165                wr_reg32((u32 __iomem *)(reg) + 1, data);
 166        }
 167}
 168
 169static inline u64 rd_reg64(void __iomem *reg)
 170{
 171#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
 172        if (caam_little_end)
 173                return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
 174                        (u64)rd_reg32((u32 __iomem *)(reg)));
 175        else
 176#endif
 177                return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
 178                        (u64)rd_reg32((u32 __iomem *)(reg) + 1));
 179}
 180#endif /* CONFIG_64BIT  */
 181
 182#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 183#ifdef CONFIG_SOC_IMX7D
 184#define cpu_to_caam_dma(value) \
 185                (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
 186                  (u64)cpu_to_caam32(upper_32_bits(value)))
 187#define caam_dma_to_cpu(value) \
 188                (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | \
 189                  (u64)caam32_to_cpu(upper_32_bits(value)))
 190#else
 191#define cpu_to_caam_dma(value) cpu_to_caam64(value)
 192#define caam_dma_to_cpu(value) caam64_to_cpu(value)
 193#endif /* CONFIG_SOC_IMX7D */
 194#else
 195#define cpu_to_caam_dma(value) cpu_to_caam32(value)
 196#define caam_dma_to_cpu(value) caam32_to_cpu(value)
 197#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT  */
 198
 199#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
 200#define cpu_to_caam_dma64(value) \
 201                (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
 202                 (u64)cpu_to_caam32(upper_32_bits(value)))
 203#else
 204#define cpu_to_caam_dma64(value) cpu_to_caam64(value)
 205#endif
 206
 207/*
 208 * jr_outentry
 209 * Represents each entry in a JobR output ring
 210 */
 211struct jr_outentry {
 212        dma_addr_t desc;/* Pointer to completed descriptor */
 213        u32 jrstatus;   /* Status for completed descriptor */
 214} __packed;
 215
 216/*
 217 * caam_perfmon - Performance Monitor/Secure Memory Status/
 218 *                CAAM Global Status/Component Version IDs
 219 *
 220 * Spans f00-fff wherever instantiated
 221 */
 222
 223/* Number of DECOs */
 224#define CHA_NUM_MS_DECONUM_SHIFT        24
 225#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
 226
 227/*
 228 * CHA version IDs / instantiation bitfields
 229 * Defined for use with the cha_id fields in perfmon, but the same shift/mask
 230 * selectors can be used to pull out the number of instantiated blocks within
 231 * cha_num fields in perfmon because the locations are the same.
 232 */
 233#define CHA_ID_LS_AES_SHIFT     0
 234#define CHA_ID_LS_AES_MASK      (0xfull << CHA_ID_LS_AES_SHIFT)
 235#define CHA_ID_LS_AES_LP        (0x3ull << CHA_ID_LS_AES_SHIFT)
 236#define CHA_ID_LS_AES_HP        (0x4ull << CHA_ID_LS_AES_SHIFT)
 237
 238#define CHA_ID_LS_DES_SHIFT     4
 239#define CHA_ID_LS_DES_MASK      (0xfull << CHA_ID_LS_DES_SHIFT)
 240
 241#define CHA_ID_LS_ARC4_SHIFT    8
 242#define CHA_ID_LS_ARC4_MASK     (0xfull << CHA_ID_LS_ARC4_SHIFT)
 243
 244#define CHA_ID_LS_MD_SHIFT      12
 245#define CHA_ID_LS_MD_MASK       (0xfull << CHA_ID_LS_MD_SHIFT)
 246#define CHA_ID_LS_MD_LP256      (0x0ull << CHA_ID_LS_MD_SHIFT)
 247#define CHA_ID_LS_MD_LP512      (0x1ull << CHA_ID_LS_MD_SHIFT)
 248#define CHA_ID_LS_MD_HP         (0x2ull << CHA_ID_LS_MD_SHIFT)
 249
 250#define CHA_ID_LS_RNG_SHIFT     16
 251#define CHA_ID_LS_RNG_MASK      (0xfull << CHA_ID_LS_RNG_SHIFT)
 252
 253#define CHA_ID_LS_SNW8_SHIFT    20
 254#define CHA_ID_LS_SNW8_MASK     (0xfull << CHA_ID_LS_SNW8_SHIFT)
 255
 256#define CHA_ID_LS_KAS_SHIFT     24
 257#define CHA_ID_LS_KAS_MASK      (0xfull << CHA_ID_LS_KAS_SHIFT)
 258
 259#define CHA_ID_LS_PK_SHIFT      28
 260#define CHA_ID_LS_PK_MASK       (0xfull << CHA_ID_LS_PK_SHIFT)
 261
 262#define CHA_ID_MS_CRC_SHIFT     0
 263#define CHA_ID_MS_CRC_MASK      (0xfull << CHA_ID_MS_CRC_SHIFT)
 264
 265#define CHA_ID_MS_SNW9_SHIFT    4
 266#define CHA_ID_MS_SNW9_MASK     (0xfull << CHA_ID_MS_SNW9_SHIFT)
 267
 268#define CHA_ID_MS_DECO_SHIFT    24
 269#define CHA_ID_MS_DECO_MASK     (0xfull << CHA_ID_MS_DECO_SHIFT)
 270
 271#define CHA_ID_MS_JR_SHIFT      28
 272#define CHA_ID_MS_JR_MASK       (0xfull << CHA_ID_MS_JR_SHIFT)
 273
 274struct sec_vid {
 275        u16 ip_id;
 276        u8 maj_rev;
 277        u8 min_rev;
 278};
 279
 280struct caam_perfmon {
 281        /* Performance Monitor Registers                        f00-f9f */
 282        u64 req_dequeued;       /* PC_REQ_DEQ - Dequeued Requests            */
 283        u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
 284        u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests  */
 285        u64 ob_enc_bytes;       /* PC_OB_ENCRYPT - Outbound Bytes Encrypted  */
 286        u64 ob_prot_bytes;      /* PC_OB_PROTECT - Outbound Bytes Protected  */
 287        u64 ib_dec_bytes;       /* PC_IB_DECRYPT - Inbound Bytes Decrypted   */
 288        u64 ib_valid_bytes;     /* PC_IB_VALIDATED Inbound Bytes Validated   */
 289        u64 rsvd[13];
 290
 291        /* CAAM Hardware Instantiation Parameters               fa0-fbf */
 292        u32 cha_rev_ms;         /* CRNR - CHA Rev No. Most significant half*/
 293        u32 cha_rev_ls;         /* CRNR - CHA Rev No. Least significant half*/
 294#define CTPR_MS_QI_SHIFT        25
 295#define CTPR_MS_QI_MASK         (0x1ull << CTPR_MS_QI_SHIFT)
 296#define CTPR_MS_VIRT_EN_INCL    0x00000001
 297#define CTPR_MS_VIRT_EN_POR     0x00000002
 298#define CTPR_MS_PG_SZ_MASK      0x10
 299#define CTPR_MS_PG_SZ_SHIFT     4
 300        u32 comp_parms_ms;      /* CTPR - Compile Parameters Register   */
 301        u32 comp_parms_ls;      /* CTPR - Compile Parameters Register   */
 302        u64 rsvd1[2];
 303
 304        /* CAAM Global Status                                   fc0-fdf */
 305        u64 faultaddr;  /* FAR  - Fault Address         */
 306        u32 faultliodn; /* FALR - Fault Address LIODN   */
 307        u32 faultdetail;        /* FADR - Fault Addr Detail     */
 308        u32 rsvd2;
 309#define CSTA_PLEND              BIT(10)
 310#define CSTA_ALT_PLEND          BIT(18)
 311        u32 status;             /* CSTA - CAAM Status */
 312        u64 rsvd3;
 313
 314        /* Component Instantiation Parameters                   fe0-fff */
 315        u32 rtic_id;            /* RVID - RTIC Version ID       */
 316        u32 ccb_id;             /* CCBVID - CCB Version ID      */
 317        u32 cha_id_ms;          /* CHAVID - CHA Version ID Most Significant*/
 318        u32 cha_id_ls;          /* CHAVID - CHA Version ID Least Significant*/
 319        u32 cha_num_ms;         /* CHANUM - CHA Number Most Significant */
 320        u32 cha_num_ls;         /* CHANUM - CHA Number Least Significant*/
 321        u32 caam_id_ms;         /* CAAMVID - CAAM Version ID MS */
 322        u32 caam_id_ls;         /* CAAMVID - CAAM Version ID LS */
 323};
 324
 325/* LIODN programming for DMA configuration */
 326#define MSTRID_LOCK_LIODN       0x80000000
 327#define MSTRID_LOCK_MAKETRUSTED 0x00010000      /* only for JR masterid */
 328
 329#define MSTRID_LIODN_MASK       0x0fff
 330struct masterid {
 331        u32 liodn_ms;   /* lock and make-trusted control bits */
 332        u32 liodn_ls;   /* LIODN for non-sequence and seq access */
 333};
 334
 335/* Partition ID for DMA configuration */
 336struct partid {
 337        u32 rsvd1;
 338        u32 pidr;       /* partition ID, DECO */
 339};
 340
 341/* RNGB test mode (replicated twice in some configurations) */
 342/* Padded out to 0x100 */
 343struct rngtst {
 344        u32 mode;               /* RTSTMODEx - Test mode */
 345        u32 rsvd1[3];
 346        u32 reset;              /* RTSTRESETx - Test reset control */
 347        u32 rsvd2[3];
 348        u32 status;             /* RTSTSSTATUSx - Test status */
 349        u32 rsvd3;
 350        u32 errstat;            /* RTSTERRSTATx - Test error status */
 351        u32 rsvd4;
 352        u32 errctl;             /* RTSTERRCTLx - Test error control */
 353        u32 rsvd5;
 354        u32 entropy;            /* RTSTENTROPYx - Test entropy */
 355        u32 rsvd6[15];
 356        u32 verifctl;   /* RTSTVERIFCTLx - Test verification control */
 357        u32 rsvd7;
 358        u32 verifstat;  /* RTSTVERIFSTATx - Test verification status */
 359        u32 rsvd8;
 360        u32 verifdata;  /* RTSTVERIFDx - Test verification data */
 361        u32 rsvd9;
 362        u32 xkey;               /* RTSTXKEYx - Test XKEY */
 363        u32 rsvd10;
 364        u32 oscctctl;   /* RTSTOSCCTCTLx - Test osc. counter control */
 365        u32 rsvd11;
 366        u32 oscct;              /* RTSTOSCCTx - Test oscillator counter */
 367        u32 rsvd12;
 368        u32 oscctstat;  /* RTSTODCCTSTATx - Test osc counter status */
 369        u32 rsvd13[2];
 370        u32 ofifo[4];   /* RTSTOFIFOx - Test output FIFO */
 371        u32 rsvd14[15];
 372};
 373
 374/* RNG4 TRNG test registers */
 375struct rng4tst {
 376#define RTMCTL_PRGM     0x00010000      /* 1 -> program mode, 0 -> run mode */
 377#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC      0 /* use von Neumann data in
 378                                                     both entropy shifter and
 379                                                     statistical checker */
 380#define RTMCTL_SAMP_MODE_RAW_ES_SC              1 /* use raw data in both
 381                                                     entropy shifter and
 382                                                     statistical checker */
 383#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC  2 /* use von Neumann data in
 384                                                     entropy shifter, raw data
 385                                                     in statistical checker */
 386#define RTMCTL_SAMP_MODE_INVALID                3 /* invalid combination */
 387        u32 rtmctl;             /* misc. control register */
 388        u32 rtscmisc;           /* statistical check misc. register */
 389        u32 rtpkrrng;           /* poker range register */
 390        union {
 391                u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
 392                u32 rtpkrsq;    /* PRGM=0: poker square calc. result register */
 393        };
 394#define RTSDCTL_ENT_DLY_SHIFT 16
 395#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
 396#define RTSDCTL_ENT_DLY_MIN 3200
 397#define RTSDCTL_ENT_DLY_MAX 12800
 398        u32 rtsdctl;            /* seed control register */
 399        union {
 400                u32 rtsblim;    /* PRGM=1: sparse bit limit register */
 401                u32 rttotsam;   /* PRGM=0: total samples register */
 402        };
 403        u32 rtfrqmin;           /* frequency count min. limit register */
 404#define RTFRQMAX_DISABLE        (1 << 20)
 405        union {
 406                u32 rtfrqmax;   /* PRGM=1: freq. count max. limit register */
 407                u32 rtfrqcnt;   /* PRGM=0: freq. count register */
 408        };
 409        u32 rsvd1[40];
 410#define RDSTA_SKVT 0x80000000
 411#define RDSTA_SKVN 0x40000000
 412#define RDSTA_IF0 0x00000001
 413#define RDSTA_IF1 0x00000002
 414#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
 415        u32 rdsta;
 416        u32 rsvd2[15];
 417};
 418
 419/*
 420 * caam_ctrl - basic core configuration
 421 * starts base + 0x0000 padded out to 0x1000
 422 */
 423
 424#define KEK_KEY_SIZE            8
 425#define TKEK_KEY_SIZE           8
 426#define TDSK_KEY_SIZE           8
 427
 428#define DECO_RESET      1       /* Use with DECO reset/availability regs */
 429#define DECO_RESET_0    (DECO_RESET << 0)
 430#define DECO_RESET_1    (DECO_RESET << 1)
 431#define DECO_RESET_2    (DECO_RESET << 2)
 432#define DECO_RESET_3    (DECO_RESET << 3)
 433#define DECO_RESET_4    (DECO_RESET << 4)
 434
 435struct caam_ctrl {
 436        /* Basic Configuration Section                          000-01f */
 437        /* Read/Writable                                                */
 438        u32 rsvd1;
 439        u32 mcr;                /* MCFG      Master Config Register  */
 440        u32 rsvd2;
 441        u32 scfgr;              /* SCFGR, Security Config Register */
 442
 443        /* Bus Access Configuration Section                     010-11f */
 444        /* Read/Writable                                                */
 445        struct masterid jr_mid[4];      /* JRxLIODNR - JobR LIODN setup */
 446        u32 rsvd3[11];
 447        u32 jrstart;                    /* JRSTART - Job Ring Start Register */
 448        struct masterid rtic_mid[4];    /* RTICxLIODNR - RTIC LIODN setup */
 449        u32 rsvd4[5];
 450        u32 deco_rsr;                   /* DECORSR - Deco Request Source */
 451        u32 rsvd11;
 452        u32 deco_rq;                    /* DECORR - DECO Request */
 453        struct partid deco_mid[5];      /* DECOxLIODNR - 1 per DECO */
 454        u32 rsvd5[22];
 455
 456        /* DECO Availability/Reset Section                      120-3ff */
 457        u32 deco_avail;         /* DAR - DECO availability */
 458        u32 deco_reset;         /* DRR - DECO reset */
 459        u32 rsvd6[182];
 460
 461        /* Key Encryption/Decryption Configuration              400-5ff */
 462        /* Read/Writable only while in Non-secure mode                  */
 463        u32 kek[KEK_KEY_SIZE];  /* JDKEKR - Key Encryption Key */
 464        u32 tkek[TKEK_KEY_SIZE];        /* TDKEKR - Trusted Desc KEK */
 465        u32 tdsk[TDSK_KEY_SIZE];        /* TDSKR - Trusted Desc Signing Key */
 466        u32 rsvd7[32];
 467        u64 sknonce;                    /* SKNR - Secure Key Nonce */
 468        u32 rsvd8[70];
 469
 470        /* RNG Test/Verification/Debug Access                   600-7ff */
 471        /* (Useful in Test/Debug modes only...)                         */
 472        union {
 473                struct rngtst rtst[2];
 474                struct rng4tst r4tst[2];
 475        };
 476
 477        u32 rsvd9[448];
 478
 479        /* Performance Monitor                                  f00-fff */
 480        struct caam_perfmon perfmon;
 481};
 482
 483/*
 484 * Controller master config register defs
 485 */
 486#define MCFGR_SWRESET           0x80000000 /* software reset */
 487#define MCFGR_WDENABLE          0x40000000 /* DECO watchdog enable */
 488#define MCFGR_WDFAIL            0x20000000 /* DECO watchdog force-fail */
 489#define MCFGR_DMA_RESET         0x10000000
 490#define MCFGR_LONG_PTR          0x00010000 /* Use >32-bit desc addressing */
 491#define SCFGR_RDBENABLE         0x00000400
 492#define SCFGR_VIRT_EN           0x00008000
 493#define DECORR_RQD0ENABLE       0x00000001 /* Enable DECO0 for direct access */
 494#define DECORSR_JR0             0x00000001 /* JR to supply TZ, SDID, ICID */
 495#define DECORSR_VALID           0x80000000
 496#define DECORR_DEN0             0x00010000 /* DECO0 available for access*/
 497
 498/* AXI read cache control */
 499#define MCFGR_ARCACHE_SHIFT     12
 500#define MCFGR_ARCACHE_MASK      (0xf << MCFGR_ARCACHE_SHIFT)
 501#define MCFGR_ARCACHE_BUFF      (0x1 << MCFGR_ARCACHE_SHIFT)
 502#define MCFGR_ARCACHE_CACH      (0x2 << MCFGR_ARCACHE_SHIFT)
 503#define MCFGR_ARCACHE_RALL      (0x4 << MCFGR_ARCACHE_SHIFT)
 504
 505/* AXI write cache control */
 506#define MCFGR_AWCACHE_SHIFT     8
 507#define MCFGR_AWCACHE_MASK      (0xf << MCFGR_AWCACHE_SHIFT)
 508#define MCFGR_AWCACHE_BUFF      (0x1 << MCFGR_AWCACHE_SHIFT)
 509#define MCFGR_AWCACHE_CACH      (0x2 << MCFGR_AWCACHE_SHIFT)
 510#define MCFGR_AWCACHE_WALL      (0x8 << MCFGR_AWCACHE_SHIFT)
 511
 512/* AXI pipeline depth */
 513#define MCFGR_AXIPIPE_SHIFT     4
 514#define MCFGR_AXIPIPE_MASK      (0xf << MCFGR_AXIPIPE_SHIFT)
 515
 516#define MCFGR_AXIPRI            0x00000008 /* Assert AXI priority sideband */
 517#define MCFGR_LARGE_BURST       0x00000004 /* 128/256-byte burst size */
 518#define MCFGR_BURST_64          0x00000001 /* 64-byte burst size */
 519
 520/* JRSTART register offsets */
 521#define JRSTART_JR0_START       0x00000001 /* Start Job ring 0 */
 522#define JRSTART_JR1_START       0x00000002 /* Start Job ring 1 */
 523#define JRSTART_JR2_START       0x00000004 /* Start Job ring 2 */
 524#define JRSTART_JR3_START       0x00000008 /* Start Job ring 3 */
 525
 526/*
 527 * caam_job_ring - direct job ring setup
 528 * 1-4 possible per instantiation, base + 1000/2000/3000/4000
 529 * Padded out to 0x1000
 530 */
 531struct caam_job_ring {
 532        /* Input ring */
 533        u64 inpring_base;       /* IRBAx -  Input desc ring baseaddr */
 534        u32 rsvd1;
 535        u32 inpring_size;       /* IRSx - Input ring size */
 536        u32 rsvd2;
 537        u32 inpring_avail;      /* IRSAx - Input ring room remaining */
 538        u32 rsvd3;
 539        u32 inpring_jobadd;     /* IRJAx - Input ring jobs added */
 540
 541        /* Output Ring */
 542        u64 outring_base;       /* ORBAx - Output status ring base addr */
 543        u32 rsvd4;
 544        u32 outring_size;       /* ORSx - Output ring size */
 545        u32 rsvd5;
 546        u32 outring_rmvd;       /* ORJRx - Output ring jobs removed */
 547        u32 rsvd6;
 548        u32 outring_used;       /* ORSFx - Output ring slots full */
 549
 550        /* Status/Configuration */
 551        u32 rsvd7;
 552        u32 jroutstatus;        /* JRSTAx - JobR output status */
 553        u32 rsvd8;
 554        u32 jrintstatus;        /* JRINTx - JobR interrupt status */
 555        u32 rconfig_hi; /* JRxCFG - Ring configuration */
 556        u32 rconfig_lo;
 557
 558        /* Indices. CAAM maintains as "heads" of each queue */
 559        u32 rsvd9;
 560        u32 inp_rdidx;  /* IRRIx - Input ring read index */
 561        u32 rsvd10;
 562        u32 out_wtidx;  /* ORWIx - Output ring write index */
 563
 564        /* Command/control */
 565        u32 rsvd11;
 566        u32 jrcommand;  /* JRCRx - JobR command */
 567
 568        u32 rsvd12[932];
 569
 570        /* Performance Monitor                                  f00-fff */
 571        struct caam_perfmon perfmon;
 572};
 573
 574#define JR_RINGSIZE_MASK        0x03ff
 575/*
 576 * jrstatus - Job Ring Output Status
 577 * All values in lo word
 578 * Also note, same values written out as status through QI
 579 * in the command/status field of a frame descriptor
 580 */
 581#define JRSTA_SSRC_SHIFT            28
 582#define JRSTA_SSRC_MASK             0xf0000000
 583
 584#define JRSTA_SSRC_NONE             0x00000000
 585#define JRSTA_SSRC_CCB_ERROR        0x20000000
 586#define JRSTA_SSRC_JUMP_HALT_USER   0x30000000
 587#define JRSTA_SSRC_DECO             0x40000000
 588#define JRSTA_SSRC_JRERROR          0x60000000
 589#define JRSTA_SSRC_JUMP_HALT_CC     0x70000000
 590
 591#define JRSTA_DECOERR_JUMP          0x08000000
 592#define JRSTA_DECOERR_INDEX_SHIFT   8
 593#define JRSTA_DECOERR_INDEX_MASK    0xff00
 594#define JRSTA_DECOERR_ERROR_MASK    0x00ff
 595
 596#define JRSTA_DECOERR_NONE          0x00
 597#define JRSTA_DECOERR_LINKLEN       0x01
 598#define JRSTA_DECOERR_LINKPTR       0x02
 599#define JRSTA_DECOERR_JRCTRL        0x03
 600#define JRSTA_DECOERR_DESCCMD       0x04
 601#define JRSTA_DECOERR_ORDER         0x05
 602#define JRSTA_DECOERR_KEYCMD        0x06
 603#define JRSTA_DECOERR_LOADCMD       0x07
 604#define JRSTA_DECOERR_STORECMD      0x08
 605#define JRSTA_DECOERR_OPCMD         0x09
 606#define JRSTA_DECOERR_FIFOLDCMD     0x0a
 607#define JRSTA_DECOERR_FIFOSTCMD     0x0b
 608#define JRSTA_DECOERR_MOVECMD       0x0c
 609#define JRSTA_DECOERR_JUMPCMD       0x0d
 610#define JRSTA_DECOERR_MATHCMD       0x0e
 611#define JRSTA_DECOERR_SHASHCMD      0x0f
 612#define JRSTA_DECOERR_SEQCMD        0x10
 613#define JRSTA_DECOERR_DECOINTERNAL  0x11
 614#define JRSTA_DECOERR_SHDESCHDR     0x12
 615#define JRSTA_DECOERR_HDRLEN        0x13
 616#define JRSTA_DECOERR_BURSTER       0x14
 617#define JRSTA_DECOERR_DESCSIGNATURE 0x15
 618#define JRSTA_DECOERR_DMA           0x16
 619#define JRSTA_DECOERR_BURSTFIFO     0x17
 620#define JRSTA_DECOERR_JRRESET       0x1a
 621#define JRSTA_DECOERR_JOBFAIL       0x1b
 622#define JRSTA_DECOERR_DNRERR        0x80
 623#define JRSTA_DECOERR_UNDEFPCL      0x81
 624#define JRSTA_DECOERR_PDBERR        0x82
 625#define JRSTA_DECOERR_ANRPLY_LATE   0x83
 626#define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
 627#define JRSTA_DECOERR_SEQOVF        0x85
 628#define JRSTA_DECOERR_INVSIGN       0x86
 629#define JRSTA_DECOERR_DSASIGN       0x87
 630
 631#define JRSTA_CCBERR_JUMP           0x08000000
 632#define JRSTA_CCBERR_INDEX_MASK     0xff00
 633#define JRSTA_CCBERR_INDEX_SHIFT    8
 634#define JRSTA_CCBERR_CHAID_MASK     0x00f0
 635#define JRSTA_CCBERR_CHAID_SHIFT    4
 636#define JRSTA_CCBERR_ERRID_MASK     0x000f
 637
 638#define JRSTA_CCBERR_CHAID_AES      (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
 639#define JRSTA_CCBERR_CHAID_DES      (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
 640#define JRSTA_CCBERR_CHAID_ARC4     (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
 641#define JRSTA_CCBERR_CHAID_MD       (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
 642#define JRSTA_CCBERR_CHAID_RNG      (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
 643#define JRSTA_CCBERR_CHAID_SNOW     (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
 644#define JRSTA_CCBERR_CHAID_KASUMI   (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
 645#define JRSTA_CCBERR_CHAID_PK       (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
 646#define JRSTA_CCBERR_CHAID_CRC      (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
 647
 648#define JRSTA_CCBERR_ERRID_NONE     0x00
 649#define JRSTA_CCBERR_ERRID_MODE     0x01
 650#define JRSTA_CCBERR_ERRID_DATASIZ  0x02
 651#define JRSTA_CCBERR_ERRID_KEYSIZ   0x03
 652#define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
 653#define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
 654#define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
 655#define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
 656#define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
 657#define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
 658#define JRSTA_CCBERR_ERRID_ICVCHK   0x0a
 659#define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
 660#define JRSTA_CCBERR_ERRID_CCMAAD   0x0c
 661#define JRSTA_CCBERR_ERRID_INVCHA   0x0f
 662
 663#define JRINT_ERR_INDEX_MASK        0x3fff0000
 664#define JRINT_ERR_INDEX_SHIFT       16
 665#define JRINT_ERR_TYPE_MASK         0xf00
 666#define JRINT_ERR_TYPE_SHIFT        8
 667#define JRINT_ERR_HALT_MASK         0xc
 668#define JRINT_ERR_HALT_SHIFT        2
 669#define JRINT_ERR_HALT_INPROGRESS   0x4
 670#define JRINT_ERR_HALT_COMPLETE     0x8
 671#define JRINT_JR_ERROR              0x02
 672#define JRINT_JR_INT                0x01
 673
 674#define JRINT_ERR_TYPE_WRITE        1
 675#define JRINT_ERR_TYPE_BAD_INPADDR  3
 676#define JRINT_ERR_TYPE_BAD_OUTADDR  4
 677#define JRINT_ERR_TYPE_INV_INPWRT   5
 678#define JRINT_ERR_TYPE_INV_OUTWRT   6
 679#define JRINT_ERR_TYPE_RESET        7
 680#define JRINT_ERR_TYPE_REMOVE_OFL   8
 681#define JRINT_ERR_TYPE_ADD_OFL      9
 682
 683#define JRCFG_SOE               0x04
 684#define JRCFG_ICEN              0x02
 685#define JRCFG_IMSK              0x01
 686#define JRCFG_ICDCT_SHIFT       8
 687#define JRCFG_ICTT_SHIFT        16
 688
 689#define JRCR_RESET                  0x01
 690
 691/*
 692 * caam_assurance - Assurance Controller View
 693 * base + 0x6000 padded out to 0x1000
 694 */
 695
 696struct rtic_element {
 697        u64 address;
 698        u32 rsvd;
 699        u32 length;
 700};
 701
 702struct rtic_block {
 703        struct rtic_element element[2];
 704};
 705
 706struct rtic_memhash {
 707        u32 memhash_be[32];
 708        u32 memhash_le[32];
 709};
 710
 711struct caam_assurance {
 712    /* Status/Command/Watchdog */
 713        u32 rsvd1;
 714        u32 status;             /* RSTA - Status */
 715        u32 rsvd2;
 716        u32 cmd;                /* RCMD - Command */
 717        u32 rsvd3;
 718        u32 ctrl;               /* RCTL - Control */
 719        u32 rsvd4;
 720        u32 throttle;   /* RTHR - Throttle */
 721        u32 rsvd5[2];
 722        u64 watchdog;   /* RWDOG - Watchdog Timer */
 723        u32 rsvd6;
 724        u32 rend;               /* REND - Endian corrections */
 725        u32 rsvd7[50];
 726
 727        /* Block access/configuration @ 100/110/120/130 */
 728        struct rtic_block memblk[4];    /* Memory Blocks A-D */
 729        u32 rsvd8[32];
 730
 731        /* Block hashes @ 200/300/400/500 */
 732        struct rtic_memhash hash[4];    /* Block hash values A-D */
 733        u32 rsvd_3[640];
 734};
 735
 736/*
 737 * caam_queue_if - QI configuration and control
 738 * starts base + 0x7000, padded out to 0x1000 long
 739 */
 740
 741struct caam_queue_if {
 742        u32 qi_control_hi;      /* QICTL  - QI Control */
 743        u32 qi_control_lo;
 744        u32 rsvd1;
 745        u32 qi_status;  /* QISTA  - QI Status */
 746        u32 qi_deq_cfg_hi;      /* QIDQC  - QI Dequeue Configuration */
 747        u32 qi_deq_cfg_lo;
 748        u32 qi_enq_cfg_hi;      /* QISEQC - QI Enqueue Command     */
 749        u32 qi_enq_cfg_lo;
 750        u32 rsvd2[1016];
 751};
 752
 753/* QI control bits - low word */
 754#define QICTL_DQEN      0x01              /* Enable frame pop          */
 755#define QICTL_STOP      0x02              /* Stop dequeue/enqueue      */
 756#define QICTL_SOE       0x04              /* Stop on error             */
 757
 758/* QI control bits - high word */
 759#define QICTL_MBSI      0x01
 760#define QICTL_MHWSI     0x02
 761#define QICTL_MWSI      0x04
 762#define QICTL_MDWSI     0x08
 763#define QICTL_CBSI      0x10            /* CtrlDataByteSwapInput     */
 764#define QICTL_CHWSI     0x20            /* CtrlDataHalfSwapInput     */
 765#define QICTL_CWSI      0x40            /* CtrlDataWordSwapInput     */
 766#define QICTL_CDWSI     0x80            /* CtrlDataDWordSwapInput    */
 767#define QICTL_MBSO      0x0100
 768#define QICTL_MHWSO     0x0200
 769#define QICTL_MWSO      0x0400
 770#define QICTL_MDWSO     0x0800
 771#define QICTL_CBSO      0x1000          /* CtrlDataByteSwapOutput    */
 772#define QICTL_CHWSO     0x2000          /* CtrlDataHalfSwapOutput    */
 773#define QICTL_CWSO      0x4000          /* CtrlDataWordSwapOutput    */
 774#define QICTL_CDWSO     0x8000          /* CtrlDataDWordSwapOutput   */
 775#define QICTL_DMBS      0x010000
 776#define QICTL_EPO       0x020000
 777
 778/* QI status bits */
 779#define QISTA_PHRDERR   0x01              /* PreHeader Read Error      */
 780#define QISTA_CFRDERR   0x02              /* Compound Frame Read Error */
 781#define QISTA_OFWRERR   0x04              /* Output Frame Read Error   */
 782#define QISTA_BPDERR    0x08              /* Buffer Pool Depleted      */
 783#define QISTA_BTSERR    0x10              /* Buffer Undersize          */
 784#define QISTA_CFWRERR   0x20              /* Compound Frame Write Err  */
 785#define QISTA_STOPD     0x80000000        /* QI Stopped (see QICTL)    */
 786
 787/* deco_sg_table - DECO view of scatter/gather table */
 788struct deco_sg_table {
 789        u64 addr;               /* Segment Address */
 790        u32 elen;               /* E, F bits + 30-bit length */
 791        u32 bpid_offset;        /* Buffer Pool ID + 16-bit length */
 792};
 793
 794/*
 795 * caam_deco - descriptor controller - CHA cluster block
 796 *
 797 * Only accessible when direct DECO access is turned on
 798 * (done in DECORR, via MID programmed in DECOxMID
 799 *
 800 * 5 typical, base + 0x8000/9000/a000/b000
 801 * Padded out to 0x1000 long
 802 */
 803struct caam_deco {
 804        u32 rsvd1;
 805        u32 cls1_mode;  /* CxC1MR -  Class 1 Mode */
 806        u32 rsvd2;
 807        u32 cls1_keysize;       /* CxC1KSR - Class 1 Key Size */
 808        u32 cls1_datasize_hi;   /* CxC1DSR - Class 1 Data Size */
 809        u32 cls1_datasize_lo;
 810        u32 rsvd3;
 811        u32 cls1_icvsize;       /* CxC1ICVSR - Class 1 ICV size */
 812        u32 rsvd4[5];
 813        u32 cha_ctrl;   /* CCTLR - CHA control */
 814        u32 rsvd5;
 815        u32 irq_crtl;   /* CxCIRQ - CCB interrupt done/error/clear */
 816        u32 rsvd6;
 817        u32 clr_written;        /* CxCWR - Clear-Written */
 818        u32 ccb_status_hi;      /* CxCSTA - CCB Status/Error */
 819        u32 ccb_status_lo;
 820        u32 rsvd7[3];
 821        u32 aad_size;   /* CxAADSZR - Current AAD Size */
 822        u32 rsvd8;
 823        u32 cls1_iv_size;       /* CxC1IVSZR - Current Class 1 IV Size */
 824        u32 rsvd9[7];
 825        u32 pkha_a_size;        /* PKASZRx - Size of PKHA A */
 826        u32 rsvd10;
 827        u32 pkha_b_size;        /* PKBSZRx - Size of PKHA B */
 828        u32 rsvd11;
 829        u32 pkha_n_size;        /* PKNSZRx - Size of PKHA N */
 830        u32 rsvd12;
 831        u32 pkha_e_size;        /* PKESZRx - Size of PKHA E */
 832        u32 rsvd13[24];
 833        u32 cls1_ctx[16];       /* CxC1CTXR - Class 1 Context @100 */
 834        u32 rsvd14[48];
 835        u32 cls1_key[8];        /* CxC1KEYR - Class 1 Key @200 */
 836        u32 rsvd15[121];
 837        u32 cls2_mode;  /* CxC2MR - Class 2 Mode */
 838        u32 rsvd16;
 839        u32 cls2_keysize;       /* CxX2KSR - Class 2 Key Size */
 840        u32 cls2_datasize_hi;   /* CxC2DSR - Class 2 Data Size */
 841        u32 cls2_datasize_lo;
 842        u32 rsvd17;
 843        u32 cls2_icvsize;       /* CxC2ICVSZR - Class 2 ICV Size */
 844        u32 rsvd18[56];
 845        u32 cls2_ctx[18];       /* CxC2CTXR - Class 2 Context @500 */
 846        u32 rsvd19[46];
 847        u32 cls2_key[32];       /* CxC2KEYR - Class2 Key @600 */
 848        u32 rsvd20[84];
 849        u32 inp_infofifo_hi;    /* CxIFIFO - Input Info FIFO @7d0 */
 850        u32 inp_infofifo_lo;
 851        u32 rsvd21[2];
 852        u64 inp_datafifo;       /* CxDFIFO - Input Data FIFO */
 853        u32 rsvd22[2];
 854        u64 out_datafifo;       /* CxOFIFO - Output Data FIFO */
 855        u32 rsvd23[2];
 856        u32 jr_ctl_hi;  /* CxJRR - JobR Control Register      @800 */
 857        u32 jr_ctl_lo;
 858        u64 jr_descaddr;        /* CxDADR - JobR Descriptor Address */
 859#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
 860        u32 op_status_hi;       /* DxOPSTA - DECO Operation Status */
 861        u32 op_status_lo;
 862        u32 rsvd24[2];
 863        u32 liodn;              /* DxLSR - DECO LIODN Status - non-seq */
 864        u32 td_liodn;   /* DxLSR - DECO LIODN Status - trustdesc */
 865        u32 rsvd26[6];
 866        u64 math[4];            /* DxMTH - Math register */
 867        u32 rsvd27[8];
 868        struct deco_sg_table gthr_tbl[4];       /* DxGTR - Gather Tables */
 869        u32 rsvd28[16];
 870        struct deco_sg_table sctr_tbl[4];       /* DxSTR - Scatter Tables */
 871        u32 rsvd29[48];
 872        u32 descbuf[64];        /* DxDESB - Descriptor buffer */
 873        u32 rscvd30[193];
 874#define DESC_DBG_DECO_STAT_HOST_ERR     0x00D00000
 875#define DESC_DBG_DECO_STAT_VALID        0x80000000
 876#define DESC_DBG_DECO_STAT_MASK         0x00F00000
 877        u32 desc_dbg;           /* DxDDR - DECO Debug Register */
 878        u32 rsvd31[126];
 879};
 880
 881#define DECO_JQCR_WHL           0x20000000
 882#define DECO_JQCR_FOUR          0x10000000
 883
 884#define JR_BLOCK_NUMBER         1
 885#define ASSURE_BLOCK_NUMBER     6
 886#define QI_BLOCK_NUMBER         7
 887#define DECO_BLOCK_NUMBER       8
 888#define PG_SIZE_4K              0x1000
 889#define PG_SIZE_64K             0x10000
 890#endif /* REGS_H */
 891