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31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <linux/mmu_notifier.h>
34#include <linux/interval_tree.h>
35#include <drm/drmP.h>
36#include <drm/drm.h>
37
38#include "amdgpu.h"
39
40struct amdgpu_mn {
41
42 struct amdgpu_device *adev;
43 struct mm_struct *mm;
44 struct mmu_notifier mn;
45
46
47 struct work_struct work;
48
49
50 struct hlist_node node;
51
52
53 struct mutex lock;
54 struct rb_root objects;
55};
56
57struct amdgpu_mn_node {
58 struct interval_tree_node it;
59 struct list_head bos;
60};
61
62
63
64
65
66
67
68
69static void amdgpu_mn_destroy(struct work_struct *work)
70{
71 struct amdgpu_mn *rmn = container_of(work, struct amdgpu_mn, work);
72 struct amdgpu_device *adev = rmn->adev;
73 struct amdgpu_mn_node *node, *next_node;
74 struct amdgpu_bo *bo, *next_bo;
75
76 mutex_lock(&adev->mn_lock);
77 mutex_lock(&rmn->lock);
78 hash_del(&rmn->node);
79 rbtree_postorder_for_each_entry_safe(node, next_node, &rmn->objects,
80 it.rb) {
81 list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
82 bo->mn = NULL;
83 list_del_init(&bo->mn_list);
84 }
85 kfree(node);
86 }
87 mutex_unlock(&rmn->lock);
88 mutex_unlock(&adev->mn_lock);
89 mmu_notifier_unregister_no_release(&rmn->mn, rmn->mm);
90 kfree(rmn);
91}
92
93
94
95
96
97
98
99
100
101static void amdgpu_mn_release(struct mmu_notifier *mn,
102 struct mm_struct *mm)
103{
104 struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
105 INIT_WORK(&rmn->work, amdgpu_mn_destroy);
106 schedule_work(&rmn->work);
107}
108
109
110
111
112
113
114
115
116
117static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
118 unsigned long start,
119 unsigned long end)
120{
121 struct amdgpu_bo *bo;
122 long r;
123
124 list_for_each_entry(bo, &node->bos, mn_list) {
125
126 if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
127 continue;
128
129 r = amdgpu_bo_reserve(bo, true);
130 if (r) {
131 DRM_ERROR("(%ld) failed to reserve user bo\n", r);
132 continue;
133 }
134
135 r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
136 true, false, MAX_SCHEDULE_TIMEOUT);
137 if (r <= 0)
138 DRM_ERROR("(%ld) failed to wait for user bo\n", r);
139
140 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
141 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
142 if (r)
143 DRM_ERROR("(%ld) failed to validate user bo\n", r);
144
145 amdgpu_bo_unreserve(bo);
146 }
147}
148
149
150
151
152
153
154
155
156
157
158
159static void amdgpu_mn_invalidate_page(struct mmu_notifier *mn,
160 struct mm_struct *mm,
161 unsigned long address)
162{
163 struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
164 struct interval_tree_node *it;
165
166 mutex_lock(&rmn->lock);
167
168 it = interval_tree_iter_first(&rmn->objects, address, address);
169 if (it) {
170 struct amdgpu_mn_node *node;
171
172 node = container_of(it, struct amdgpu_mn_node, it);
173 amdgpu_mn_invalidate_node(node, address, address);
174 }
175
176 mutex_unlock(&rmn->lock);
177}
178
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187
188
189
190static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
191 struct mm_struct *mm,
192 unsigned long start,
193 unsigned long end)
194{
195 struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
196 struct interval_tree_node *it;
197
198
199 end -= 1;
200
201 mutex_lock(&rmn->lock);
202
203 it = interval_tree_iter_first(&rmn->objects, start, end);
204 while (it) {
205 struct amdgpu_mn_node *node;
206
207 node = container_of(it, struct amdgpu_mn_node, it);
208 it = interval_tree_iter_next(it, start, end);
209
210 amdgpu_mn_invalidate_node(node, start, end);
211 }
212
213 mutex_unlock(&rmn->lock);
214}
215
216static const struct mmu_notifier_ops amdgpu_mn_ops = {
217 .release = amdgpu_mn_release,
218 .invalidate_page = amdgpu_mn_invalidate_page,
219 .invalidate_range_start = amdgpu_mn_invalidate_range_start,
220};
221
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225
226
227
228
229static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
230{
231 struct mm_struct *mm = current->mm;
232 struct amdgpu_mn *rmn;
233 int r;
234
235 mutex_lock(&adev->mn_lock);
236 if (down_write_killable(&mm->mmap_sem)) {
237 mutex_unlock(&adev->mn_lock);
238 return ERR_PTR(-EINTR);
239 }
240
241 hash_for_each_possible(adev->mn_hash, rmn, node, (unsigned long)mm)
242 if (rmn->mm == mm)
243 goto release_locks;
244
245 rmn = kzalloc(sizeof(*rmn), GFP_KERNEL);
246 if (!rmn) {
247 rmn = ERR_PTR(-ENOMEM);
248 goto release_locks;
249 }
250
251 rmn->adev = adev;
252 rmn->mm = mm;
253 rmn->mn.ops = &amdgpu_mn_ops;
254 mutex_init(&rmn->lock);
255 rmn->objects = RB_ROOT;
256
257 r = __mmu_notifier_register(&rmn->mn, mm);
258 if (r)
259 goto free_rmn;
260
261 hash_add(adev->mn_hash, &rmn->node, (unsigned long)mm);
262
263release_locks:
264 up_write(&mm->mmap_sem);
265 mutex_unlock(&adev->mn_lock);
266
267 return rmn;
268
269free_rmn:
270 up_write(&mm->mmap_sem);
271 mutex_unlock(&adev->mn_lock);
272 kfree(rmn);
273
274 return ERR_PTR(r);
275}
276
277
278
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280
281
282
283
284
285
286int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
287{
288 unsigned long end = addr + amdgpu_bo_size(bo) - 1;
289 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
290 struct amdgpu_mn *rmn;
291 struct amdgpu_mn_node *node = NULL;
292 struct list_head bos;
293 struct interval_tree_node *it;
294
295 rmn = amdgpu_mn_get(adev);
296 if (IS_ERR(rmn))
297 return PTR_ERR(rmn);
298
299 INIT_LIST_HEAD(&bos);
300
301 mutex_lock(&rmn->lock);
302
303 while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) {
304 kfree(node);
305 node = container_of(it, struct amdgpu_mn_node, it);
306 interval_tree_remove(&node->it, &rmn->objects);
307 addr = min(it->start, addr);
308 end = max(it->last, end);
309 list_splice(&node->bos, &bos);
310 }
311
312 if (!node) {
313 node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL);
314 if (!node) {
315 mutex_unlock(&rmn->lock);
316 return -ENOMEM;
317 }
318 }
319
320 bo->mn = rmn;
321
322 node->it.start = addr;
323 node->it.last = end;
324 INIT_LIST_HEAD(&node->bos);
325 list_splice(&bos, &node->bos);
326 list_add(&bo->mn_list, &node->bos);
327
328 interval_tree_insert(&node->it, &rmn->objects);
329
330 mutex_unlock(&rmn->lock);
331
332 return 0;
333}
334
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336
337
338
339
340
341
342void amdgpu_mn_unregister(struct amdgpu_bo *bo)
343{
344 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
345 struct amdgpu_mn *rmn;
346 struct list_head *head;
347
348 mutex_lock(&adev->mn_lock);
349
350 rmn = bo->mn;
351 if (rmn == NULL) {
352 mutex_unlock(&adev->mn_lock);
353 return;
354 }
355
356 mutex_lock(&rmn->lock);
357
358
359 head = bo->mn_list.next;
360
361 bo->mn = NULL;
362 list_del(&bo->mn_list);
363
364 if (list_empty(head)) {
365 struct amdgpu_mn_node *node;
366 node = container_of(head, struct amdgpu_mn_node, bos);
367 interval_tree_remove(&node->it, &rmn->objects);
368 kfree(node);
369 }
370
371 mutex_unlock(&rmn->lock);
372 mutex_unlock(&adev->mn_lock);
373}
374