LXR linux/drivers/gpu/drm/amd/amdgpu/soc15

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#ifndef __SOC15_COMMON_H__
  25#define __SOC15_COMMON_H__
  26
  27struct nbio_hdp_flush_reg {
  28        u32 hdp_flush_req_offset;
  29        u32 hdp_flush_done_offset;
  30        u32 ref_and_mask_cp0;
  31        u32 ref_and_mask_cp1;
  32        u32 ref_and_mask_cp2;
  33        u32 ref_and_mask_cp3;
  34        u32 ref_and_mask_cp4;
  35        u32 ref_and_mask_cp5;
  36        u32 ref_and_mask_cp6;
  37        u32 ref_and_mask_cp7;
  38        u32 ref_and_mask_cp8;
  39        u32 ref_and_mask_cp9;
  40        u32 ref_and_mask_sdma0;
  41        u32 ref_and_mask_sdma1;
  42};
  43
  44struct nbio_pcie_index_data {
  45        u32 index_offset;
  46        u32 data_offset;
  47};
  48
  49/* Register Access Macros */
  50#define SOC15_REG_OFFSET(ip, inst, reg)       (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
  51                                                (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
  52                                                    (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
  53                                                        (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
  54                                                            (ip##_BASE__INST##inst##_SEG4 + reg)))))
  55
  56#define WREG32_FIELD15(ip, idx, reg, field, val)        \
  57        WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
  58
  59#define RREG32_SOC15(ip, inst, reg) \
  60        RREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
  61                (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
  62                (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
  63                (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
  64                (ip##_BASE__INST##inst##_SEG4 + reg))))))
  65
  66#define WREG32_SOC15(ip, inst, reg, value) \
  67        WREG32( (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \
  68                (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \
  69                (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \
  70                (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \
  71                (ip##_BASE__INST##inst##_SEG4 + reg))))), value)
  72
  73#endif
  74
  75
  76