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14#include <drm/drmP.h>
15#include <drm/exynos_drm.h>
16
17#include <linux/clk.h>
18#include <linux/component.h>
19#include <linux/kernel.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25
26#include <video/of_display_timing.h>
27#include <video/of_videomode.h>
28#include <video/exynos7_decon.h>
29
30#include "exynos_drm_crtc.h"
31#include "exynos_drm_plane.h"
32#include "exynos_drm_drv.h"
33#include "exynos_drm_fb.h"
34#include "exynos_drm_iommu.h"
35
36
37
38
39
40#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
41
42#define WINDOWS_NR 2
43
44struct decon_context {
45 struct device *dev;
46 struct drm_device *drm_dev;
47 struct exynos_drm_crtc *crtc;
48 struct exynos_drm_plane planes[WINDOWS_NR];
49 struct exynos_drm_plane_config configs[WINDOWS_NR];
50 struct clk *pclk;
51 struct clk *aclk;
52 struct clk *eclk;
53 struct clk *vclk;
54 void __iomem *regs;
55 unsigned long irq_flags;
56 bool i80_if;
57 bool suspended;
58 int pipe;
59 wait_queue_head_t wait_vsync_queue;
60 atomic_t wait_vsync_event;
61
62 struct drm_encoder *encoder;
63};
64
65static const struct of_device_id decon_driver_dt_match[] = {
66 {.compatible = "samsung,exynos7-decon"},
67 {},
68};
69MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
70
71static const uint32_t decon_formats[] = {
72 DRM_FORMAT_RGB565,
73 DRM_FORMAT_XRGB8888,
74 DRM_FORMAT_XBGR8888,
75 DRM_FORMAT_RGBX8888,
76 DRM_FORMAT_BGRX8888,
77 DRM_FORMAT_ARGB8888,
78 DRM_FORMAT_ABGR8888,
79 DRM_FORMAT_RGBA8888,
80 DRM_FORMAT_BGRA8888,
81};
82
83static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
84 DRM_PLANE_TYPE_PRIMARY,
85 DRM_PLANE_TYPE_CURSOR,
86};
87
88static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
89{
90 struct decon_context *ctx = crtc->ctx;
91
92 if (ctx->suspended)
93 return;
94
95 atomic_set(&ctx->wait_vsync_event, 1);
96
97
98
99
100
101 if (!wait_event_timeout(ctx->wait_vsync_queue,
102 !atomic_read(&ctx->wait_vsync_event),
103 HZ/20))
104 DRM_DEBUG_KMS("vblank wait timed out.\n");
105}
106
107static void decon_clear_channels(struct exynos_drm_crtc *crtc)
108{
109 struct decon_context *ctx = crtc->ctx;
110 unsigned int win, ch_enabled = 0;
111
112 DRM_DEBUG_KMS("%s\n", __FILE__);
113
114
115 for (win = 0; win < WINDOWS_NR; win++) {
116 u32 val = readl(ctx->regs + WINCON(win));
117
118 if (val & WINCONx_ENWIN) {
119 val &= ~WINCONx_ENWIN;
120 writel(val, ctx->regs + WINCON(win));
121 ch_enabled = 1;
122 }
123 }
124
125
126 if (ch_enabled)
127 decon_wait_for_vblank(ctx->crtc);
128}
129
130static int decon_ctx_initialize(struct decon_context *ctx,
131 struct drm_device *drm_dev)
132{
133 struct exynos_drm_private *priv = drm_dev->dev_private;
134 int ret;
135
136 ctx->drm_dev = drm_dev;
137 ctx->pipe = priv->pipe++;
138
139 decon_clear_channels(ctx->crtc);
140
141 ret = drm_iommu_attach_device(drm_dev, ctx->dev);
142 if (ret)
143 priv->pipe--;
144
145 return ret;
146}
147
148static void decon_ctx_remove(struct decon_context *ctx)
149{
150
151 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
152}
153
154static u32 decon_calc_clkdiv(struct decon_context *ctx,
155 const struct drm_display_mode *mode)
156{
157 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
158 u32 clkdiv;
159
160
161 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
162
163 return (clkdiv < 0x100) ? clkdiv : 0xff;
164}
165
166static void decon_commit(struct exynos_drm_crtc *crtc)
167{
168 struct decon_context *ctx = crtc->ctx;
169 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
170 u32 val, clkdiv;
171
172 if (ctx->suspended)
173 return;
174
175
176 if (mode->htotal == 0 || mode->vtotal == 0)
177 return;
178
179 if (!ctx->i80_if) {
180 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
181
182 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
183 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
184 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
185
186 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
187 writel(val, ctx->regs + VIDTCON0);
188
189 val = VIDTCON1_VSPW(vsync_len - 1);
190 writel(val, ctx->regs + VIDTCON1);
191
192
193 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
194 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
195 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
196
197
198 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
199 writel(val, ctx->regs + VIDTCON2);
200
201 val = VIDTCON3_HSPW(hsync_len - 1);
202 writel(val, ctx->regs + VIDTCON3);
203 }
204
205
206 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
207 VIDTCON4_HOZVAL(mode->hdisplay - 1);
208 writel(val, ctx->regs + VIDTCON4);
209
210 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
211
212
213
214
215
216 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
217 writel(val, ctx->regs + VIDCON0);
218
219 clkdiv = decon_calc_clkdiv(ctx, mode);
220 if (clkdiv > 1) {
221 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
222 writel(val, ctx->regs + VCLKCON1);
223 writel(val, ctx->regs + VCLKCON2);
224 }
225
226 val = readl(ctx->regs + DECON_UPDATE);
227 val |= DECON_UPDATE_STANDALONE_F;
228 writel(val, ctx->regs + DECON_UPDATE);
229}
230
231static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
232{
233 struct decon_context *ctx = crtc->ctx;
234 u32 val;
235
236 if (ctx->suspended)
237 return -EPERM;
238
239 if (!test_and_set_bit(0, &ctx->irq_flags)) {
240 val = readl(ctx->regs + VIDINTCON0);
241
242 val |= VIDINTCON0_INT_ENABLE;
243
244 if (!ctx->i80_if) {
245 val |= VIDINTCON0_INT_FRAME;
246 val &= ~VIDINTCON0_FRAMESEL0_MASK;
247 val |= VIDINTCON0_FRAMESEL0_VSYNC;
248 }
249
250 writel(val, ctx->regs + VIDINTCON0);
251 }
252
253 return 0;
254}
255
256static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
257{
258 struct decon_context *ctx = crtc->ctx;
259 u32 val;
260
261 if (ctx->suspended)
262 return;
263
264 if (test_and_clear_bit(0, &ctx->irq_flags)) {
265 val = readl(ctx->regs + VIDINTCON0);
266
267 val &= ~VIDINTCON0_INT_ENABLE;
268 if (!ctx->i80_if)
269 val &= ~VIDINTCON0_INT_FRAME;
270
271 writel(val, ctx->regs + VIDINTCON0);
272 }
273}
274
275static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
276 struct drm_framebuffer *fb)
277{
278 unsigned long val;
279 int padding;
280
281 val = readl(ctx->regs + WINCON(win));
282 val &= ~WINCONx_BPPMODE_MASK;
283
284 switch (fb->format->format) {
285 case DRM_FORMAT_RGB565:
286 val |= WINCONx_BPPMODE_16BPP_565;
287 val |= WINCONx_BURSTLEN_16WORD;
288 break;
289 case DRM_FORMAT_XRGB8888:
290 val |= WINCONx_BPPMODE_24BPP_xRGB;
291 val |= WINCONx_BURSTLEN_16WORD;
292 break;
293 case DRM_FORMAT_XBGR8888:
294 val |= WINCONx_BPPMODE_24BPP_xBGR;
295 val |= WINCONx_BURSTLEN_16WORD;
296 break;
297 case DRM_FORMAT_RGBX8888:
298 val |= WINCONx_BPPMODE_24BPP_RGBx;
299 val |= WINCONx_BURSTLEN_16WORD;
300 break;
301 case DRM_FORMAT_BGRX8888:
302 val |= WINCONx_BPPMODE_24BPP_BGRx;
303 val |= WINCONx_BURSTLEN_16WORD;
304 break;
305 case DRM_FORMAT_ARGB8888:
306 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
307 WINCONx_ALPHA_SEL;
308 val |= WINCONx_BURSTLEN_16WORD;
309 break;
310 case DRM_FORMAT_ABGR8888:
311 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
312 WINCONx_ALPHA_SEL;
313 val |= WINCONx_BURSTLEN_16WORD;
314 break;
315 case DRM_FORMAT_RGBA8888:
316 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
317 WINCONx_ALPHA_SEL;
318 val |= WINCONx_BURSTLEN_16WORD;
319 break;
320 case DRM_FORMAT_BGRA8888:
321 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
322 WINCONx_ALPHA_SEL;
323 val |= WINCONx_BURSTLEN_16WORD;
324 break;
325 default:
326 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
327
328 val |= WINCONx_BPPMODE_24BPP_xRGB;
329 val |= WINCONx_BURSTLEN_16WORD;
330 break;
331 }
332
333 DRM_DEBUG_KMS("bpp = %d\n", fb->format->cpp[0] * 8);
334
335
336
337
338
339
340
341
342
343 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;
344 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
345 val &= ~WINCONx_BURSTLEN_MASK;
346 val |= WINCONx_BURSTLEN_8WORD;
347 }
348
349 writel(val, ctx->regs + WINCON(win));
350}
351
352static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
353{
354 unsigned int keycon0 = 0, keycon1 = 0;
355
356 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
357 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
358
359 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
360
361 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
362 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
363}
364
365
366
367
368
369
370
371static void decon_shadow_protect_win(struct decon_context *ctx,
372 unsigned int win, bool protect)
373{
374 u32 bits, val;
375
376 bits = SHADOWCON_WINx_PROTECT(win);
377
378 val = readl(ctx->regs + SHADOWCON);
379 if (protect)
380 val |= bits;
381 else
382 val &= ~bits;
383 writel(val, ctx->regs + SHADOWCON);
384}
385
386static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
387{
388 struct decon_context *ctx = crtc->ctx;
389 int i;
390
391 if (ctx->suspended)
392 return;
393
394 for (i = 0; i < WINDOWS_NR; i++)
395 decon_shadow_protect_win(ctx, i, true);
396}
397
398static void decon_update_plane(struct exynos_drm_crtc *crtc,
399 struct exynos_drm_plane *plane)
400{
401 struct exynos_drm_plane_state *state =
402 to_exynos_plane_state(plane->base.state);
403 struct decon_context *ctx = crtc->ctx;
404 struct drm_framebuffer *fb = state->base.fb;
405 int padding;
406 unsigned long val, alpha;
407 unsigned int last_x;
408 unsigned int last_y;
409 unsigned int win = plane->index;
410 unsigned int bpp = fb->format->cpp[0];
411 unsigned int pitch = fb->pitches[0];
412
413 if (ctx->suspended)
414 return;
415
416
417
418
419
420
421
422
423
424
425
426
427 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
428 writel(val, ctx->regs + VIDW_BUF_START(win));
429
430 padding = (pitch / bpp) - fb->width;
431
432
433 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
434 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
435
436
437 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
438 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
439
440 DRM_DEBUG_KMS("start addr = 0x%lx\n",
441 (unsigned long)val);
442 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
443 state->crtc.w, state->crtc.h);
444
445 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
446 VIDOSDxA_TOPLEFT_Y(state->crtc.y);
447 writel(val, ctx->regs + VIDOSD_A(win));
448
449 last_x = state->crtc.x + state->crtc.w;
450 if (last_x)
451 last_x--;
452 last_y = state->crtc.y + state->crtc.h;
453 if (last_y)
454 last_y--;
455
456 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
457
458 writel(val, ctx->regs + VIDOSD_B(win));
459
460 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
461 state->crtc.x, state->crtc.y, last_x, last_y);
462
463
464 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
465 VIDOSDxC_ALPHA0_G_F(0x0) |
466 VIDOSDxC_ALPHA0_B_F(0x0);
467
468 writel(alpha, ctx->regs + VIDOSD_C(win));
469
470 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
471 VIDOSDxD_ALPHA1_G_F(0xff) |
472 VIDOSDxD_ALPHA1_B_F(0xff);
473
474 writel(alpha, ctx->regs + VIDOSD_D(win));
475
476 decon_win_set_pixfmt(ctx, win, fb);
477
478
479 if (win != 0)
480 decon_win_set_colkey(ctx, win);
481
482
483 val = readl(ctx->regs + WINCON(win));
484 val |= WINCONx_TRIPLE_BUF_MODE;
485 val |= WINCONx_ENWIN;
486 writel(val, ctx->regs + WINCON(win));
487
488
489 decon_shadow_protect_win(ctx, win, false);
490
491 val = readl(ctx->regs + DECON_UPDATE);
492 val |= DECON_UPDATE_STANDALONE_F;
493 writel(val, ctx->regs + DECON_UPDATE);
494}
495
496static void decon_disable_plane(struct exynos_drm_crtc *crtc,
497 struct exynos_drm_plane *plane)
498{
499 struct decon_context *ctx = crtc->ctx;
500 unsigned int win = plane->index;
501 u32 val;
502
503 if (ctx->suspended)
504 return;
505
506
507 decon_shadow_protect_win(ctx, win, true);
508
509
510 val = readl(ctx->regs + WINCON(win));
511 val &= ~WINCONx_ENWIN;
512 writel(val, ctx->regs + WINCON(win));
513
514 val = readl(ctx->regs + DECON_UPDATE);
515 val |= DECON_UPDATE_STANDALONE_F;
516 writel(val, ctx->regs + DECON_UPDATE);
517}
518
519static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
520{
521 struct decon_context *ctx = crtc->ctx;
522 int i;
523
524 if (ctx->suspended)
525 return;
526
527 for (i = 0; i < WINDOWS_NR; i++)
528 decon_shadow_protect_win(ctx, i, false);
529 exynos_crtc_handle_event(crtc);
530}
531
532static void decon_init(struct decon_context *ctx)
533{
534 u32 val;
535
536 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
537
538 val = VIDOUTCON0_DISP_IF_0_ON;
539 if (!ctx->i80_if)
540 val |= VIDOUTCON0_RGBIF;
541 writel(val, ctx->regs + VIDOUTCON0);
542
543 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
544
545 if (!ctx->i80_if)
546 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
547}
548
549static void decon_enable(struct exynos_drm_crtc *crtc)
550{
551 struct decon_context *ctx = crtc->ctx;
552
553 if (!ctx->suspended)
554 return;
555
556 pm_runtime_get_sync(ctx->dev);
557
558 decon_init(ctx);
559
560
561 if (test_and_clear_bit(0, &ctx->irq_flags))
562 decon_enable_vblank(ctx->crtc);
563
564 decon_commit(ctx->crtc);
565
566 ctx->suspended = false;
567}
568
569static void decon_disable(struct exynos_drm_crtc *crtc)
570{
571 struct decon_context *ctx = crtc->ctx;
572 int i;
573
574 if (ctx->suspended)
575 return;
576
577
578
579
580
581
582 for (i = 0; i < WINDOWS_NR; i++)
583 decon_disable_plane(crtc, &ctx->planes[i]);
584
585 pm_runtime_put_sync(ctx->dev);
586
587 ctx->suspended = true;
588}
589
590static const struct exynos_drm_crtc_ops decon_crtc_ops = {
591 .enable = decon_enable,
592 .disable = decon_disable,
593 .commit = decon_commit,
594 .enable_vblank = decon_enable_vblank,
595 .disable_vblank = decon_disable_vblank,
596 .atomic_begin = decon_atomic_begin,
597 .update_plane = decon_update_plane,
598 .disable_plane = decon_disable_plane,
599 .atomic_flush = decon_atomic_flush,
600};
601
602
603static irqreturn_t decon_irq_handler(int irq, void *dev_id)
604{
605 struct decon_context *ctx = (struct decon_context *)dev_id;
606 u32 val, clear_bit;
607
608 val = readl(ctx->regs + VIDINTCON1);
609
610 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
611 if (val & clear_bit)
612 writel(clear_bit, ctx->regs + VIDINTCON1);
613
614
615 if (ctx->pipe < 0 || !ctx->drm_dev)
616 goto out;
617
618 if (!ctx->i80_if) {
619 drm_crtc_handle_vblank(&ctx->crtc->base);
620
621
622 if (atomic_read(&ctx->wait_vsync_event)) {
623 atomic_set(&ctx->wait_vsync_event, 0);
624 wake_up(&ctx->wait_vsync_queue);
625 }
626 }
627out:
628 return IRQ_HANDLED;
629}
630
631static int decon_bind(struct device *dev, struct device *master, void *data)
632{
633 struct decon_context *ctx = dev_get_drvdata(dev);
634 struct drm_device *drm_dev = data;
635 struct exynos_drm_plane *exynos_plane;
636 unsigned int i;
637 int ret;
638
639 ret = decon_ctx_initialize(ctx, drm_dev);
640 if (ret) {
641 DRM_ERROR("decon_ctx_initialize failed.\n");
642 return ret;
643 }
644
645 for (i = 0; i < WINDOWS_NR; i++) {
646 ctx->configs[i].pixel_formats = decon_formats;
647 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
648 ctx->configs[i].zpos = i;
649 ctx->configs[i].type = decon_win_types[i];
650
651 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
652 1 << ctx->pipe, &ctx->configs[i]);
653 if (ret)
654 return ret;
655 }
656
657 exynos_plane = &ctx->planes[DEFAULT_WIN];
658 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
659 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
660 &decon_crtc_ops, ctx);
661 if (IS_ERR(ctx->crtc)) {
662 decon_ctx_remove(ctx);
663 return PTR_ERR(ctx->crtc);
664 }
665
666 if (ctx->encoder)
667 exynos_dpi_bind(drm_dev, ctx->encoder);
668
669 return 0;
670
671}
672
673static void decon_unbind(struct device *dev, struct device *master,
674 void *data)
675{
676 struct decon_context *ctx = dev_get_drvdata(dev);
677
678 decon_disable(ctx->crtc);
679
680 if (ctx->encoder)
681 exynos_dpi_remove(ctx->encoder);
682
683 decon_ctx_remove(ctx);
684}
685
686static const struct component_ops decon_component_ops = {
687 .bind = decon_bind,
688 .unbind = decon_unbind,
689};
690
691static int decon_probe(struct platform_device *pdev)
692{
693 struct device *dev = &pdev->dev;
694 struct decon_context *ctx;
695 struct device_node *i80_if_timings;
696 struct resource *res;
697 int ret;
698
699 if (!dev->of_node)
700 return -ENODEV;
701
702 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
703 if (!ctx)
704 return -ENOMEM;
705
706 ctx->dev = dev;
707 ctx->suspended = true;
708
709 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
710 if (i80_if_timings)
711 ctx->i80_if = true;
712 of_node_put(i80_if_timings);
713
714 ctx->regs = of_iomap(dev->of_node, 0);
715 if (!ctx->regs)
716 return -ENOMEM;
717
718 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
719 if (IS_ERR(ctx->pclk)) {
720 dev_err(dev, "failed to get bus clock pclk\n");
721 ret = PTR_ERR(ctx->pclk);
722 goto err_iounmap;
723 }
724
725 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
726 if (IS_ERR(ctx->aclk)) {
727 dev_err(dev, "failed to get bus clock aclk\n");
728 ret = PTR_ERR(ctx->aclk);
729 goto err_iounmap;
730 }
731
732 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
733 if (IS_ERR(ctx->eclk)) {
734 dev_err(dev, "failed to get eclock\n");
735 ret = PTR_ERR(ctx->eclk);
736 goto err_iounmap;
737 }
738
739 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
740 if (IS_ERR(ctx->vclk)) {
741 dev_err(dev, "failed to get vclock\n");
742 ret = PTR_ERR(ctx->vclk);
743 goto err_iounmap;
744 }
745
746 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
747 ctx->i80_if ? "lcd_sys" : "vsync");
748 if (!res) {
749 dev_err(dev, "irq request failed.\n");
750 ret = -ENXIO;
751 goto err_iounmap;
752 }
753
754 ret = devm_request_irq(dev, res->start, decon_irq_handler,
755 0, "drm_decon", ctx);
756 if (ret) {
757 dev_err(dev, "irq request failed.\n");
758 goto err_iounmap;
759 }
760
761 init_waitqueue_head(&ctx->wait_vsync_queue);
762 atomic_set(&ctx->wait_vsync_event, 0);
763
764 platform_set_drvdata(pdev, ctx);
765
766 ctx->encoder = exynos_dpi_probe(dev);
767 if (IS_ERR(ctx->encoder)) {
768 ret = PTR_ERR(ctx->encoder);
769 goto err_iounmap;
770 }
771
772 pm_runtime_enable(dev);
773
774 ret = component_add(dev, &decon_component_ops);
775 if (ret)
776 goto err_disable_pm_runtime;
777
778 return ret;
779
780err_disable_pm_runtime:
781 pm_runtime_disable(dev);
782
783err_iounmap:
784 iounmap(ctx->regs);
785
786 return ret;
787}
788
789static int decon_remove(struct platform_device *pdev)
790{
791 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
792
793 pm_runtime_disable(&pdev->dev);
794
795 iounmap(ctx->regs);
796
797 component_del(&pdev->dev, &decon_component_ops);
798
799 return 0;
800}
801
802#ifdef CONFIG_PM
803static int exynos7_decon_suspend(struct device *dev)
804{
805 struct decon_context *ctx = dev_get_drvdata(dev);
806
807 clk_disable_unprepare(ctx->vclk);
808 clk_disable_unprepare(ctx->eclk);
809 clk_disable_unprepare(ctx->aclk);
810 clk_disable_unprepare(ctx->pclk);
811
812 return 0;
813}
814
815static int exynos7_decon_resume(struct device *dev)
816{
817 struct decon_context *ctx = dev_get_drvdata(dev);
818 int ret;
819
820 ret = clk_prepare_enable(ctx->pclk);
821 if (ret < 0) {
822 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
823 return ret;
824 }
825
826 ret = clk_prepare_enable(ctx->aclk);
827 if (ret < 0) {
828 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
829 return ret;
830 }
831
832 ret = clk_prepare_enable(ctx->eclk);
833 if (ret < 0) {
834 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
835 return ret;
836 }
837
838 ret = clk_prepare_enable(ctx->vclk);
839 if (ret < 0) {
840 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
841 return ret;
842 }
843
844 return 0;
845}
846#endif
847
848static const struct dev_pm_ops exynos7_decon_pm_ops = {
849 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
850 NULL)
851};
852
853struct platform_driver decon_driver = {
854 .probe = decon_probe,
855 .remove = decon_remove,
856 .driver = {
857 .name = "exynos-decon",
858 .pm = &exynos7_decon_pm_ops,
859 .of_match_table = decon_driver_dt_match,
860 },
861};
862
