1#ifndef __NVIF_CL0002_H__ 2#define __NVIF_CL0002_H__ 3 4struct nv_dma_v0 { 5 __u8 version; 6#define NV_DMA_V0_TARGET_VM 0x00 7#define NV_DMA_V0_TARGET_VRAM 0x01 8#define NV_DMA_V0_TARGET_PCI 0x02 9#define NV_DMA_V0_TARGET_PCI_US 0x03 10#define NV_DMA_V0_TARGET_AGP 0x04 11 __u8 target; 12#define NV_DMA_V0_ACCESS_VM 0x00 13#define NV_DMA_V0_ACCESS_RD 0x01 14#define NV_DMA_V0_ACCESS_WR 0x02 15#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 16 __u8 access; 17 __u8 pad03[5]; 18 __u64 start; 19 __u64 limit; 20 /* ... chipset-specific class data */ 21}; 22 23struct nv50_dma_v0 { 24 __u8 version; 25#define NV50_DMA_V0_PRIV_VM 0x00 26#define NV50_DMA_V0_PRIV_US 0x01 27#define NV50_DMA_V0_PRIV__S 0x02 28 __u8 priv; 29#define NV50_DMA_V0_PART_VM 0x00 30#define NV50_DMA_V0_PART_256 0x01 31#define NV50_DMA_V0_PART_1KB 0x02 32 __u8 part; 33#define NV50_DMA_V0_COMP_NONE 0x00 34#define NV50_DMA_V0_COMP_1 0x01 35#define NV50_DMA_V0_COMP_2 0x02 36#define NV50_DMA_V0_COMP_VM 0x03 37 __u8 comp; 38#define NV50_DMA_V0_KIND_PITCH 0x00 39#define NV50_DMA_V0_KIND_VM 0x7f 40 __u8 kind; 41 __u8 pad05[3]; 42}; 43 44struct gf100_dma_v0 { 45 __u8 version; 46#define GF100_DMA_V0_PRIV_VM 0x00 47#define GF100_DMA_V0_PRIV_US 0x01 48#define GF100_DMA_V0_PRIV__S 0x02 49 __u8 priv; 50#define GF100_DMA_V0_KIND_PITCH 0x00 51#define GF100_DMA_V0_KIND_VM 0xff 52 __u8 kind; 53 __u8 pad03[5]; 54}; 55 56struct gf119_dma_v0 { 57 __u8 version; 58#define GF119_DMA_V0_PAGE_LP 0x00 59#define GF119_DMA_V0_PAGE_SP 0x01 60 __u8 page; 61#define GF119_DMA_V0_KIND_PITCH 0x00 62#define GF119_DMA_V0_KIND_VM 0xff 63 __u8 kind; 64 __u8 pad03[5]; 65}; 66#endif 67