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20#ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21#define _ASM_X86_AMD_IOMMU_TYPES_H
22
23#include <linux/types.h>
24#include <linux/mutex.h>
25#include <linux/msi.h>
26#include <linux/list.h>
27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/irqreturn.h>
30
31
32
33
34#define MAX_IOMMUS 32
35
36
37
38
39#define DEV_TABLE_ENTRY_SIZE 32
40#define ALIAS_TABLE_ENTRY_SIZE 2
41#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
42
43
44#define MMIO_CAP_HDR_OFFSET 0x00
45#define MMIO_RANGE_OFFSET 0x0c
46#define MMIO_MISC_OFFSET 0x10
47
48
49#define MMIO_RANGE_LD_MASK 0xff000000
50#define MMIO_RANGE_FD_MASK 0x00ff0000
51#define MMIO_RANGE_BUS_MASK 0x0000ff00
52#define MMIO_RANGE_LD_SHIFT 24
53#define MMIO_RANGE_FD_SHIFT 16
54#define MMIO_RANGE_BUS_SHIFT 8
55#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58#define MMIO_MSI_NUM(x) ((x) & 0x1f)
59
60
61#define MMIO_EXCL_ENABLE_MASK 0x01ULL
62#define MMIO_EXCL_ALLOW_MASK 0x02ULL
63
64
65#define MMIO_DEV_TABLE_OFFSET 0x0000
66#define MMIO_CMD_BUF_OFFSET 0x0008
67#define MMIO_EVT_BUF_OFFSET 0x0010
68#define MMIO_CONTROL_OFFSET 0x0018
69#define MMIO_EXCL_BASE_OFFSET 0x0020
70#define MMIO_EXCL_LIMIT_OFFSET 0x0028
71#define MMIO_EXT_FEATURES 0x0030
72#define MMIO_PPR_LOG_OFFSET 0x0038
73#define MMIO_GA_LOG_BASE_OFFSET 0x00e0
74#define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
75#define MMIO_CMD_HEAD_OFFSET 0x2000
76#define MMIO_CMD_TAIL_OFFSET 0x2008
77#define MMIO_EVT_HEAD_OFFSET 0x2010
78#define MMIO_EVT_TAIL_OFFSET 0x2018
79#define MMIO_STATUS_OFFSET 0x2020
80#define MMIO_PPR_HEAD_OFFSET 0x2030
81#define MMIO_PPR_TAIL_OFFSET 0x2038
82#define MMIO_GA_HEAD_OFFSET 0x2040
83#define MMIO_GA_TAIL_OFFSET 0x2048
84#define MMIO_CNTR_CONF_OFFSET 0x4000
85#define MMIO_CNTR_REG_OFFSET 0x40000
86#define MMIO_REG_END_OFFSET 0x80000
87
88
89
90
91#define FEATURE_PREFETCH (1ULL<<0)
92#define FEATURE_PPR (1ULL<<1)
93#define FEATURE_X2APIC (1ULL<<2)
94#define FEATURE_NX (1ULL<<3)
95#define FEATURE_GT (1ULL<<4)
96#define FEATURE_IA (1ULL<<6)
97#define FEATURE_GA (1ULL<<7)
98#define FEATURE_HE (1ULL<<8)
99#define FEATURE_PC (1ULL<<9)
100#define FEATURE_GAM_VAPIC (1ULL<<21)
101
102#define FEATURE_PASID_SHIFT 32
103#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
104
105#define FEATURE_GLXVAL_SHIFT 14
106#define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
107
108
109
110
111
112
113#define PASID_MASK 0x0000ffff
114
115
116#define MMIO_STATUS_EVT_INT_MASK (1 << 1)
117#define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
118#define MMIO_STATUS_PPR_INT_MASK (1 << 6)
119#define MMIO_STATUS_GALOG_RUN_MASK (1 << 8)
120#define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
121#define MMIO_STATUS_GALOG_INT_MASK (1 << 10)
122
123
124#define EVENT_ENTRY_SIZE 0x10
125#define EVENT_TYPE_SHIFT 28
126#define EVENT_TYPE_MASK 0xf
127#define EVENT_TYPE_ILL_DEV 0x1
128#define EVENT_TYPE_IO_FAULT 0x2
129#define EVENT_TYPE_DEV_TAB_ERR 0x3
130#define EVENT_TYPE_PAGE_TAB_ERR 0x4
131#define EVENT_TYPE_ILL_CMD 0x5
132#define EVENT_TYPE_CMD_HARD_ERR 0x6
133#define EVENT_TYPE_IOTLB_INV_TO 0x7
134#define EVENT_TYPE_INV_DEV_REQ 0x8
135#define EVENT_DEVID_MASK 0xffff
136#define EVENT_DEVID_SHIFT 0
137#define EVENT_DOMID_MASK 0xffff
138#define EVENT_DOMID_SHIFT 0
139#define EVENT_FLAGS_MASK 0xfff
140#define EVENT_FLAGS_SHIFT 0x10
141
142
143#define CONTROL_IOMMU_EN 0x00ULL
144#define CONTROL_HT_TUN_EN 0x01ULL
145#define CONTROL_EVT_LOG_EN 0x02ULL
146#define CONTROL_EVT_INT_EN 0x03ULL
147#define CONTROL_COMWAIT_EN 0x04ULL
148#define CONTROL_INV_TIMEOUT 0x05ULL
149#define CONTROL_PASSPW_EN 0x08ULL
150#define CONTROL_RESPASSPW_EN 0x09ULL
151#define CONTROL_COHERENT_EN 0x0aULL
152#define CONTROL_ISOC_EN 0x0bULL
153#define CONTROL_CMDBUF_EN 0x0cULL
154#define CONTROL_PPFLOG_EN 0x0dULL
155#define CONTROL_PPFINT_EN 0x0eULL
156#define CONTROL_PPR_EN 0x0fULL
157#define CONTROL_GT_EN 0x10ULL
158#define CONTROL_GA_EN 0x11ULL
159#define CONTROL_GAM_EN 0x19ULL
160#define CONTROL_GALOG_EN 0x1CULL
161#define CONTROL_GAINT_EN 0x1DULL
162
163#define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
164#define CTRL_INV_TO_NONE 0
165#define CTRL_INV_TO_1MS 1
166#define CTRL_INV_TO_10MS 2
167#define CTRL_INV_TO_100MS 3
168#define CTRL_INV_TO_1S 4
169#define CTRL_INV_TO_10S 5
170#define CTRL_INV_TO_100S 6
171
172
173#define CMD_COMPL_WAIT 0x01
174#define CMD_INV_DEV_ENTRY 0x02
175#define CMD_INV_IOMMU_PAGES 0x03
176#define CMD_INV_IOTLB_PAGES 0x04
177#define CMD_INV_IRT 0x05
178#define CMD_COMPLETE_PPR 0x07
179#define CMD_INV_ALL 0x08
180
181#define CMD_COMPL_WAIT_STORE_MASK 0x01
182#define CMD_COMPL_WAIT_INT_MASK 0x02
183#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
184#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
185#define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
186
187#define PPR_STATUS_MASK 0xf
188#define PPR_STATUS_SHIFT 12
189
190#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
191
192
193#define DEV_ENTRY_VALID 0x00
194#define DEV_ENTRY_TRANSLATION 0x01
195#define DEV_ENTRY_IR 0x3d
196#define DEV_ENTRY_IW 0x3e
197#define DEV_ENTRY_NO_PAGE_FAULT 0x62
198#define DEV_ENTRY_EX 0x67
199#define DEV_ENTRY_SYSMGT1 0x68
200#define DEV_ENTRY_SYSMGT2 0x69
201#define DEV_ENTRY_IRQ_TBL_EN 0x80
202#define DEV_ENTRY_INIT_PASS 0xb8
203#define DEV_ENTRY_EINT_PASS 0xb9
204#define DEV_ENTRY_NMI_PASS 0xba
205#define DEV_ENTRY_LINT0_PASS 0xbe
206#define DEV_ENTRY_LINT1_PASS 0xbf
207#define DEV_ENTRY_MODE_MASK 0x07
208#define DEV_ENTRY_MODE_SHIFT 0x09
209
210#define MAX_DEV_TABLE_ENTRIES 0xffff
211
212
213#define CMD_BUFFER_SIZE 8192
214#define CMD_BUFFER_UNINITIALIZED 1
215#define CMD_BUFFER_ENTRIES 512
216#define MMIO_CMD_SIZE_SHIFT 56
217#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
218
219
220#define EVT_BUFFER_SIZE 8192
221#define EVT_LEN_MASK (0x9ULL << 56)
222
223
224#define PPR_LOG_ENTRIES 512
225#define PPR_LOG_SIZE_SHIFT 56
226#define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
227#define PPR_ENTRY_SIZE 16
228#define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
229
230#define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
231#define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
232#define PPR_DEVID(x) ((x) & 0xffffULL)
233#define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
234#define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
235#define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
236#define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
237
238#define PPR_REQ_FAULT 0x01
239
240
241#define GA_LOG_ENTRIES 512
242#define GA_LOG_SIZE_SHIFT 56
243#define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
244#define GA_ENTRY_SIZE 8
245#define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
246
247#define GA_TAG(x) (u32)(x & 0xffffffffULL)
248#define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
249#define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
250
251#define GA_GUEST_NR 0x1
252
253#define PAGE_MODE_NONE 0x00
254#define PAGE_MODE_1_LEVEL 0x01
255#define PAGE_MODE_2_LEVEL 0x02
256#define PAGE_MODE_3_LEVEL 0x03
257#define PAGE_MODE_4_LEVEL 0x04
258#define PAGE_MODE_5_LEVEL 0x05
259#define PAGE_MODE_6_LEVEL 0x06
260
261#define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
262#define PM_LEVEL_SIZE(x) (((x) < 6) ? \
263 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
264 (0xffffffffffffffffULL))
265#define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
266#define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
267#define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
268 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
269#define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
270
271#define PM_MAP_4k 0
272#define PM_ADDR_MASK 0x000ffffffffff000ULL
273#define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
274 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
275#define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
276
277
278
279
280
281#define PAGE_SIZE_LEVEL(pagesize) \
282 ((__ffs(pagesize) - 12) / 9)
283
284
285
286
287#define PAGE_SIZE_PTE_COUNT(pagesize) \
288 (1ULL << ((__ffs(pagesize) - 12) % 9))
289
290
291
292
293
294#define PAGE_SIZE_ALIGN(address, pagesize) \
295 ((address) & ~((pagesize) - 1))
296
297
298
299
300
301#define PAGE_SIZE_PTE(address, pagesize) \
302 (((address) | ((pagesize) - 1)) & \
303 (~(pagesize >> 1)) & PM_ADDR_MASK)
304
305
306
307
308#define PTE_PAGE_SIZE(pte) \
309 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
310
311
312
313
314#define PTE_LEVEL_PAGE_SIZE(level) \
315 (1ULL << (12 + (9 * (level))))
316
317#define IOMMU_PTE_P (1ULL << 0)
318#define IOMMU_PTE_TV (1ULL << 1)
319#define IOMMU_PTE_U (1ULL << 59)
320#define IOMMU_PTE_FC (1ULL << 60)
321#define IOMMU_PTE_IR (1ULL << 61)
322#define IOMMU_PTE_IW (1ULL << 62)
323
324#define DTE_FLAG_IOTLB (1ULL << 32)
325#define DTE_FLAG_GV (1ULL << 55)
326#define DTE_FLAG_MASK (0x3ffULL << 32)
327#define DTE_GLX_SHIFT (56)
328#define DTE_GLX_MASK (3)
329
330#define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
331#define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
332#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL)
333
334#define DTE_GCR3_INDEX_A 0
335#define DTE_GCR3_INDEX_B 1
336#define DTE_GCR3_INDEX_C 1
337
338#define DTE_GCR3_SHIFT_A 58
339#define DTE_GCR3_SHIFT_B 16
340#define DTE_GCR3_SHIFT_C 43
341
342#define GCR3_VALID 0x01ULL
343
344#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
345#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
346#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
347#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
348
349#define IOMMU_PROT_MASK 0x03
350#define IOMMU_PROT_IR 0x01
351#define IOMMU_PROT_IW 0x02
352
353
354#define IOMMU_CAP_IOTLB 24
355#define IOMMU_CAP_NPCACHE 26
356#define IOMMU_CAP_EFR 27
357
358
359#define IOMMU_FEAT_GASUP_SHIFT 6
360
361
362#define IOMMU_EFR_GASUP_SHIFT 7
363
364#define MAX_DOMAIN_ID 65536
365
366
367#define PD_DMA_OPS_MASK (1UL << 0)
368#define PD_DEFAULT_MASK (1UL << 1)
369
370#define PD_PASSTHROUGH_MASK (1UL << 2)
371
372#define PD_IOMMUV2_MASK (1UL << 3)
373
374extern bool amd_iommu_dump;
375#define DUMP_printk(format, arg...) \
376 do { \
377 if (amd_iommu_dump) \
378 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
379 } while(0);
380
381
382extern bool amd_iommu_np_cache;
383
384extern bool amd_iommu_iotlb_sup;
385
386#define MAX_IRQS_PER_TABLE 256
387#define IRQ_TABLE_ALIGNMENT 128
388
389struct irq_remap_table {
390 spinlock_t lock;
391 unsigned min_index;
392 u32 *table;
393};
394
395extern struct irq_remap_table **irq_lookup_table;
396
397
398extern bool amd_iommu_irq_remap;
399
400
401extern struct kmem_cache *amd_iommu_irq_cache;
402
403
404
405
406#define for_each_iommu(iommu) \
407 list_for_each_entry((iommu), &amd_iommu_list, list)
408#define for_each_iommu_safe(iommu, next) \
409 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
410
411#define APERTURE_RANGE_SHIFT 27
412#define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
413#define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
414#define APERTURE_MAX_RANGES 32
415#define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
416#define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
417
418
419
420
421
422
423struct amd_iommu_fault {
424 u64 address;
425 u32 pasid;
426 u16 device_id;
427 u16 tag;
428 u16 flags;
429
430};
431
432
433struct iommu_domain;
434struct irq_domain;
435struct amd_irte_ops;
436
437
438
439
440
441struct protection_domain {
442 struct list_head list;
443 struct list_head dev_list;
444 struct iommu_domain domain;
445
446 spinlock_t lock;
447 struct mutex api_lock;
448 u16 id;
449 int mode;
450 u64 *pt_root;
451 int glx;
452 u64 *gcr3_tbl;
453 unsigned long flags;
454 bool updated;
455 unsigned dev_cnt;
456 unsigned dev_iommu[MAX_IOMMUS];
457};
458
459
460
461
462
463struct amd_iommu {
464 struct list_head list;
465
466
467 int index;
468
469
470 spinlock_t lock;
471
472
473 struct pci_dev *dev;
474
475
476 struct pci_dev *root_pdev;
477
478
479 u64 mmio_phys;
480
481
482 u64 mmio_phys_end;
483
484
485 u8 __iomem *mmio_base;
486
487
488 u32 cap;
489
490
491 u8 acpi_flags;
492
493
494 u64 features;
495
496
497 bool is_iommu_v2;
498
499
500 u16 devid;
501
502
503
504
505
506
507 u16 cap_ptr;
508
509
510 u16 pci_seg;
511
512
513 u64 exclusion_start;
514
515 u64 exclusion_length;
516
517
518 u8 *cmd_buf;
519
520
521 u8 *evt_buf;
522
523
524 u8 *ppr_log;
525
526
527 u8 *ga_log;
528
529
530 u8 *ga_log_tail;
531
532
533 bool int_enabled;
534
535
536 bool need_sync;
537
538
539 struct iommu_device iommu;
540
541
542
543
544
545
546
547 u32 stored_addr_lo;
548 u32 stored_addr_hi;
549
550
551
552
553
554 u32 stored_l1[6][0x12];
555
556
557 u32 stored_l2[0x83];
558
559
560 u8 max_banks;
561 u8 max_counters;
562#ifdef CONFIG_IRQ_REMAP
563 struct irq_domain *ir_domain;
564 struct irq_domain *msi_domain;
565
566 struct amd_irte_ops *irte_ops;
567#endif
568
569 volatile u64 __aligned(8) cmd_sem;
570};
571
572static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
573{
574 return container_of(dev, struct amd_iommu, iommu.dev);
575}
576
577#define ACPIHID_UID_LEN 256
578#define ACPIHID_HID_LEN 9
579
580struct acpihid_map_entry {
581 struct list_head list;
582 u8 uid[ACPIHID_UID_LEN];
583 u8 hid[ACPIHID_HID_LEN];
584 u16 devid;
585 u16 root_devid;
586 bool cmd_line;
587 struct iommu_group *group;
588};
589
590struct devid_map {
591 struct list_head list;
592 u8 id;
593 u16 devid;
594 bool cmd_line;
595};
596
597
598extern struct list_head ioapic_map;
599extern struct list_head hpet_map;
600extern struct list_head acpihid_map;
601
602
603
604
605
606extern struct list_head amd_iommu_list;
607
608
609
610
611
612extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
613
614
615
616
617extern spinlock_t amd_iommu_pd_lock;
618extern struct list_head amd_iommu_pd_list;
619
620
621
622
623struct dev_table_entry {
624 u64 data[4];
625};
626
627
628
629
630struct unity_map_entry {
631 struct list_head list;
632
633
634 u16 devid_start;
635
636 u16 devid_end;
637
638
639 u64 address_start;
640
641 u64 address_end;
642
643
644 int prot;
645};
646
647
648
649
650
651extern struct list_head amd_iommu_unity_map;
652
653
654
655
656
657
658
659
660
661extern struct dev_table_entry *amd_iommu_dev_table;
662
663
664
665
666
667extern u16 *amd_iommu_alias_table;
668
669
670
671
672extern struct amd_iommu **amd_iommu_rlookup_table;
673
674
675extern unsigned amd_iommu_aperture_order;
676
677
678extern u16 amd_iommu_last_bdf;
679
680
681extern unsigned long *amd_iommu_pd_alloc_bitmap;
682
683
684
685
686
687extern bool amd_iommu_unmap_flush;
688
689
690extern u32 amd_iommu_max_pasid;
691
692extern bool amd_iommu_v2_present;
693
694extern bool amd_iommu_force_isolation;
695
696
697extern int amd_iommu_max_glx_val;
698
699
700
701
702
703extern void iommu_flush_all_caches(struct amd_iommu *iommu);
704
705static inline int get_ioapic_devid(int id)
706{
707 struct devid_map *entry;
708
709 list_for_each_entry(entry, &ioapic_map, list) {
710 if (entry->id == id)
711 return entry->devid;
712 }
713
714 return -EINVAL;
715}
716
717static inline int get_hpet_devid(int id)
718{
719 struct devid_map *entry;
720
721 list_for_each_entry(entry, &hpet_map, list) {
722 if (entry->id == id)
723 return entry->devid;
724 }
725
726 return -EINVAL;
727}
728
729enum amd_iommu_intr_mode_type {
730 AMD_IOMMU_GUEST_IR_LEGACY,
731
732
733
734
735
736 AMD_IOMMU_GUEST_IR_LEGACY_GA,
737 AMD_IOMMU_GUEST_IR_VAPIC,
738};
739
740#define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
741 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
742
743#define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
744
745union irte {
746 u32 val;
747 struct {
748 u32 valid : 1,
749 no_fault : 1,
750 int_type : 3,
751 rq_eoi : 1,
752 dm : 1,
753 rsvd_1 : 1,
754 destination : 8,
755 vector : 8,
756 rsvd_2 : 8;
757 } fields;
758};
759
760union irte_ga_lo {
761 u64 val;
762
763
764 struct {
765 u64 valid : 1,
766 no_fault : 1,
767
768 int_type : 3,
769 rq_eoi : 1,
770 dm : 1,
771
772 guest_mode : 1,
773 destination : 8,
774 rsvd : 48;
775 } fields_remap;
776
777
778 struct {
779 u64 valid : 1,
780 no_fault : 1,
781
782 ga_log_intr : 1,
783 rsvd1 : 3,
784 is_run : 1,
785
786 guest_mode : 1,
787 destination : 8,
788 rsvd2 : 16,
789 ga_tag : 32;
790 } fields_vapic;
791};
792
793union irte_ga_hi {
794 u64 val;
795 struct {
796 u64 vector : 8,
797 rsvd_1 : 4,
798 ga_root_ptr : 40,
799 rsvd_2 : 12;
800 } fields;
801};
802
803struct irte_ga {
804 union irte_ga_lo lo;
805 union irte_ga_hi hi;
806};
807
808struct irq_2_irte {
809 u16 devid;
810 u16 index;
811};
812
813struct amd_ir_data {
814 u32 cached_ga_tag;
815 struct irq_2_irte irq_2_irte;
816 struct msi_msg msi_entry;
817 void *entry;
818 void *ref;
819};
820
821struct amd_irte_ops {
822 void (*prepare)(void *, u32, u32, u8, u32, int);
823 void (*activate)(void *, u16, u16);
824 void (*deactivate)(void *, u16, u16);
825 void (*set_affinity)(void *, u16, u16, u8, u32);
826 void *(*get)(struct irq_remap_table *, int);
827 void (*set_allocated)(struct irq_remap_table *, int);
828 bool (*is_allocated)(struct irq_remap_table *, int);
829 void (*clear_allocated)(struct irq_remap_table *, int);
830};
831
832#ifdef CONFIG_IRQ_REMAP
833extern struct amd_irte_ops irte_32_ops;
834extern struct amd_irte_ops irte_128_ops;
835#endif
836
837#endif
838