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117#include <linux/module.h>
118#include <linux/interrupt.h>
119#include <linux/kmod.h>
120#include <linux/delay.h>
121#include <linux/completion.h>
122#include <linux/mutex.h>
123
124#include "xgbe.h"
125#include "xgbe-common.h"
126
127#define XGBE_ABORT_COUNT 500
128#define XGBE_DISABLE_COUNT 1000
129
130#define XGBE_STD_SPEED 1
131
132#define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
133#define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
134#define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
135#define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
136#define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \
137 XGBE_INTR_TX_EMPTY | \
138 XGBE_INTR_TX_ABRT | \
139 XGBE_INTR_STOP_DET)
140
141#define XGBE_I2C_READ BIT(8)
142#define XGBE_I2C_STOP BIT(9)
143
144static int xgbe_i2c_abort(struct xgbe_prv_data *pdata)
145{
146 unsigned int wait = XGBE_ABORT_COUNT;
147
148
149 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);
150
151
152 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);
153
154 while (wait--) {
155 if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
156 return 0;
157
158 usleep_range(500, 600);
159 }
160
161 return -EBUSY;
162}
163
164static int xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable)
165{
166 unsigned int wait = XGBE_DISABLE_COUNT;
167 unsigned int mode = enable ? 1 : 0;
168
169 while (wait--) {
170 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
171 if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
172 return 0;
173
174 usleep_range(100, 110);
175 }
176
177 return -EBUSY;
178}
179
180static int xgbe_i2c_disable(struct xgbe_prv_data *pdata)
181{
182 unsigned int ret;
183
184 ret = xgbe_i2c_set_enable(pdata, false);
185 if (ret) {
186
187 ret = xgbe_i2c_abort(pdata);
188 if (ret)
189 return ret;
190
191
192 ret = xgbe_i2c_set_enable(pdata, false);
193 }
194
195 return ret;
196}
197
198static int xgbe_i2c_enable(struct xgbe_prv_data *pdata)
199{
200 return xgbe_i2c_set_enable(pdata, true);
201}
202
203static void xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata)
204{
205 XI2C_IOREAD(pdata, IC_CLR_INTR);
206}
207
208static void xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata)
209{
210 XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
211}
212
213static void xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata)
214{
215 XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK);
216}
217
218static void xgbe_i2c_write(struct xgbe_prv_data *pdata)
219{
220 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
221 unsigned int tx_slots;
222 unsigned int cmd;
223
224
225 tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
226 while (tx_slots && state->tx_len) {
227 if (state->op->cmd == XGBE_I2C_CMD_READ)
228 cmd = XGBE_I2C_READ;
229 else
230 cmd = *state->tx_buf++;
231
232 if (state->tx_len == 1)
233 XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);
234
235 XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);
236
237 tx_slots--;
238 state->tx_len--;
239 }
240
241
242 if (!state->tx_len)
243 XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
244}
245
246static void xgbe_i2c_read(struct xgbe_prv_data *pdata)
247{
248 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
249 unsigned int rx_slots;
250
251
252 if (state->op->cmd != XGBE_I2C_CMD_READ)
253 return;
254
255 rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
256 while (rx_slots && state->rx_len) {
257 *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
258 state->rx_len--;
259 rx_slots--;
260 }
261}
262
263static void xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata,
264 unsigned int isr)
265{
266 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
267
268 if (isr & XGBE_INTR_TX_ABRT) {
269 state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
270 XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
271 }
272
273 if (isr & XGBE_INTR_STOP_DET)
274 XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
275}
276
277static irqreturn_t xgbe_i2c_isr(int irq, void *data)
278{
279 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
280 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
281 unsigned int isr;
282
283 isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
284 netif_dbg(pdata, intr, pdata->netdev,
285 "I2C interrupt received: status=%#010x\n", isr);
286
287 xgbe_i2c_clear_isr_interrupts(pdata, isr);
288
289 if (isr & XGBE_INTR_TX_ABRT) {
290 netif_dbg(pdata, link, pdata->netdev,
291 "I2C TX_ABRT received (%#010x) for target %#04x\n",
292 state->tx_abort_source, state->op->target);
293
294 xgbe_i2c_disable_interrupts(pdata);
295
296 state->ret = -EIO;
297 goto out;
298 }
299
300
301 xgbe_i2c_read(pdata);
302
303
304 xgbe_i2c_write(pdata);
305
306out:
307
308 if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
309 complete(&pdata->i2c_complete);
310
311 return IRQ_HANDLED;
312}
313
314static void xgbe_i2c_set_mode(struct xgbe_prv_data *pdata)
315{
316 unsigned int reg;
317
318 reg = XI2C_IOREAD(pdata, IC_CON);
319 XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
320 XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
321 XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
322 XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);
323 XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
324 XI2C_IOWRITE(pdata, IC_CON, reg);
325}
326
327static void xgbe_i2c_get_features(struct xgbe_prv_data *pdata)
328{
329 struct xgbe_i2c *i2c = &pdata->i2c;
330 unsigned int reg;
331
332 reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
333 i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
334 MAX_SPEED_MODE);
335 i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
336 RX_BUFFER_DEPTH);
337 i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
338 TX_BUFFER_DEPTH);
339
340 if (netif_msg_probe(pdata))
341 dev_dbg(pdata->dev, "I2C features: %s=%u, %s=%u, %s=%u\n",
342 "MAX_SPEED_MODE", i2c->max_speed_mode,
343 "RX_BUFFER_DEPTH", i2c->rx_fifo_size,
344 "TX_BUFFER_DEPTH", i2c->tx_fifo_size);
345}
346
347static void xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr)
348{
349 XI2C_IOWRITE(pdata, IC_TAR, addr);
350}
351
352static irqreturn_t xgbe_i2c_combined_isr(int irq, struct xgbe_prv_data *pdata)
353{
354 if (!XI2C_IOREAD(pdata, IC_RAW_INTR_STAT))
355 return IRQ_HANDLED;
356
357 return xgbe_i2c_isr(irq, pdata);
358}
359
360static int xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op)
361{
362 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
363 int ret;
364
365 mutex_lock(&pdata->i2c_mutex);
366
367 reinit_completion(&pdata->i2c_complete);
368
369 ret = xgbe_i2c_disable(pdata);
370 if (ret) {
371 netdev_err(pdata->netdev, "failed to disable i2c master\n");
372 goto unlock;
373 }
374
375 xgbe_i2c_set_target(pdata, op->target);
376
377 memset(state, 0, sizeof(*state));
378 state->op = op;
379 state->tx_len = op->len;
380 state->tx_buf = op->buf;
381 state->rx_len = op->len;
382 state->rx_buf = op->buf;
383
384 xgbe_i2c_clear_all_interrupts(pdata);
385 ret = xgbe_i2c_enable(pdata);
386 if (ret) {
387 netdev_err(pdata->netdev, "failed to enable i2c master\n");
388 goto unlock;
389 }
390
391
392
393
394 xgbe_i2c_enable_interrupts(pdata);
395
396 if (!wait_for_completion_timeout(&pdata->i2c_complete, HZ)) {
397 netdev_err(pdata->netdev, "i2c operation timed out\n");
398 ret = -ETIMEDOUT;
399 goto disable;
400 }
401
402 ret = state->ret;
403 if (ret) {
404 if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
405 ret = -ENOTCONN;
406 else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
407 ret = -EAGAIN;
408 }
409
410disable:
411 xgbe_i2c_disable_interrupts(pdata);
412 xgbe_i2c_disable(pdata);
413
414unlock:
415 mutex_unlock(&pdata->i2c_mutex);
416
417 return ret;
418}
419
420static void xgbe_i2c_stop(struct xgbe_prv_data *pdata)
421{
422 if (!pdata->i2c.started)
423 return;
424
425 netif_dbg(pdata, link, pdata->netdev, "stopping I2C\n");
426
427 pdata->i2c.started = 0;
428
429 xgbe_i2c_disable_interrupts(pdata);
430 xgbe_i2c_disable(pdata);
431 xgbe_i2c_clear_all_interrupts(pdata);
432
433 if (pdata->dev_irq != pdata->i2c_irq)
434 devm_free_irq(pdata->dev, pdata->i2c_irq, pdata);
435}
436
437static int xgbe_i2c_start(struct xgbe_prv_data *pdata)
438{
439 int ret;
440
441 if (pdata->i2c.started)
442 return 0;
443
444 netif_dbg(pdata, link, pdata->netdev, "starting I2C\n");
445
446
447 if (pdata->dev_irq != pdata->i2c_irq) {
448 ret = devm_request_irq(pdata->dev, pdata->i2c_irq,
449 xgbe_i2c_isr, 0, pdata->i2c_name,
450 pdata);
451 if (ret) {
452 netdev_err(pdata->netdev, "i2c irq request failed\n");
453 return ret;
454 }
455 }
456
457 pdata->i2c.started = 1;
458
459 return 0;
460}
461
462static int xgbe_i2c_init(struct xgbe_prv_data *pdata)
463{
464 int ret;
465
466 xgbe_i2c_disable_interrupts(pdata);
467
468 ret = xgbe_i2c_disable(pdata);
469 if (ret) {
470 dev_err(pdata->dev, "failed to disable i2c master\n");
471 return ret;
472 }
473
474 xgbe_i2c_get_features(pdata);
475
476 xgbe_i2c_set_mode(pdata);
477
478 xgbe_i2c_clear_all_interrupts(pdata);
479
480 return 0;
481}
482
483void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if)
484{
485 i2c_if->i2c_init = xgbe_i2c_init;
486
487 i2c_if->i2c_start = xgbe_i2c_start;
488 i2c_if->i2c_stop = xgbe_i2c_stop;
489
490 i2c_if->i2c_xfer = xgbe_i2c_xfer;
491
492 i2c_if->i2c_isr = xgbe_i2c_combined_isr;
493}
494