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23#ifndef __LIQUIDIO_COMMON_H__
24#define __LIQUIDIO_COMMON_H__
25
26#include "octeon_config.h"
27
28#define LIQUIDIO_PACKAGE ""
29#define LIQUIDIO_BASE_MAJOR_VERSION 1
30#define LIQUIDIO_BASE_MINOR_VERSION 5
31#define LIQUIDIO_BASE_MICRO_VERSION 1
32#define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
33 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
34#define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
35#define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \
36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
39
40struct lio_version {
41 u16 major;
42 u16 minor;
43 u16 micro;
44 u16 reserved;
45};
46
47#define CONTROL_IQ 0
48
49enum octeon_tag_type {
50 ORDERED_TAG = 0,
51 ATOMIC_TAG = 1,
52 NULL_TAG = 2,
53 NULL_NULL_TAG = 3
54};
55
56
57#define LIO_CONTROL (0x11111110)
58#define LIO_DATA(i) (0x11111111 + (i))
59
60
61
62
63
64#define OPCODE_CORE 0
65#define OPCODE_NIC 1
66
67
68
69#define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
70
71
72
73
74
75
76#define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
77#define OPCODE_NIC_NW_DATA 0x02
78#define OPCODE_NIC_CMD 0x03
79#define OPCODE_NIC_INFO 0x04
80#define OPCODE_NIC_PORT_STATS 0x05
81#define OPCODE_NIC_MDIO45 0x06
82#define OPCODE_NIC_TIMESTAMP 0x07
83#define OPCODE_NIC_INTRMOD_CFG 0x08
84#define OPCODE_NIC_IF_CFG 0x09
85#define OPCODE_NIC_VF_DRV_NOTICE 0x0A
86#define OPCODE_NIC_INTRMOD_PARAMS 0x0B
87#define VF_DRV_LOADED 1
88#define VF_DRV_REMOVED -1
89#define VF_DRV_MACADDR_CHANGED 2
90
91#define CORE_DRV_TEST_SCATTER_OP 0xFFF5
92
93
94#define CVM_DRV_APP_START 0x0
95#define CVM_DRV_NO_APP 0
96#define CVM_DRV_APP_COUNT 0x2
97#define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
98#define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
99#define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
100#define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
101
102#define BYTES_PER_DHLEN_UNIT 8
103#define MAX_REG_CNT 2000000U
104#define INTRNAMSIZ 32
105#define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ)
106#define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2)
107#define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2)
108
109
110static inline u32 incr_index(u32 index, u32 count, u32 max)
111{
112 if ((index + count) >= max)
113 index = index + count - max;
114 else
115 index += count;
116
117 return index;
118}
119
120#define OCT_BOARD_NAME 32
121#define OCT_SERIAL_LEN 64
122
123
124
125
126struct octeon_core_setup {
127 u64 corefreq;
128
129 char boardname[OCT_BOARD_NAME];
130
131 char board_serial_number[OCT_SERIAL_LEN];
132
133 u64 board_rev_major;
134
135 u64 board_rev_minor;
136
137};
138
139
140
141
142
143
144struct octeon_sg_entry {
145
146 union {
147 u16 size[4];
148 u64 size64;
149 } u;
150
151
152 u64 ptr[4];
153
154};
155
156#define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
157
158
159
160
161
162
163static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
164 u16 size,
165 u32 pos)
166{
167#ifdef __BIG_ENDIAN_BITFIELD
168 sg_entry->u.size[pos] = size;
169#else
170 sg_entry->u.size[3 - pos] = size;
171#endif
172}
173
174
175
176#define OCTNET_FRM_PTP_HEADER_SIZE 8
177
178#define OCTNET_FRM_HEADER_SIZE 22
179
180#define OCTNET_MIN_FRM_SIZE 64
181
182#define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
183
184#define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE)
185
186
187#define OCTNET_CMD_Q 0
188
189
190#define OCTNET_CMD_RESET_PF 0x0
191#define OCTNET_CMD_CHANGE_MTU 0x1
192#define OCTNET_CMD_CHANGE_MACADDR 0x2
193#define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
194#define OCTNET_CMD_RX_CTL 0x4
195
196#define OCTNET_CMD_SET_MULTI_LIST 0x5
197#define OCTNET_CMD_CLEAR_STATS 0x6
198
199
200#define OCTNET_CMD_SET_SETTINGS 0x7
201#define OCTNET_CMD_SET_FLOW_CTL 0x8
202
203#define OCTNET_CMD_MDIO_READ_WRITE 0x9
204#define OCTNET_CMD_GPIO_ACCESS 0xA
205#define OCTNET_CMD_LRO_ENABLE 0xB
206#define OCTNET_CMD_LRO_DISABLE 0xC
207#define OCTNET_CMD_SET_RSS 0xD
208#define OCTNET_CMD_WRITE_SA 0xE
209#define OCTNET_CMD_DELETE_SA 0xF
210#define OCTNET_CMD_UPDATE_SA 0x12
211
212#define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
213#define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
214#define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
215#define OCTNET_CMD_VERBOSE_ENABLE 0x14
216#define OCTNET_CMD_VERBOSE_DISABLE 0x15
217
218#define OCTNET_CMD_ENABLE_VLAN_FILTER 0x16
219#define OCTNET_CMD_ADD_VLAN_FILTER 0x17
220#define OCTNET_CMD_DEL_VLAN_FILTER 0x18
221#define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
222
223#define OCTNET_CMD_ID_ACTIVE 0x1a
224
225#define OCTNET_CMD_SET_UC_LIST 0x1b
226#define OCTNET_CMD_SET_VF_LINKSTATE 0x1c
227#define OCTNET_CMD_VXLAN_PORT_ADD 0x0
228#define OCTNET_CMD_VXLAN_PORT_DEL 0x1
229#define OCTNET_CMD_RXCSUM_ENABLE 0x0
230#define OCTNET_CMD_RXCSUM_DISABLE 0x1
231#define OCTNET_CMD_TXCSUM_ENABLE 0x0
232#define OCTNET_CMD_TXCSUM_DISABLE 0x1
233
234
235
236#define CNNIC_L4SUM_VERIFIED 0x1
237#define CNNIC_IPSUM_VERIFIED 0x2
238#define CNNIC_TUN_CSUM_VERIFIED 0x4
239#define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
240
241
242#define OCTNIC_LROIPV4 0x1
243#define OCTNIC_LROIPV6 0x2
244
245
246enum octnet_ifflags {
247 OCTNET_IFFLAG_PROMISC = 0x01,
248 OCTNET_IFFLAG_ALLMULTI = 0x02,
249 OCTNET_IFFLAG_MULTICAST = 0x04,
250 OCTNET_IFFLAG_BROADCAST = 0x08,
251 OCTNET_IFFLAG_UNICAST = 0x10
252};
253
254
255
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264
265
266
267
268
269
270
271union octnet_cmd {
272 u64 u64;
273
274 struct {
275#ifdef __BIG_ENDIAN_BITFIELD
276 u64 cmd:5;
277
278 u64 more:6;
279
280 u64 reserved:29;
281
282 u64 param1:16;
283
284 u64 param2:8;
285
286#else
287
288 u64 param2:8;
289
290 u64 param1:16;
291
292 u64 reserved:29;
293
294 u64 more:6;
295
296 u64 cmd:5;
297
298#endif
299 } s;
300
301};
302
303#define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
304
305
306#define LIO_SOFTCMDRESP_IH2 40
307#define LIO_SOFTCMDRESP_IH3 (40 + 8)
308
309#define LIO_PCICMD_O2 24
310#define LIO_PCICMD_O3 (24 + 8)
311
312
313struct octeon_instr_ih3 {
314#ifdef __BIG_ENDIAN_BITFIELD
315
316
317 u64 reserved3:1;
318
319
320 u64 gather:1;
321
322
323 u64 dlengsz:14;
324
325
326 u64 fsz:6;
327
328
329 u64 reserved2:4;
330
331
332 u64 pkind:6;
333
334
335 u64 reserved1:32;
336
337#else
338
339 u64 reserved1:32;
340
341
342 u64 pkind:6;
343
344
345 u64 reserved2:4;
346
347
348 u64 fsz:6;
349
350
351 u64 dlengsz:14;
352
353
354 u64 gather:1;
355
356
357 u64 reserved3:1;
358
359#endif
360};
361
362
363
364struct octeon_instr_pki_ih3 {
365#ifdef __BIG_ENDIAN_BITFIELD
366
367
368 u64 w:1;
369
370
371 u64 raw:1;
372
373
374 u64 utag:1;
375
376
377 u64 uqpg:1;
378
379
380 u64 reserved2:1;
381
382
383 u64 pm:3;
384
385
386 u64 sl:8;
387
388
389 u64 utt:1;
390
391
392 u64 tagtype:2;
393
394
395 u64 reserved1:2;
396
397
398 u64 qpg:11;
399
400
401 u64 tag:32;
402
403#else
404
405
406 u64 tag:32;
407
408
409 u64 qpg:11;
410
411
412 u64 reserved1:2;
413
414
415 u64 tagtype:2;
416
417
418 u64 utt:1;
419
420
421 u64 sl:8;
422
423
424 u64 pm:3;
425
426
427 u64 reserved2:1;
428
429
430 u64 uqpg:1;
431
432
433 u64 utag:1;
434
435
436 u64 raw:1;
437
438
439 u64 w:1;
440#endif
441
442};
443
444
445struct octeon_instr_ih2 {
446#ifdef __BIG_ENDIAN_BITFIELD
447
448 u64 raw:1;
449
450
451 u64 gather:1;
452
453
454 u64 dlengsz:14;
455
456
457 u64 fsz:6;
458
459
460 u64 qos:3;
461
462
463 u64 grp:4;
464
465
466 u64 rs:1;
467
468
469 u64 tagtype:2;
470
471
472 u64 tag:32;
473#else
474
475 u64 tag:32;
476
477
478 u64 tagtype:2;
479
480
481 u64 rs:1;
482
483
484 u64 grp:4;
485
486
487 u64 qos:3;
488
489
490 u64 fsz:6;
491
492
493 u64 dlengsz:14;
494
495
496 u64 gather:1;
497
498
499 u64 raw:1;
500#endif
501};
502
503
504struct octeon_instr_irh {
505#ifdef __BIG_ENDIAN_BITFIELD
506 u64 opcode:4;
507 u64 rflag:1;
508 u64 subcode:7;
509 u64 vlan:12;
510 u64 priority:3;
511 u64 reserved:5;
512 u64 ossp:32;
513#else
514 u64 ossp:32;
515 u64 reserved:5;
516 u64 priority:3;
517 u64 vlan:12;
518 u64 subcode:7;
519 u64 rflag:1;
520 u64 opcode:4;
521#endif
522};
523
524
525struct octeon_instr_rdp {
526#ifdef __BIG_ENDIAN_BITFIELD
527 u64 reserved:49;
528 u64 pcie_port:3;
529 u64 rlen:12;
530#else
531 u64 rlen:12;
532 u64 pcie_port:3;
533 u64 reserved:49;
534#endif
535};
536
537
538union octeon_rh {
539#ifdef __BIG_ENDIAN_BITFIELD
540 u64 u64;
541 struct {
542 u64 opcode:4;
543 u64 subcode:8;
544 u64 len:3;
545 u64 reserved:17;
546 u64 ossp:32;
547 } r;
548 struct {
549 u64 opcode:4;
550 u64 subcode:8;
551 u64 len:3;
552 u64 extra:28;
553 u64 vlan:12;
554 u64 priority:3;
555 u64 csum_verified:3;
556 u64 has_hwtstamp:1;
557 u64 encap_on:1;
558 u64 has_hash:1;
559 } r_dh;
560 struct {
561 u64 opcode:4;
562 u64 subcode:8;
563 u64 len:3;
564 u64 reserved:11;
565 u64 num_gmx_ports:8;
566 u64 max_nic_ports:10;
567 u64 app_cap_flags:4;
568 u64 app_mode:8;
569 u64 pkind:8;
570 } r_core_drv_init;
571 struct {
572 u64 opcode:4;
573 u64 subcode:8;
574 u64 len:3;
575 u64 reserved:8;
576 u64 extra:25;
577 u64 gmxport:16;
578 } r_nic_info;
579#else
580 u64 u64;
581 struct {
582 u64 ossp:32;
583 u64 reserved:17;
584 u64 len:3;
585 u64 subcode:8;
586 u64 opcode:4;
587 } r;
588 struct {
589 u64 has_hash:1;
590 u64 encap_on:1;
591 u64 has_hwtstamp:1;
592 u64 csum_verified:3;
593 u64 priority:3;
594 u64 vlan:12;
595 u64 extra:28;
596 u64 len:3;
597 u64 subcode:8;
598 u64 opcode:4;
599 } r_dh;
600 struct {
601 u64 pkind:8;
602 u64 app_mode:8;
603 u64 app_cap_flags:4;
604 u64 max_nic_ports:10;
605 u64 num_gmx_ports:8;
606 u64 reserved:11;
607 u64 len:3;
608 u64 subcode:8;
609 u64 opcode:4;
610 } r_core_drv_init;
611 struct {
612 u64 gmxport:16;
613 u64 extra:25;
614 u64 reserved:8;
615 u64 len:3;
616 u64 subcode:8;
617 u64 opcode:4;
618 } r_nic_info;
619#endif
620};
621
622#define OCT_RH_SIZE (sizeof(union octeon_rh))
623
624union octnic_packet_params {
625 u32 u32;
626 struct {
627#ifdef __BIG_ENDIAN_BITFIELD
628 u32 reserved:24;
629 u32 ip_csum:1;
630
631 u32 transport_csum:1;
632
633 u32 tnl_csum:1;
634 u32 tsflag:1;
635 u32 ipsec_ops:4;
636#else
637 u32 ipsec_ops:4;
638 u32 tsflag:1;
639 u32 tnl_csum:1;
640 u32 transport_csum:1;
641 u32 ip_csum:1;
642 u32 reserved:24;
643#endif
644 } s;
645};
646
647
648union oct_link_status {
649 u64 u64;
650
651 struct {
652#ifdef __BIG_ENDIAN_BITFIELD
653 u64 duplex:8;
654 u64 mtu:16;
655 u64 speed:16;
656 u64 link_up:1;
657 u64 autoneg:1;
658 u64 if_mode:5;
659 u64 pause:1;
660 u64 flashing:1;
661 u64 reserved:15;
662#else
663 u64 reserved:15;
664 u64 flashing:1;
665 u64 pause:1;
666 u64 if_mode:5;
667 u64 autoneg:1;
668 u64 link_up:1;
669 u64 speed:16;
670 u64 mtu:16;
671 u64 duplex:8;
672#endif
673 } s;
674};
675
676
677
678union oct_txpciq {
679 u64 u64;
680
681 struct {
682#ifdef __BIG_ENDIAN_BITFIELD
683 u64 q_no:8;
684 u64 port:8;
685 u64 pkind:6;
686 u64 use_qpg:1;
687 u64 qpg:11;
688 u64 reserved:30;
689#else
690 u64 reserved:30;
691 u64 qpg:11;
692 u64 use_qpg:1;
693 u64 pkind:6;
694 u64 port:8;
695 u64 q_no:8;
696#endif
697 } s;
698};
699
700
701
702union oct_rxpciq {
703 u64 u64;
704
705 struct {
706#ifdef __BIG_ENDIAN_BITFIELD
707 u64 q_no:8;
708 u64 reserved:56;
709#else
710 u64 reserved:56;
711 u64 q_no:8;
712#endif
713 } s;
714};
715
716
717struct oct_link_info {
718 union oct_link_status link;
719 u64 hw_addr;
720
721#ifdef __BIG_ENDIAN_BITFIELD
722 u64 gmxport:16;
723 u64 macaddr_is_admin_asgnd:1;
724 u64 rsvd:31;
725 u64 num_txpciq:8;
726 u64 num_rxpciq:8;
727#else
728 u64 num_rxpciq:8;
729 u64 num_txpciq:8;
730 u64 rsvd:31;
731 u64 macaddr_is_admin_asgnd:1;
732 u64 gmxport:16;
733#endif
734
735 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
736 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
737};
738
739#define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
740
741struct liquidio_if_cfg_info {
742 u64 iqmask;
743 u64 oqmask;
744 struct oct_link_info linfo;
745 char liquidio_firmware_version[32];
746};
747
748
749struct nic_rx_stats {
750
751 u64 total_rcvd;
752 u64 bytes_rcvd;
753 u64 total_bcst;
754 u64 total_mcst;
755 u64 runts;
756 u64 ctl_rcvd;
757 u64 fifo_err;
758 u64 dmac_drop;
759 u64 fcs_err;
760 u64 jabber_err;
761 u64 l2_err;
762 u64 frame_err;
763
764
765 u64 fw_total_rcvd;
766 u64 fw_total_fwd;
767 u64 fw_err_pko;
768 u64 fw_err_link;
769 u64 fw_err_drop;
770 u64 fw_rx_vxlan;
771 u64 fw_rx_vxlan_err;
772
773
774 u64 fw_lro_pkts;
775 u64 fw_lro_octs;
776 u64 fw_total_lro;
777 u64 fw_lro_aborts;
778 u64 fw_lro_aborts_port;
779 u64 fw_lro_aborts_seq;
780 u64 fw_lro_aborts_tsval;
781 u64 fw_lro_aborts_timer;
782
783 u64 fwd_rate;
784};
785
786
787struct nic_tx_stats {
788
789 u64 total_pkts_sent;
790 u64 total_bytes_sent;
791 u64 mcast_pkts_sent;
792 u64 bcast_pkts_sent;
793 u64 ctl_sent;
794 u64 one_collision_sent;
795 u64 multi_collision_sent;
796 u64 max_collision_fail;
797 u64 max_deferral_fail;
798 u64 fifo_err;
799 u64 runts;
800 u64 total_collisions;
801
802
803 u64 fw_total_sent;
804 u64 fw_total_fwd;
805 u64 fw_total_fwd_bytes;
806 u64 fw_err_pko;
807 u64 fw_err_link;
808 u64 fw_err_drop;
809 u64 fw_err_tso;
810 u64 fw_tso;
811 u64 fw_tso_fwd;
812 u64 fw_tx_vxlan;
813};
814
815struct oct_link_stats {
816 struct nic_rx_stats fromwire;
817 struct nic_tx_stats fromhost;
818
819};
820
821static inline int opcode_slow_path(union octeon_rh *rh)
822{
823 u16 subcode1, subcode2;
824
825 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode);
826 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA);
827
828 return (subcode2 != subcode1);
829}
830
831#define LIO68XX_LED_CTRL_ADDR 0x3501
832#define LIO68XX_LED_CTRL_CFGON 0x1f
833#define LIO68XX_LED_CTRL_CFGOFF 0x100
834#define LIO68XX_LED_BEACON_ADDR 0x3508
835#define LIO68XX_LED_BEACON_CFGON 0x47fd
836#define LIO68XX_LED_BEACON_CFGOFF 0x11fc
837#define VITESSE_PHY_GPIO_DRIVEON 0x1
838#define VITESSE_PHY_GPIO_CFG 0x8
839#define VITESSE_PHY_GPIO_DRIVEOFF 0x4
840#define VITESSE_PHY_GPIO_HIGH 0x2
841#define VITESSE_PHY_GPIO_LOW 0x3
842#define LED_IDENTIFICATION_ON 0x1
843#define LED_IDENTIFICATION_OFF 0x0
844
845struct oct_mdio_cmd {
846 u64 op;
847 u64 mdio_addr;
848 u64 value1;
849 u64 value2;
850 u64 value3;
851};
852
853#define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
854
855struct oct_intrmod_cfg {
856 u64 rx_enable;
857 u64 tx_enable;
858 u64 check_intrvl;
859 u64 maxpkt_ratethr;
860 u64 minpkt_ratethr;
861 u64 rx_maxcnt_trigger;
862 u64 rx_mincnt_trigger;
863 u64 rx_maxtmr_trigger;
864 u64 rx_mintmr_trigger;
865 u64 tx_mincnt_trigger;
866 u64 tx_maxcnt_trigger;
867 u64 rx_frames;
868 u64 tx_frames;
869 u64 rx_usecs;
870};
871
872#define BASE_QUEUE_NOT_REQUESTED 65535
873
874union oct_nic_if_cfg {
875 u64 u64;
876 struct {
877#ifdef __BIG_ENDIAN_BITFIELD
878 u64 base_queue:16;
879 u64 num_iqueues:16;
880 u64 num_oqueues:16;
881 u64 gmx_port_id:8;
882 u64 vf_id:8;
883#else
884 u64 vf_id:8;
885 u64 gmx_port_id:8;
886 u64 num_oqueues:16;
887 u64 num_iqueues:16;
888 u64 base_queue:16;
889#endif
890 } s;
891};
892
893#endif
894