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27#ifndef _I40E_TYPE_H_
28#define _I40E_TYPE_H_
29
30#include "i40e_status.h"
31#include "i40e_osdep.h"
32#include "i40e_register.h"
33#include "i40e_adminq.h"
34#include "i40e_hmc.h"
35#include "i40e_lan_hmc.h"
36#include "i40e_devids.h"
37
38
39#define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
40
41#define I40E_MAX_VSI_QP 16
42#define I40E_MAX_VF_VSI 3
43#define I40E_MAX_CHAINED_RX_BUFFERS 5
44#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
45
46
47#define I40E_MAX_NVM_TIMEOUT 18000
48
49
50#define I40E_MS_TO_GTIME(time) ((time) * 1000)
51
52
53struct i40e_hw;
54typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
55
56
57
58#define I40E_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
61
62
63#define I40E_QTX_CTL_VF_QUEUE 0x0
64#define I40E_QTX_CTL_VM_QUEUE 0x1
65#define I40E_QTX_CTL_PF_QUEUE 0x2
66
67
68enum i40e_debug_mask {
69 I40E_DEBUG_INIT = 0x00000001,
70 I40E_DEBUG_RELEASE = 0x00000002,
71
72 I40E_DEBUG_LINK = 0x00000010,
73 I40E_DEBUG_PHY = 0x00000020,
74 I40E_DEBUG_HMC = 0x00000040,
75 I40E_DEBUG_NVM = 0x00000080,
76 I40E_DEBUG_LAN = 0x00000100,
77 I40E_DEBUG_FLOW = 0x00000200,
78 I40E_DEBUG_DCB = 0x00000400,
79 I40E_DEBUG_DIAG = 0x00000800,
80 I40E_DEBUG_FD = 0x00001000,
81 I40E_DEBUG_PACKAGE = 0x00002000,
82 I40E_DEBUG_IWARP = 0x00F00000,
83 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
84 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
85 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
86 I40E_DEBUG_AQ_COMMAND = 0x06000000,
87 I40E_DEBUG_AQ = 0x0F000000,
88
89 I40E_DEBUG_USER = 0xF0000000,
90
91 I40E_DEBUG_ALL = 0xFFFFFFFF
92};
93
94#define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
95 I40E_GLGEN_MSCA_STCODE_SHIFT)
96#define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
97 I40E_GLGEN_MSCA_OPCODE_SHIFT)
98#define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
99 I40E_GLGEN_MSCA_OPCODE_SHIFT)
100
101#define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
102 I40E_GLGEN_MSCA_STCODE_SHIFT)
103#define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
104 I40E_GLGEN_MSCA_OPCODE_SHIFT)
105#define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
106 I40E_GLGEN_MSCA_OPCODE_SHIFT)
107#define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
108 I40E_GLGEN_MSCA_OPCODE_SHIFT)
109#define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
110 I40E_GLGEN_MSCA_OPCODE_SHIFT)
111
112#define I40E_PHY_COM_REG_PAGE 0x1E
113#define I40E_PHY_LED_LINK_MODE_MASK 0xF0
114#define I40E_PHY_LED_MANUAL_ON 0x100
115#define I40E_PHY_LED_PROV_REG_1 0xC430
116#define I40E_PHY_LED_MODE_MASK 0xFFFF
117#define I40E_PHY_LED_MODE_ORIG 0x80000000
118
119
120
121
122
123
124
125
126
127enum i40e_mac_type {
128 I40E_MAC_UNKNOWN = 0,
129 I40E_MAC_XL710,
130 I40E_MAC_VF,
131 I40E_MAC_X722,
132 I40E_MAC_X722_VF,
133 I40E_MAC_GENERIC,
134};
135
136enum i40e_media_type {
137 I40E_MEDIA_TYPE_UNKNOWN = 0,
138 I40E_MEDIA_TYPE_FIBER,
139 I40E_MEDIA_TYPE_BASET,
140 I40E_MEDIA_TYPE_BACKPLANE,
141 I40E_MEDIA_TYPE_CX4,
142 I40E_MEDIA_TYPE_DA,
143 I40E_MEDIA_TYPE_VIRTUAL
144};
145
146enum i40e_fc_mode {
147 I40E_FC_NONE = 0,
148 I40E_FC_RX_PAUSE,
149 I40E_FC_TX_PAUSE,
150 I40E_FC_FULL,
151 I40E_FC_PFC,
152 I40E_FC_DEFAULT
153};
154
155enum i40e_set_fc_aq_failures {
156 I40E_SET_FC_AQ_FAIL_NONE = 0,
157 I40E_SET_FC_AQ_FAIL_GET = 1,
158 I40E_SET_FC_AQ_FAIL_SET = 2,
159 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
160 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
161};
162
163enum i40e_vsi_type {
164 I40E_VSI_MAIN = 0,
165 I40E_VSI_VMDQ1 = 1,
166 I40E_VSI_VMDQ2 = 2,
167 I40E_VSI_CTRL = 3,
168 I40E_VSI_FCOE = 4,
169 I40E_VSI_MIRROR = 5,
170 I40E_VSI_SRIOV = 6,
171 I40E_VSI_FDIR = 7,
172 I40E_VSI_IWARP = 8,
173 I40E_VSI_TYPE_UNKNOWN
174};
175
176enum i40e_queue_type {
177 I40E_QUEUE_TYPE_RX = 0,
178 I40E_QUEUE_TYPE_TX,
179 I40E_QUEUE_TYPE_PE_CEQ,
180 I40E_QUEUE_TYPE_UNKNOWN
181};
182
183struct i40e_link_status {
184 enum i40e_aq_phy_type phy_type;
185 enum i40e_aq_link_speed link_speed;
186 u8 link_info;
187 u8 an_info;
188 u8 fec_info;
189 u8 ext_info;
190 u8 loopback;
191
192 bool lse_enable;
193 u16 max_frame_size;
194 bool crc_enable;
195 u8 pacing;
196 u8 requested_speeds;
197 u8 module_type[3];
198
199#define I40E_MODULE_TYPE_SFP 0x03
200#define I40E_MODULE_TYPE_QSFP 0x0D
201
202#define I40E_MODULE_TYPE_40G_ACTIVE 0x01
203#define I40E_MODULE_TYPE_40G_LR4 0x02
204#define I40E_MODULE_TYPE_40G_SR4 0x04
205#define I40E_MODULE_TYPE_40G_CR4 0x08
206#define I40E_MODULE_TYPE_10G_BASE_SR 0x10
207#define I40E_MODULE_TYPE_10G_BASE_LR 0x20
208#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
209#define I40E_MODULE_TYPE_10G_BASE_ER 0x80
210
211#define I40E_MODULE_TYPE_1000BASE_SX 0x01
212#define I40E_MODULE_TYPE_1000BASE_LX 0x02
213#define I40E_MODULE_TYPE_1000BASE_CX 0x04
214#define I40E_MODULE_TYPE_1000BASE_T 0x08
215};
216
217struct i40e_phy_info {
218 struct i40e_link_status link_info;
219 struct i40e_link_status link_info_old;
220 bool get_link_info;
221 enum i40e_media_type media_type;
222
223 u64 phy_types;
224};
225
226#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
227#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
228#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
229#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
230#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
231#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
232#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
233#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
234#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
235#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
236#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
237#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
238#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
239#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
240#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
241#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
242#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
243#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
244#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
245#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
246#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
247#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
248#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
249#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
250#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
251#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
252#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
253 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
254#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
255
256
257
258
259
260
261#define I40E_PHY_TYPE_OFFSET 1
262#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
263 I40E_PHY_TYPE_OFFSET)
264#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
265 I40E_PHY_TYPE_OFFSET)
266#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
267 I40E_PHY_TYPE_OFFSET)
268#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
269 I40E_PHY_TYPE_OFFSET)
270#define I40E_HW_CAP_MAX_GPIO 30
271
272struct i40e_hw_capabilities {
273 u32 switch_mode;
274#define I40E_NVM_IMAGE_TYPE_EVB 0x0
275#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
276#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
277
278 u32 management_mode;
279 u32 mng_protocols_over_mctp;
280#define I40E_MNG_PROTOCOL_PLDM 0x2
281#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
282#define I40E_MNG_PROTOCOL_NCSI 0x8
283 u32 npar_enable;
284 u32 os2bmc;
285 u32 valid_functions;
286 bool sr_iov_1_1;
287 bool vmdq;
288 bool evb_802_1_qbg;
289 bool evb_802_1_qbh;
290 bool dcb;
291 bool fcoe;
292 bool iscsi;
293 bool flex10_enable;
294 bool flex10_capable;
295 u32 flex10_mode;
296#define I40E_FLEX10_MODE_UNKNOWN 0x0
297#define I40E_FLEX10_MODE_DCC 0x1
298#define I40E_FLEX10_MODE_DCI 0x2
299
300 u32 flex10_status;
301#define I40E_FLEX10_STATUS_DCC_ERROR 0x1
302#define I40E_FLEX10_STATUS_VC_MODE 0x2
303
304 bool sec_rev_disabled;
305 bool update_disabled;
306#define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
307#define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
308
309 bool mgmt_cem;
310 bool ieee_1588;
311 bool iwarp;
312 bool fd;
313 u32 fd_filters_guaranteed;
314 u32 fd_filters_best_effort;
315 bool rss;
316 u32 rss_table_size;
317 u32 rss_table_entry_width;
318 bool led[I40E_HW_CAP_MAX_GPIO];
319 bool sdp[I40E_HW_CAP_MAX_GPIO];
320 u32 nvm_image_type;
321 u32 num_flow_director_filters;
322 u32 num_vfs;
323 u32 vf_base_id;
324 u32 num_vsis;
325 u32 num_rx_qp;
326 u32 num_tx_qp;
327 u32 base_queue;
328 u32 num_msix_vectors;
329 u32 num_msix_vectors_vf;
330 u32 led_pin_num;
331 u32 sdp_pin_num;
332 u32 mdio_port_num;
333 u32 mdio_port_mode;
334 u8 rx_buf_chain_len;
335 u32 enabled_tcmap;
336 u32 maxtc;
337 u64 wr_csr_prot;
338};
339
340struct i40e_mac_info {
341 enum i40e_mac_type type;
342 u8 addr[ETH_ALEN];
343 u8 perm_addr[ETH_ALEN];
344 u8 san_addr[ETH_ALEN];
345 u8 port_addr[ETH_ALEN];
346 u16 max_fcoeq;
347};
348
349enum i40e_aq_resources_ids {
350 I40E_NVM_RESOURCE_ID = 1
351};
352
353enum i40e_aq_resource_access_type {
354 I40E_RESOURCE_READ = 1,
355 I40E_RESOURCE_WRITE
356};
357
358struct i40e_nvm_info {
359 u64 hw_semaphore_timeout;
360 u32 timeout;
361 u16 sr_size;
362 bool blank_nvm_mode;
363 u16 version;
364 u32 eetrack;
365 u32 oem_ver;
366};
367
368
369
370enum i40e_nvmupd_cmd {
371 I40E_NVMUPD_INVALID,
372 I40E_NVMUPD_READ_CON,
373 I40E_NVMUPD_READ_SNT,
374 I40E_NVMUPD_READ_LCB,
375 I40E_NVMUPD_READ_SA,
376 I40E_NVMUPD_WRITE_ERA,
377 I40E_NVMUPD_WRITE_CON,
378 I40E_NVMUPD_WRITE_SNT,
379 I40E_NVMUPD_WRITE_LCB,
380 I40E_NVMUPD_WRITE_SA,
381 I40E_NVMUPD_CSUM_CON,
382 I40E_NVMUPD_CSUM_SA,
383 I40E_NVMUPD_CSUM_LCB,
384 I40E_NVMUPD_STATUS,
385 I40E_NVMUPD_EXEC_AQ,
386 I40E_NVMUPD_GET_AQ_RESULT,
387};
388
389enum i40e_nvmupd_state {
390 I40E_NVMUPD_STATE_INIT,
391 I40E_NVMUPD_STATE_READING,
392 I40E_NVMUPD_STATE_WRITING,
393 I40E_NVMUPD_STATE_INIT_WAIT,
394 I40E_NVMUPD_STATE_WRITE_WAIT,
395 I40E_NVMUPD_STATE_ERROR
396};
397
398
399
400
401#define I40E_NVM_READ 0xB
402#define I40E_NVM_WRITE 0xC
403
404#define I40E_NVM_MOD_PNT_MASK 0xFF
405
406#define I40E_NVM_TRANS_SHIFT 8
407#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
408#define I40E_NVM_CON 0x0
409#define I40E_NVM_SNT 0x1
410#define I40E_NVM_LCB 0x2
411#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
412#define I40E_NVM_ERA 0x4
413#define I40E_NVM_CSUM 0x8
414#define I40E_NVM_EXEC 0xf
415
416#define I40E_NVM_ADAPT_SHIFT 16
417#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
418
419#define I40E_NVMUPD_MAX_DATA 4096
420#define I40E_NVMUPD_IFACE_TIMEOUT 2
421
422struct i40e_nvm_access {
423 u32 command;
424 u32 config;
425 u32 offset;
426 u32 data_size;
427 u8 data[1];
428};
429
430
431enum i40e_bus_type {
432 i40e_bus_type_unknown = 0,
433 i40e_bus_type_pci,
434 i40e_bus_type_pcix,
435 i40e_bus_type_pci_express,
436 i40e_bus_type_reserved
437};
438
439
440enum i40e_bus_speed {
441 i40e_bus_speed_unknown = 0,
442 i40e_bus_speed_33 = 33,
443 i40e_bus_speed_66 = 66,
444 i40e_bus_speed_100 = 100,
445 i40e_bus_speed_120 = 120,
446 i40e_bus_speed_133 = 133,
447 i40e_bus_speed_2500 = 2500,
448 i40e_bus_speed_5000 = 5000,
449 i40e_bus_speed_8000 = 8000,
450 i40e_bus_speed_reserved
451};
452
453
454enum i40e_bus_width {
455 i40e_bus_width_unknown = 0,
456 i40e_bus_width_pcie_x1 = 1,
457 i40e_bus_width_pcie_x2 = 2,
458 i40e_bus_width_pcie_x4 = 4,
459 i40e_bus_width_pcie_x8 = 8,
460 i40e_bus_width_32 = 32,
461 i40e_bus_width_64 = 64,
462 i40e_bus_width_reserved
463};
464
465
466struct i40e_bus_info {
467 enum i40e_bus_speed speed;
468 enum i40e_bus_width width;
469 enum i40e_bus_type type;
470
471 u16 func;
472 u16 device;
473 u16 lan_id;
474 u16 bus_id;
475};
476
477
478struct i40e_fc_info {
479 enum i40e_fc_mode current_mode;
480 enum i40e_fc_mode requested_mode;
481};
482
483#define I40E_MAX_TRAFFIC_CLASS 8
484#define I40E_MAX_USER_PRIORITY 8
485#define I40E_DCBX_MAX_APPS 32
486#define I40E_LLDPDU_SIZE 1500
487#define I40E_TLV_STATUS_OPER 0x1
488#define I40E_TLV_STATUS_SYNC 0x2
489#define I40E_TLV_STATUS_ERR 0x4
490#define I40E_CEE_OPER_MAX_APPS 3
491#define I40E_APP_PROTOID_FCOE 0x8906
492#define I40E_APP_PROTOID_ISCSI 0x0cbc
493#define I40E_APP_PROTOID_FIP 0x8914
494#define I40E_APP_SEL_ETHTYPE 0x1
495#define I40E_APP_SEL_TCPIP 0x2
496#define I40E_CEE_APP_SEL_ETHTYPE 0x0
497#define I40E_CEE_APP_SEL_TCPIP 0x1
498
499
500struct i40e_dcb_ets_config {
501 u8 willing;
502 u8 cbs;
503 u8 maxtcs;
504 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
505 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
506 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
507};
508
509
510struct i40e_dcb_pfc_config {
511 u8 willing;
512 u8 mbc;
513 u8 pfccap;
514 u8 pfcenable;
515};
516
517
518struct i40e_dcb_app_priority_table {
519 u8 priority;
520 u8 selector;
521 u16 protocolid;
522};
523
524struct i40e_dcbx_config {
525 u8 dcbx_mode;
526#define I40E_DCBX_MODE_CEE 0x1
527#define I40E_DCBX_MODE_IEEE 0x2
528 u8 app_mode;
529#define I40E_DCBX_APPS_NON_WILLING 0x1
530 u32 numapps;
531 u32 tlv_status;
532 struct i40e_dcb_ets_config etscfg;
533 struct i40e_dcb_ets_config etsrec;
534 struct i40e_dcb_pfc_config pfc;
535 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
536};
537
538
539struct i40e_hw {
540 u8 __iomem *hw_addr;
541 void *back;
542
543
544 struct i40e_phy_info phy;
545 struct i40e_mac_info mac;
546 struct i40e_bus_info bus;
547 struct i40e_nvm_info nvm;
548 struct i40e_fc_info fc;
549
550
551 u16 device_id;
552 u16 vendor_id;
553 u16 subsystem_device_id;
554 u16 subsystem_vendor_id;
555 u8 revision_id;
556 u8 port;
557 bool adapter_stopped;
558
559
560 struct i40e_hw_capabilities dev_caps;
561 struct i40e_hw_capabilities func_caps;
562
563
564 u16 fdir_shared_filter_count;
565
566
567 u8 pf_id;
568 u16 main_vsi_seid;
569
570
571 u16 partition_id;
572 u16 num_partitions;
573 u16 num_ports;
574
575
576 u16 numa_node;
577
578
579 struct i40e_adminq_info aq;
580
581
582 enum i40e_nvmupd_state nvmupd_state;
583 struct i40e_aq_desc nvm_wb_desc;
584 struct i40e_virt_mem nvm_buff;
585 bool nvm_release_on_done;
586 u16 nvm_wait_opcode;
587
588
589 struct i40e_hmc_info hmc;
590
591
592 u16 dcbx_status;
593
594
595 struct i40e_dcbx_config local_dcbx_config;
596 struct i40e_dcbx_config remote_dcbx_config;
597 struct i40e_dcbx_config desired_dcbx_config;
598
599#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
600 u64 flags;
601
602
603 u32 debug_mask;
604 char err_str[16];
605};
606
607static inline bool i40e_is_vf(struct i40e_hw *hw)
608{
609 return (hw->mac.type == I40E_MAC_VF ||
610 hw->mac.type == I40E_MAC_X722_VF);
611}
612
613struct i40e_driver_version {
614 u8 major_version;
615 u8 minor_version;
616 u8 build_version;
617 u8 subbuild_version;
618 u8 driver_string[32];
619};
620
621
622union i40e_16byte_rx_desc {
623 struct {
624 __le64 pkt_addr;
625 __le64 hdr_addr;
626 } read;
627 struct {
628 struct {
629 struct {
630 union {
631 __le16 mirroring_status;
632 __le16 fcoe_ctx_id;
633 } mirr_fcoe;
634 __le16 l2tag1;
635 } lo_dword;
636 union {
637 __le32 rss;
638 __le32 fd_id;
639 __le32 fcoe_param;
640 } hi_dword;
641 } qword0;
642 struct {
643
644 __le64 status_error_len;
645 } qword1;
646 } wb;
647};
648
649union i40e_32byte_rx_desc {
650 struct {
651 __le64 pkt_addr;
652 __le64 hdr_addr;
653
654 __le64 rsvd1;
655 __le64 rsvd2;
656 } read;
657 struct {
658 struct {
659 struct {
660 union {
661 __le16 mirroring_status;
662 __le16 fcoe_ctx_id;
663 } mirr_fcoe;
664 __le16 l2tag1;
665 } lo_dword;
666 union {
667 __le32 rss;
668 __le32 fcoe_param;
669
670
671
672 __le32 fd_id;
673 } hi_dword;
674 } qword0;
675 struct {
676
677 __le64 status_error_len;
678 } qword1;
679 struct {
680 __le16 ext_status;
681 __le16 rsvd;
682 __le16 l2tag2_1;
683 __le16 l2tag2_2;
684 } qword2;
685 struct {
686 union {
687 __le32 flex_bytes_lo;
688 __le32 pe_status;
689 } lo_dword;
690 union {
691 __le32 flex_bytes_hi;
692 __le32 fd_id;
693 } hi_dword;
694 } qword3;
695 } wb;
696};
697
698enum i40e_rx_desc_status_bits {
699
700 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
701 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
702 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
703 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
704 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
705 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5,
706 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
707
708 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
709 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9,
710 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
711 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12,
712 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
713 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
714 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16,
715
716
717
718 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
719 I40E_RX_DESC_STATUS_LAST
720};
721
722#define I40E_RXD_QW1_STATUS_SHIFT 0
723#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
724 << I40E_RXD_QW1_STATUS_SHIFT)
725
726#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
727#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
728 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
729
730#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
731#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
732 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
733
734enum i40e_rx_desc_fltstat_values {
735 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
736 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1,
737 I40E_RX_DESC_FLTSTAT_RSV = 2,
738 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
739};
740
741#define I40E_RXD_QW1_ERROR_SHIFT 19
742#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
743
744enum i40e_rx_desc_error_bits {
745
746 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
747 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
748 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
749 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3,
750 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
751 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
752 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
753 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
754 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
755};
756
757enum i40e_rx_desc_error_l3l4e_fcoe_masks {
758 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
759 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
760 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
761 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
762 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
763};
764
765#define I40E_RXD_QW1_PTYPE_SHIFT 30
766#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
767
768
769enum i40e_rx_l2_ptype {
770 I40E_RX_PTYPE_L2_RESERVED = 0,
771 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
772 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
773 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
774 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
775 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
776 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
777 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
778 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
779 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
780 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
781 I40E_RX_PTYPE_L2_ARP = 11,
782 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
783 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
784 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
785 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
786 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
787 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
788 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
789 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
790 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
791 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
792 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
793 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
794 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
795 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
796};
797
798struct i40e_rx_ptype_decoded {
799 u32 ptype:8;
800 u32 known:1;
801 u32 outer_ip:1;
802 u32 outer_ip_ver:1;
803 u32 outer_frag:1;
804 u32 tunnel_type:3;
805 u32 tunnel_end_prot:2;
806 u32 tunnel_end_frag:1;
807 u32 inner_prot:4;
808 u32 payload_layer:3;
809};
810
811enum i40e_rx_ptype_outer_ip {
812 I40E_RX_PTYPE_OUTER_L2 = 0,
813 I40E_RX_PTYPE_OUTER_IP = 1
814};
815
816enum i40e_rx_ptype_outer_ip_ver {
817 I40E_RX_PTYPE_OUTER_NONE = 0,
818 I40E_RX_PTYPE_OUTER_IPV4 = 0,
819 I40E_RX_PTYPE_OUTER_IPV6 = 1
820};
821
822enum i40e_rx_ptype_outer_fragmented {
823 I40E_RX_PTYPE_NOT_FRAG = 0,
824 I40E_RX_PTYPE_FRAG = 1
825};
826
827enum i40e_rx_ptype_tunnel_type {
828 I40E_RX_PTYPE_TUNNEL_NONE = 0,
829 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
830 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
831 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
832 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
833};
834
835enum i40e_rx_ptype_tunnel_end_prot {
836 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
837 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
838 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
839};
840
841enum i40e_rx_ptype_inner_prot {
842 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
843 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
844 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
845 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
846 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
847 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
848};
849
850enum i40e_rx_ptype_payload_layer {
851 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
852 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
853 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
854 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
855};
856
857#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
858#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
859 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
860
861#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
862#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
863 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
864
865#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
866#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
867
868enum i40e_rx_desc_ext_status_bits {
869
870 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
871 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
872 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2,
873 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4,
874 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
875 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
876 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
877};
878
879enum i40e_rx_desc_pe_status_bits {
880
881 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0,
882 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0,
883 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16,
884 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
885 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
886 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
887 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
888 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
889 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
890};
891
892#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
893#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
894
895#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
896#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
897 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
898
899#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
900#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
901 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
902
903enum i40e_rx_prog_status_desc_status_bits {
904
905 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
906 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2
907};
908
909enum i40e_rx_prog_status_desc_prog_id_masks {
910 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
911 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
912 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
913};
914
915enum i40e_rx_prog_status_desc_error_bits {
916
917 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
918 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
919 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
920 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
921};
922
923
924struct i40e_tx_desc {
925 __le64 buffer_addr;
926 __le64 cmd_type_offset_bsz;
927};
928
929#define I40E_TXD_QW1_DTYPE_SHIFT 0
930#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
931
932enum i40e_tx_desc_dtype_value {
933 I40E_TX_DESC_DTYPE_DATA = 0x0,
934 I40E_TX_DESC_DTYPE_NOP = 0x1,
935 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
936 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
937 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
938 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
939 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
940 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
941 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
942 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
943};
944
945#define I40E_TXD_QW1_CMD_SHIFT 4
946#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
947
948enum i40e_tx_desc_cmd_bits {
949 I40E_TX_DESC_CMD_EOP = 0x0001,
950 I40E_TX_DESC_CMD_RS = 0x0002,
951 I40E_TX_DESC_CMD_ICRC = 0x0004,
952 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
953 I40E_TX_DESC_CMD_DUMMY = 0x0010,
954 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000,
955 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020,
956 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040,
957 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060,
958 I40E_TX_DESC_CMD_FCOET = 0x0080,
959 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000,
960 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100,
961 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200,
962 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300,
963 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000,
964 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100,
965 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200,
966 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300,
967};
968
969#define I40E_TXD_QW1_OFFSET_SHIFT 16
970#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
971 I40E_TXD_QW1_OFFSET_SHIFT)
972
973enum i40e_tx_desc_length_fields {
974
975 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0,
976 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7,
977 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14
978};
979
980#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
981#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
982 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
983
984#define I40E_TXD_QW1_L2TAG1_SHIFT 48
985#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
986
987
988struct i40e_tx_context_desc {
989 __le32 tunneling_params;
990 __le16 l2tag2;
991 __le16 rsvd;
992 __le64 type_cmd_tso_mss;
993};
994
995#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
996#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
997
998#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
999#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1000
1001enum i40e_tx_ctx_desc_cmd_bits {
1002 I40E_TX_CTX_DESC_TSO = 0x01,
1003 I40E_TX_CTX_DESC_TSYN = 0x02,
1004 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1005 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1006 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1007 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1008 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1009 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1010 I40E_TX_CTX_DESC_SWPE = 0x40
1011};
1012
1013#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1014#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1015 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1016
1017#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1018#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1019 I40E_TXD_CTX_QW1_MSS_SHIFT)
1020
1021#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1022#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1023
1024#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1025#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1026 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1027
1028enum i40e_tx_ctx_desc_eipt_offload {
1029 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1030 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1031 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1032 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1033};
1034
1035#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1036#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1037 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1038
1039#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1040#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1041
1042#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1043#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1044
1045#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1046#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1047 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1048
1049#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1050
1051#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1052#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1053 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1054
1055#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1056#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1057 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1058
1059#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1060#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1061struct i40e_filter_program_desc {
1062 __le32 qindex_flex_ptype_vsi;
1063 __le32 rsvd;
1064 __le32 dtype_cmd_cntindex;
1065 __le32 fd_id;
1066};
1067#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1068#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1069 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1070#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1071#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1072 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1073#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1074#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1075 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1076
1077
1078enum i40e_filter_pctype {
1079
1080
1081
1082 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1083 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1084 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1085 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1086 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1087 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1088 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1089 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1090
1091
1092
1093 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1094 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1095 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1096 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1097 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1098 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1099 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1100 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1101
1102 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1103 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1104 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1105
1106 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1107};
1108
1109enum i40e_filter_program_desc_dest {
1110 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1111 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1112 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1113};
1114
1115enum i40e_filter_program_desc_fd_status {
1116 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1117 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1118 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1119 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1120};
1121
1122#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1123#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1124 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1125
1126#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1127#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1128 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1129
1130#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1131#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1132
1133enum i40e_filter_program_desc_pcmd {
1134 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1135 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1136};
1137
1138#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1139#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1140
1141#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1142#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1143
1144#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1145 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1146#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1147 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1148
1149#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1150 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1151#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1152
1153#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1154 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1155#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1156
1157#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1158#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1159 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1160
1161enum i40e_filter_type {
1162 I40E_FLOW_DIRECTOR_FLTR = 0,
1163 I40E_PE_QUAD_HASH_FLTR = 1,
1164 I40E_ETHERTYPE_FLTR,
1165 I40E_FCOE_CTX_FLTR,
1166 I40E_MAC_VLAN_FLTR,
1167 I40E_HASH_FLTR
1168};
1169
1170struct i40e_vsi_context {
1171 u16 seid;
1172 u16 uplink_seid;
1173 u16 vsi_number;
1174 u16 vsis_allocated;
1175 u16 vsis_unallocated;
1176 u16 flags;
1177 u8 pf_num;
1178 u8 vf_num;
1179 u8 connection_type;
1180 struct i40e_aqc_vsi_properties_data info;
1181};
1182
1183struct i40e_veb_context {
1184 u16 seid;
1185 u16 uplink_seid;
1186 u16 veb_number;
1187 u16 vebs_allocated;
1188 u16 vebs_unallocated;
1189 u16 flags;
1190 struct i40e_aqc_get_veb_parameters_completion info;
1191};
1192
1193
1194struct i40e_eth_stats {
1195 u64 rx_bytes;
1196 u64 rx_unicast;
1197 u64 rx_multicast;
1198 u64 rx_broadcast;
1199 u64 rx_discards;
1200 u64 rx_unknown_protocol;
1201 u64 tx_bytes;
1202 u64 tx_unicast;
1203 u64 tx_multicast;
1204 u64 tx_broadcast;
1205 u64 tx_discards;
1206 u64 tx_errors;
1207};
1208
1209
1210struct i40e_veb_tc_stats {
1211 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1212 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1213 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1214 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1215};
1216
1217
1218struct i40e_hw_port_stats {
1219
1220 struct i40e_eth_stats eth;
1221
1222
1223 u64 tx_dropped_link_down;
1224 u64 crc_errors;
1225 u64 illegal_bytes;
1226 u64 error_bytes;
1227 u64 mac_local_faults;
1228 u64 mac_remote_faults;
1229 u64 rx_length_errors;
1230 u64 link_xon_rx;
1231 u64 link_xoff_rx;
1232 u64 priority_xon_rx[8];
1233 u64 priority_xoff_rx[8];
1234 u64 link_xon_tx;
1235 u64 link_xoff_tx;
1236 u64 priority_xon_tx[8];
1237 u64 priority_xoff_tx[8];
1238 u64 priority_xon_2_xoff[8];
1239 u64 rx_size_64;
1240 u64 rx_size_127;
1241 u64 rx_size_255;
1242 u64 rx_size_511;
1243 u64 rx_size_1023;
1244 u64 rx_size_1522;
1245 u64 rx_size_big;
1246 u64 rx_undersize;
1247 u64 rx_fragments;
1248 u64 rx_oversize;
1249 u64 rx_jabber;
1250 u64 tx_size_64;
1251 u64 tx_size_127;
1252 u64 tx_size_255;
1253 u64 tx_size_511;
1254 u64 tx_size_1023;
1255 u64 tx_size_1522;
1256 u64 tx_size_big;
1257 u64 mac_short_packet_dropped;
1258 u64 checksum_error;
1259
1260 u64 fd_atr_match;
1261 u64 fd_sb_match;
1262 u64 fd_atr_tunnel_match;
1263 u32 fd_atr_status;
1264 u32 fd_sb_status;
1265
1266 u32 tx_lpi_status;
1267 u32 rx_lpi_status;
1268 u64 tx_lpi_count;
1269 u64 rx_lpi_count;
1270};
1271
1272
1273#define I40E_SR_NVM_CONTROL_WORD 0x00
1274#define I40E_SR_EMP_MODULE_PTR 0x0F
1275#define I40E_SR_PBA_FLAGS 0x15
1276#define I40E_SR_PBA_BLOCK_PTR 0x16
1277#define I40E_SR_BOOT_CONFIG_PTR 0x17
1278#define I40E_NVM_OEM_VER_OFF 0x83
1279#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1280#define I40E_SR_NVM_WAKE_ON_LAN 0x19
1281#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1282#define I40E_SR_NVM_EETRACK_LO 0x2D
1283#define I40E_SR_NVM_EETRACK_HI 0x2E
1284#define I40E_SR_VPD_PTR 0x2F
1285#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1286#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1287
1288
1289#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1290#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1291#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1292#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1293
1294
1295#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1296#define I40E_SR_WORDS_IN_1KB 512
1297
1298
1299
1300#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1301
1302#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1303
1304enum i40e_switch_element_types {
1305 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1306 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1307 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1308 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1309 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1310 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1311 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1312 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1313 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1314};
1315
1316
1317enum i40e_ether_type_index {
1318 I40E_ETHER_TYPE_1588 = 0,
1319 I40E_ETHER_TYPE_FIP = 1,
1320 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1321 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1322 I40E_ETHER_TYPE_LLDP = 4,
1323 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1324 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1325 I40E_ETHER_TYPE_QCN_CNM = 7,
1326 I40E_ETHER_TYPE_8021X = 8,
1327 I40E_ETHER_TYPE_ARP = 9,
1328 I40E_ETHER_TYPE_RSV1 = 10,
1329 I40E_ETHER_TYPE_RSV2 = 11,
1330};
1331
1332
1333#define I40E_HASH_FILTER_BASE_SIZE 1024
1334
1335enum i40e_hash_filter_size {
1336 I40E_HASH_FILTER_SIZE_1K = 0,
1337 I40E_HASH_FILTER_SIZE_2K = 1,
1338 I40E_HASH_FILTER_SIZE_4K = 2,
1339 I40E_HASH_FILTER_SIZE_8K = 3,
1340 I40E_HASH_FILTER_SIZE_16K = 4,
1341 I40E_HASH_FILTER_SIZE_32K = 5,
1342 I40E_HASH_FILTER_SIZE_64K = 6,
1343 I40E_HASH_FILTER_SIZE_128K = 7,
1344 I40E_HASH_FILTER_SIZE_256K = 8,
1345 I40E_HASH_FILTER_SIZE_512K = 9,
1346 I40E_HASH_FILTER_SIZE_1M = 10,
1347};
1348
1349
1350#define I40E_DMA_CNTX_BASE_SIZE 512
1351
1352enum i40e_dma_cntx_size {
1353 I40E_DMA_CNTX_SIZE_512 = 0,
1354 I40E_DMA_CNTX_SIZE_1K = 1,
1355 I40E_DMA_CNTX_SIZE_2K = 2,
1356 I40E_DMA_CNTX_SIZE_4K = 3,
1357 I40E_DMA_CNTX_SIZE_8K = 4,
1358 I40E_DMA_CNTX_SIZE_16K = 5,
1359 I40E_DMA_CNTX_SIZE_32K = 6,
1360 I40E_DMA_CNTX_SIZE_64K = 7,
1361 I40E_DMA_CNTX_SIZE_128K = 8,
1362 I40E_DMA_CNTX_SIZE_256K = 9,
1363};
1364
1365
1366enum i40e_hash_lut_size {
1367 I40E_HASH_LUT_SIZE_128 = 0,
1368 I40E_HASH_LUT_SIZE_512 = 1,
1369};
1370
1371
1372struct i40e_filter_control_settings {
1373
1374 enum i40e_hash_filter_size pe_filt_num;
1375
1376 enum i40e_dma_cntx_size pe_cntx_num;
1377
1378 enum i40e_hash_filter_size fcoe_filt_num;
1379
1380 enum i40e_dma_cntx_size fcoe_cntx_num;
1381
1382 enum i40e_hash_lut_size hash_lut_size;
1383
1384 bool enable_fdir;
1385
1386 bool enable_ethtype;
1387
1388 bool enable_macvlan;
1389};
1390
1391
1392struct i40e_control_filter_stats {
1393 u16 mac_etype_used;
1394 u16 etype_used;
1395 u16 mac_etype_free;
1396 u16 etype_free;
1397};
1398
1399enum i40e_reset_type {
1400 I40E_RESET_POR = 0,
1401 I40E_RESET_CORER = 1,
1402 I40E_RESET_GLOBR = 2,
1403 I40E_RESET_EMPR = 3,
1404};
1405
1406
1407#define I40E_NVM_LLDP_CFG_PTR 0xD
1408struct i40e_lldp_variables {
1409 u16 length;
1410 u16 adminstatus;
1411 u16 msgfasttx;
1412 u16 msgtxinterval;
1413 u16 txparams;
1414 u16 timers;
1415 u16 crc8;
1416};
1417
1418
1419#define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0
1420#define I40E_ALT_STRUCT_DWORDS_PER_PF 64
1421#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD
1422#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC
1423#define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE
1424#define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF
1425
1426
1427#define I40E_ALT_BW_VALUE_MASK 0xFF
1428#define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1429#define I40E_ALT_BW_VALID_MASK 0x80000000
1430
1431
1432#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1433
1434
1435#define I40E_L3_SRC_SHIFT 47
1436#define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1437#define I40E_L3_V6_SRC_SHIFT 43
1438#define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1439#define I40E_L3_DST_SHIFT 35
1440#define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1441#define I40E_L3_V6_DST_SHIFT 35
1442#define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1443#define I40E_L4_SRC_SHIFT 34
1444#define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1445#define I40E_L4_DST_SHIFT 33
1446#define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1447#define I40E_VERIFY_TAG_SHIFT 31
1448#define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1449
1450#define I40E_FLEX_50_SHIFT 13
1451#define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1452#define I40E_FLEX_51_SHIFT 12
1453#define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1454#define I40E_FLEX_52_SHIFT 11
1455#define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1456#define I40E_FLEX_53_SHIFT 10
1457#define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1458#define I40E_FLEX_54_SHIFT 9
1459#define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1460#define I40E_FLEX_55_SHIFT 8
1461#define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1462#define I40E_FLEX_56_SHIFT 7
1463#define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1464#define I40E_FLEX_57_SHIFT 6
1465#define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1466
1467
1468struct i40e_ppp_version {
1469 u8 major;
1470 u8 minor;
1471 u8 update;
1472 u8 draft;
1473};
1474
1475#define I40E_PPP_NAME_SIZE 32
1476
1477
1478struct i40e_package_header {
1479 struct i40e_ppp_version version;
1480 u32 segment_count;
1481 u32 segment_offset[1];
1482};
1483
1484
1485struct i40e_generic_seg_header {
1486#define SEGMENT_TYPE_METADATA 0x00000001
1487#define SEGMENT_TYPE_NOTES 0x00000002
1488#define SEGMENT_TYPE_I40E 0x00000011
1489#define SEGMENT_TYPE_X722 0x00000012
1490 u32 type;
1491 struct i40e_ppp_version version;
1492 u32 size;
1493 char name[I40E_PPP_NAME_SIZE];
1494};
1495
1496struct i40e_metadata_segment {
1497 struct i40e_generic_seg_header header;
1498 struct i40e_ppp_version version;
1499 u32 track_id;
1500 char name[I40E_PPP_NAME_SIZE];
1501};
1502
1503struct i40e_device_id_entry {
1504 u32 vendor_dev_id;
1505 u32 sub_vendor_dev_id;
1506};
1507
1508struct i40e_profile_segment {
1509 struct i40e_generic_seg_header header;
1510 struct i40e_ppp_version version;
1511 char name[I40E_PPP_NAME_SIZE];
1512 u32 device_table_count;
1513 struct i40e_device_id_entry device_table[1];
1514};
1515
1516struct i40e_section_table {
1517 u32 section_count;
1518 u32 section_offset[1];
1519};
1520
1521struct i40e_profile_section_header {
1522 u16 tbl_size;
1523 u16 data_end;
1524 struct {
1525#define SECTION_TYPE_INFO 0x00000010
1526#define SECTION_TYPE_MMIO 0x00000800
1527#define SECTION_TYPE_AQ 0x00000801
1528#define SECTION_TYPE_NOTE 0x80000000
1529#define SECTION_TYPE_NAME 0x80000001
1530 u32 type;
1531 u32 offset;
1532 u32 size;
1533 } section;
1534};
1535
1536struct i40e_profile_info {
1537 u32 track_id;
1538 struct i40e_ppp_version version;
1539 u8 op;
1540#define I40E_PPP_ADD_TRACKID 0x01
1541#define I40E_PPP_REMOVE_TRACKID 0x02
1542 u8 reserved[7];
1543 u8 name[I40E_PPP_NAME_SIZE];
1544};
1545#endif
1546
