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34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
37#include <linux/bitops.h>
38#include <linux/compiler.h>
39#include <linux/list.h>
40#include <linux/mutex.h>
41#include <linux/netdevice.h>
42#include <linux/if_vlan.h>
43#include <linux/net_tstamp.h>
44#ifdef CONFIG_MLX4_EN_DCB
45#include <linux/dcbnl.h>
46#endif
47#include <linux/cpu_rmap.h>
48#include <linux/ptp_clock_kernel.h>
49
50#include <linux/mlx4/device.h>
51#include <linux/mlx4/qp.h>
52#include <linux/mlx4/cq.h>
53#include <linux/mlx4/srq.h>
54#include <linux/mlx4/doorbell.h>
55#include <linux/mlx4/cmd.h>
56
57#include "en_port.h"
58#include "mlx4_stats.h"
59
60#define DRV_NAME "mlx4_en"
61#define DRV_VERSION "2.2-1"
62#define DRV_RELDATE "Feb 2014"
63
64#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
65
66
67
68
69
70
71#define MLX4_EN_PAGE_SHIFT 12
72#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73#define DEF_RX_RINGS 16
74#define MAX_RX_RINGS 128
75#define MIN_RX_RINGS 4
76#define TXBB_SIZE 64
77#define HEADROOM (2048 / TXBB_SIZE + 1)
78#define STAMP_STRIDE 64
79#define STAMP_DWORDS (STAMP_STRIDE / 4)
80#define STAMP_SHIFT 31
81#define STAMP_VAL 0x7fffffff
82#define STATS_DELAY (HZ / 4)
83#define SERVICE_TASK_DELAY (HZ / 4)
84#define MAX_NUM_OF_FS_RULES 256
85
86#define MLX4_EN_FILTER_HASH_SHIFT 4
87#define MLX4_EN_FILTER_EXPIRY_QUOTA 60
88
89
90#define MAX_DESC_SIZE 512
91#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
92
93
94
95
96
97#define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
98#define MLX4_EN_PRIV_FLAGS_PHV 2
99
100#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
101
102
103#define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
104
105#define MLX4_EN_MAX_RX_FRAGS 4
106
107
108#define MLX4_EN_MAX_TX_SIZE 8192
109#define MLX4_EN_MAX_RX_SIZE 8192
110
111
112#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
113#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
114
115#define MLX4_EN_SMALL_PKT_SIZE 64
116#define MLX4_EN_MIN_TX_RING_P_UP 1
117#define MLX4_EN_MAX_TX_RING_P_UP 32
118#define MLX4_EN_NUM_UP 8
119#define MLX4_EN_DEF_TX_RING_SIZE 512
120#define MLX4_EN_DEF_RX_RING_SIZE 1024
121#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
122 MLX4_EN_NUM_UP)
123
124#define MLX4_EN_DEFAULT_TX_WORK 256
125#define MLX4_EN_DOORBELL_BUDGET 8
126
127
128#define MLX4_EN_RX_COAL_TARGET 44
129#define MLX4_EN_RX_COAL_TIME 0x10
130
131#define MLX4_EN_TX_COAL_PKTS 16
132#define MLX4_EN_TX_COAL_TIME 0x10
133
134#define MLX4_EN_RX_RATE_LOW 400000
135#define MLX4_EN_RX_COAL_TIME_LOW 0
136#define MLX4_EN_RX_RATE_HIGH 450000
137#define MLX4_EN_RX_COAL_TIME_HIGH 128
138#define MLX4_EN_RX_SIZE_THRESH 1024
139#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
140#define MLX4_EN_SAMPLE_INTERVAL 0
141#define MLX4_EN_AVG_PKT_SMALL 256
142
143#define MLX4_EN_AUTO_CONF 0xffff
144
145#define MLX4_EN_DEF_RX_PAUSE 1
146#define MLX4_EN_DEF_TX_PAUSE 1
147
148
149
150#define MLX4_EN_TX_POLL_MODER 16
151#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
152
153#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
154#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
155#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
156
157#define MLX4_EN_MIN_MTU 46
158
159
160
161#define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
162#define ETH_BCAST 0xffffffffffffULL
163
164#define MLX4_EN_LOOPBACK_RETRIES 5
165#define MLX4_EN_LOOPBACK_TIMEOUT 100
166
167#ifdef MLX4_EN_PERF_STAT
168
169#define AVG_SIZE 128
170#define AVG_FACTOR 1024
171
172#define INC_PERF_COUNTER(cnt) (++(cnt))
173#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
174#define AVG_PERF_COUNTER(cnt, sample) \
175 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
176#define GET_PERF_COUNTER(cnt) (cnt)
177#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
178
179#else
180
181#define INC_PERF_COUNTER(cnt) do {} while (0)
182#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
183#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
184#define GET_PERF_COUNTER(cnt) (0)
185#define GET_AVG_PERF_COUNTER(cnt) (0)
186#endif
187
188
189enum {
190 MAX_INLINE = 104,
191 MAX_BF = 256,
192 MIN_PKT_LEN = 17,
193};
194
195
196
197
198
199enum cq_type {
200
201 TX,
202 TX_XDP,
203#define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
204 RX,
205};
206
207
208
209
210
211#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
212#define XNOR(x, y) (!(x) == !(y))
213
214
215struct mlx4_en_tx_info {
216 union {
217 struct sk_buff *skb;
218 struct page *page;
219 };
220 dma_addr_t map0_dma;
221 u32 map0_byte_count;
222 u32 nr_txbb;
223 u32 nr_bytes;
224 u8 linear;
225 u8 data_offset;
226 u8 inl;
227 u8 ts_requested;
228 u8 nr_maps;
229} ____cacheline_aligned_in_smp;
230
231
232#define MLX4_EN_BIT_DESC_OWN 0x80000000
233#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
234#define MLX4_EN_MEMTYPE_PAD 0x100
235#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
236
237
238struct mlx4_en_tx_desc {
239 struct mlx4_wqe_ctrl_seg ctrl;
240 union {
241 struct mlx4_wqe_data_seg data;
242 struct mlx4_wqe_lso_seg lso;
243 struct mlx4_wqe_inline_seg inl;
244 };
245};
246
247#define MLX4_EN_USE_SRQ 0x01000000
248
249#define MLX4_EN_CX3_LOW_ID 0x1000
250#define MLX4_EN_CX3_HIGH_ID 0x1005
251
252struct mlx4_en_rx_alloc {
253 struct page *page;
254 dma_addr_t dma;
255 u32 page_offset;
256};
257
258#define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
259
260struct mlx4_en_page_cache {
261 u32 index;
262 struct {
263 struct page *page;
264 dma_addr_t dma;
265 } buf[MLX4_EN_CACHE_SIZE];
266};
267
268struct mlx4_en_priv;
269
270struct mlx4_en_tx_ring {
271
272
273
274 u32 last_nr_txbb;
275 u32 cons;
276 unsigned long wake_queue;
277 struct netdev_queue *tx_queue;
278 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
279 struct mlx4_en_tx_ring *ring,
280 int index, u8 owner,
281 u64 timestamp, int napi_mode);
282 struct mlx4_en_rx_ring *recycle_ring;
283
284
285 u32 prod ____cacheline_aligned_in_smp;
286 unsigned int tx_dropped;
287 unsigned long bytes;
288 unsigned long packets;
289 unsigned long tx_csum;
290 unsigned long tso_packets;
291 unsigned long xmit_more;
292 struct mlx4_bf bf;
293
294
295 __be32 doorbell_qpn;
296 __be32 mr_key;
297 u32 size;
298 u32 size_mask;
299 u32 full_size;
300 u32 buf_size;
301 void *buf;
302 struct mlx4_en_tx_info *tx_info;
303 int qpn;
304 u8 queue_index;
305 bool bf_enabled;
306 bool bf_alloced;
307 u8 hwtstamp_tx_type;
308 u8 *bounce_buf;
309
310
311
312
313 unsigned long queue_stopped;
314 struct mlx4_hwq_resources sp_wqres;
315 struct mlx4_qp sp_qp;
316 struct mlx4_qp_context sp_context;
317 cpumask_t sp_affinity_mask;
318 enum mlx4_qp_state sp_qp_state;
319 u16 sp_stride;
320 u16 sp_cqn;
321} ____cacheline_aligned_in_smp;
322
323struct mlx4_en_rx_desc {
324
325 struct mlx4_wqe_data_seg data[0];
326};
327
328struct mlx4_en_rx_ring {
329 struct mlx4_hwq_resources wqres;
330 u32 size ;
331 u32 actual_size;
332 u32 size_mask;
333 u16 stride;
334 u16 log_stride;
335 u16 cqn;
336 u32 prod;
337 u32 cons;
338 u32 buf_size;
339 u8 fcs_del;
340 void *buf;
341 void *rx_info;
342 struct bpf_prog __rcu *xdp_prog;
343 struct mlx4_en_page_cache page_cache;
344 unsigned long bytes;
345 unsigned long packets;
346 unsigned long csum_ok;
347 unsigned long csum_none;
348 unsigned long csum_complete;
349 unsigned long rx_alloc_pages;
350 unsigned long xdp_drop;
351 unsigned long xdp_tx;
352 unsigned long xdp_tx_full;
353 unsigned long dropped;
354 int hwtstamp_rx_filter;
355 cpumask_var_t affinity_mask;
356};
357
358struct mlx4_en_cq {
359 struct mlx4_cq mcq;
360 struct mlx4_hwq_resources wqres;
361 int ring;
362 struct net_device *dev;
363 struct napi_struct napi;
364 int size;
365 int buf_size;
366 int vector;
367 enum cq_type type;
368 u16 moder_time;
369 u16 moder_cnt;
370 struct mlx4_cqe *buf;
371#define MLX4_EN_OPCODE_ERROR 0x1e
372
373 struct irq_desc *irq_desc;
374};
375
376struct mlx4_en_port_profile {
377 u32 flags;
378 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
379 u32 rx_ring_num;
380 u32 tx_ring_size;
381 u32 rx_ring_size;
382 u8 num_tx_rings_p_up;
383 u8 rx_pause;
384 u8 rx_ppp;
385 u8 tx_pause;
386 u8 tx_ppp;
387 int rss_rings;
388 int inline_thold;
389 struct hwtstamp_config hwtstamp_config;
390};
391
392struct mlx4_en_profile {
393 int udp_rss;
394 u8 rss_mask;
395 u32 active_ports;
396 u32 small_pkt_int;
397 u8 no_reset;
398 u8 num_tx_rings_p_up;
399 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
400};
401
402struct mlx4_en_dev {
403 struct mlx4_dev *dev;
404 struct pci_dev *pdev;
405 struct mutex state_lock;
406 struct net_device *pndev[MLX4_MAX_PORTS + 1];
407 struct net_device *upper[MLX4_MAX_PORTS + 1];
408 u32 port_cnt;
409 bool device_up;
410 struct mlx4_en_profile profile;
411 u32 LSO_support;
412 struct workqueue_struct *workqueue;
413 struct device *dma_device;
414 void __iomem *uar_map;
415 struct mlx4_uar priv_uar;
416 struct mlx4_mr mr;
417 u32 priv_pdn;
418 spinlock_t uar_lock;
419 u8 mac_removed[MLX4_MAX_PORTS + 1];
420 u32 nominal_c_mult;
421 struct cyclecounter cycles;
422 seqlock_t clock_lock;
423 struct timecounter clock;
424 unsigned long last_overflow_check;
425 struct ptp_clock *ptp_clock;
426 struct ptp_clock_info ptp_clock_info;
427 struct notifier_block nb;
428};
429
430
431struct mlx4_en_rss_map {
432 int base_qpn;
433 struct mlx4_qp qps[MAX_RX_RINGS];
434 enum mlx4_qp_state state[MAX_RX_RINGS];
435 struct mlx4_qp indir_qp;
436 enum mlx4_qp_state indir_state;
437};
438
439enum mlx4_en_port_flag {
440 MLX4_EN_PORT_ANC = 1<<0,
441 MLX4_EN_PORT_ANE = 1<<1,
442};
443
444struct mlx4_en_port_state {
445 int link_state;
446 int link_speed;
447 int transceiver;
448 u32 flags;
449};
450
451enum mlx4_en_mclist_act {
452 MCLIST_NONE,
453 MCLIST_REM,
454 MCLIST_ADD,
455};
456
457struct mlx4_en_mc_list {
458 struct list_head list;
459 enum mlx4_en_mclist_act action;
460 u8 addr[ETH_ALEN];
461 u64 reg_id;
462 u64 tunnel_reg_id;
463};
464
465struct mlx4_en_frag_info {
466 u16 frag_size;
467 u32 frag_stride;
468};
469
470#ifdef CONFIG_MLX4_EN_DCB
471
472#define MLX4_EN_BW_MIN 1
473#define MLX4_EN_BW_MAX 100
474
475#define MLX4_EN_TC_ETS 7
476
477enum dcb_pfc_type {
478 pfc_disabled = 0,
479 pfc_enabled_full,
480 pfc_enabled_tx,
481 pfc_enabled_rx
482};
483
484struct mlx4_en_cee_config {
485 bool pfc_state;
486 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP];
487};
488#endif
489
490struct ethtool_flow_id {
491 struct list_head list;
492 struct ethtool_rx_flow_spec flow_spec;
493 u64 id;
494};
495
496enum {
497 MLX4_EN_FLAG_PROMISC = (1 << 0),
498 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
499
500
501
502 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
503
504 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
505 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
506 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
507#ifdef CONFIG_MLX4_EN_DCB
508 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
509#endif
510};
511
512#define PORT_BEACON_MAX_LIMIT (65535)
513#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
514#define MLX4_EN_MAC_HASH_IDX 5
515
516struct mlx4_en_stats_bitmap {
517 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
518 struct mutex mutex;
519};
520
521struct mlx4_en_priv {
522 struct mlx4_en_dev *mdev;
523 struct mlx4_en_port_profile *prof;
524 struct net_device *dev;
525 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
526 struct mlx4_en_port_state port_state;
527 spinlock_t stats_lock;
528 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
529
530 struct list_head ethtool_list;
531
532 unsigned long last_moder_packets[MAX_RX_RINGS];
533 unsigned long last_moder_tx_packets;
534 unsigned long last_moder_bytes[MAX_RX_RINGS];
535 unsigned long last_moder_jiffies;
536 int last_moder_time[MAX_RX_RINGS];
537 u16 rx_usecs;
538 u16 rx_frames;
539 u16 tx_usecs;
540 u16 tx_frames;
541 u32 pkt_rate_low;
542 u16 rx_usecs_low;
543 u32 pkt_rate_high;
544 u16 rx_usecs_high;
545 u16 sample_interval;
546 u16 adaptive_rx_coal;
547 u32 msg_enable;
548 u32 loopback_ok;
549 u32 validate_loopback;
550
551 struct mlx4_hwq_resources res;
552 int link_state;
553 int last_link_state;
554 bool port_up;
555 int port;
556 int registered;
557 int allocated;
558 int stride;
559 unsigned char current_mac[ETH_ALEN + 2];
560 int mac_index;
561 unsigned max_mtu;
562 int base_qpn;
563 int cqe_factor;
564 int cqe_size;
565
566 struct mlx4_en_rss_map rss_map;
567 __be32 ctrl_flags;
568 u32 flags;
569 u8 num_tx_rings_p_up;
570 u32 tx_work_limit;
571 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
572 u32 rx_ring_num;
573 u32 rx_skb_size;
574 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
575 u8 num_frags;
576 u8 log_rx_info;
577 u8 dma_dir;
578 u16 rx_headroom;
579
580 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
581 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
582 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
583 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
584 struct mlx4_qp drop_qp;
585 struct work_struct rx_mode_task;
586 struct work_struct watchdog_task;
587 struct work_struct linkstate_task;
588 struct delayed_work stats_task;
589 struct delayed_work service_task;
590 struct work_struct vxlan_add_task;
591 struct work_struct vxlan_del_task;
592 struct mlx4_en_perf_stats pstats;
593 struct mlx4_en_pkt_stats pkstats;
594 struct mlx4_en_counter_stats pf_stats;
595 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
596 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
597 struct mlx4_en_flow_stats_rx rx_flowstats;
598 struct mlx4_en_flow_stats_tx tx_flowstats;
599 struct mlx4_en_port_stats port_stats;
600 struct mlx4_en_xdp_stats xdp_stats;
601 struct mlx4_en_stats_bitmap stats_bitmap;
602 struct list_head mc_list;
603 struct list_head curr_list;
604 u64 broadcast_id;
605 struct mlx4_en_stat_out_mbox hw_stats;
606 int vids[128];
607 bool wol;
608 struct device *ddev;
609 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
610 struct hwtstamp_config hwtstamp_config;
611 u32 counter_index;
612
613#ifdef CONFIG_MLX4_EN_DCB
614#define MLX4_EN_DCB_ENABLED 0x3
615 struct ieee_ets ets;
616 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
617 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
618 struct mlx4_en_cee_config cee_config;
619 u8 dcbx_cap;
620#endif
621#ifdef CONFIG_RFS_ACCEL
622 spinlock_t filters_lock;
623 int last_filter_id;
624 struct list_head filters;
625 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
626#endif
627 u64 tunnel_reg_id;
628 __be16 vxlan_port;
629
630 u32 pflags;
631 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
632 u8 rss_hash_fn;
633};
634
635enum mlx4_en_wol {
636 MLX4_EN_WOL_MAGIC = (1ULL << 61),
637 MLX4_EN_WOL_ENABLED = (1ULL << 62),
638};
639
640struct mlx4_mac_entry {
641 struct hlist_node hlist;
642 unsigned char mac[ETH_ALEN + 2];
643 u64 reg_id;
644 struct rcu_head rcu;
645};
646
647static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
648{
649 return buf + idx * cqe_sz;
650}
651
652#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
653
654void mlx4_en_init_ptys2ethtool_map(void);
655void mlx4_en_update_loopback_state(struct net_device *dev,
656 netdev_features_t features);
657
658void mlx4_en_destroy_netdev(struct net_device *dev);
659int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
660 struct mlx4_en_port_profile *prof);
661
662int mlx4_en_start_port(struct net_device *dev);
663void mlx4_en_stop_port(struct net_device *dev, int detach);
664
665void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
666 struct mlx4_en_stats_bitmap *stats_bitmap,
667 u8 rx_ppp, u8 rx_pause,
668 u8 tx_ppp, u8 tx_pause);
669
670int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
671 struct mlx4_en_priv *tmp,
672 struct mlx4_en_port_profile *prof,
673 bool carry_xdp_prog);
674void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
675 struct mlx4_en_priv *tmp);
676
677int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
678 int entries, int ring, enum cq_type mode, int node);
679void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
680int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
681 int cq_idx);
682void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
683int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
684int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
685
686void mlx4_en_tx_irq(struct mlx4_cq *mcq);
687u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
688 void *accel_priv, select_queue_fallback_t fallback);
689netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
690netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
691 struct mlx4_en_rx_alloc *frame,
692 struct net_device *dev, unsigned int length,
693 int tx_ind, int *doorbell_pending);
694void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
695bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
696 struct mlx4_en_rx_alloc *frame);
697
698int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
699 struct mlx4_en_tx_ring **pring,
700 u32 size, u16 stride,
701 int node, int queue_index);
702void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
703 struct mlx4_en_tx_ring **pring);
704int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
705 struct mlx4_en_tx_ring *ring,
706 int cq, int user_prio);
707void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
708 struct mlx4_en_tx_ring *ring);
709void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
710void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
711int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
712 struct mlx4_en_rx_ring **pring,
713 u32 size, u16 stride, int node);
714void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
715 struct mlx4_en_rx_ring **pring,
716 u32 size, u16 stride);
717int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
718void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
719 struct mlx4_en_rx_ring *ring);
720int mlx4_en_process_rx_cq(struct net_device *dev,
721 struct mlx4_en_cq *cq,
722 int budget);
723int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
724int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
725u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
726 struct mlx4_en_tx_ring *ring,
727 int index, u8 owner, u64 timestamp,
728 int napi_mode);
729u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
730 struct mlx4_en_tx_ring *ring,
731 int index, u8 owner, u64 timestamp,
732 int napi_mode);
733void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
734 int is_tx, int rss, int qpn, int cqn, int user_prio,
735 struct mlx4_qp_context *context);
736void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
737int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
738 int loopback);
739void mlx4_en_calc_rx_buf(struct net_device *dev);
740int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
741void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
742int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
743void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
744int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
745void mlx4_en_rx_irq(struct mlx4_cq *mcq);
746
747int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
748int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
749
750void mlx4_en_fold_software_stats(struct net_device *dev);
751int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
752int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
753
754#ifdef CONFIG_MLX4_EN_DCB
755extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
756extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
757#endif
758
759int mlx4_en_setup_tc(struct net_device *dev, u8 up);
760
761#ifdef CONFIG_RFS_ACCEL
762void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
763#endif
764
765#define MLX4_EN_NUM_SELF_TEST 5
766void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
767void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
768
769#define DEV_FEATURE_CHANGED(dev, new_features, feature) \
770 ((dev->features & feature) ^ (new_features & feature))
771
772int mlx4_en_reset_config(struct net_device *dev,
773 struct hwtstamp_config ts_config,
774 netdev_features_t new_features);
775void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
776 struct mlx4_en_stats_bitmap *stats_bitmap,
777 u8 rx_ppp, u8 rx_pause,
778 u8 tx_ppp, u8 tx_pause);
779int mlx4_en_netdev_event(struct notifier_block *this,
780 unsigned long event, void *ptr);
781
782
783
784
785u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
786void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
787 struct skb_shared_hwtstamps *hwts,
788 u64 timestamp);
789void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
790void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
791
792
793
794extern const struct ethtool_ops mlx4_en_ethtool_ops;
795
796
797
798
799
800
801
802__printf(3, 4)
803void en_print(const char *level, const struct mlx4_en_priv *priv,
804 const char *format, ...);
805
806#define en_dbg(mlevel, priv, format, ...) \
807do { \
808 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
809 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
810} while (0)
811#define en_warn(priv, format, ...) \
812 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
813#define en_err(priv, format, ...) \
814 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
815#define en_info(priv, format, ...) \
816 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
817
818#define mlx4_err(mdev, format, ...) \
819 pr_err(DRV_NAME " %s: " format, \
820 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
821#define mlx4_info(mdev, format, ...) \
822 pr_info(DRV_NAME " %s: " format, \
823 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
824#define mlx4_warn(mdev, format, ...) \
825 pr_warn(DRV_NAME " %s: " format, \
826 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
827
828#endif
829
