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20#ifndef _PCH_GBE_H_
21#define _PCH_GBE_H_
22
23#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25#include <linux/mii.h>
26#include <linux/delay.h>
27#include <linux/pci.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/vmalloc.h>
32#include <net/ip.h>
33#include <net/tcp.h>
34#include <net/udp.h>
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40
41struct pch_gbe_regs_mac_adr {
42 u32 high;
43 u32 low;
44};
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46
47
48struct pch_gbe_regs {
49 u32 INT_ST;
50 u32 INT_EN;
51 u32 MODE;
52 u32 RESET;
53 u32 TCPIP_ACC;
54 u32 EX_LIST;
55 u32 INT_ST_HOLD;
56 u32 PHY_INT_CTRL;
57 u32 MAC_RX_EN;
58 u32 RX_FCTRL;
59 u32 PAUSE_REQ;
60 u32 RX_MODE;
61 u32 TX_MODE;
62 u32 RX_FIFO_ST;
63 u32 TX_FIFO_ST;
64 u32 TX_FID;
65 u32 TX_RESULT;
66 u32 PAUSE_PKT1;
67 u32 PAUSE_PKT2;
68 u32 PAUSE_PKT3;
69 u32 PAUSE_PKT4;
70 u32 PAUSE_PKT5;
71 u32 reserve[2];
72 struct pch_gbe_regs_mac_adr mac_adr[16];
73 u32 ADDR_MASK;
74 u32 MIIM;
75 u32 MAC_ADDR_LOAD;
76 u32 RGMII_ST;
77 u32 RGMII_CTRL;
78 u32 reserve3[3];
79 u32 DMA_CTRL;
80 u32 reserve4[3];
81 u32 RX_DSC_BASE;
82 u32 RX_DSC_SIZE;
83 u32 RX_DSC_HW_P;
84 u32 RX_DSC_HW_P_HLD;
85 u32 RX_DSC_SW_P;
86 u32 reserve5[3];
87 u32 TX_DSC_BASE;
88 u32 TX_DSC_SIZE;
89 u32 TX_DSC_HW_P;
90 u32 TX_DSC_HW_P_HLD;
91 u32 TX_DSC_SW_P;
92 u32 reserve6[3];
93 u32 RX_DMA_ST;
94 u32 TX_DMA_ST;
95 u32 reserve7[2];
96 u32 WOL_ST;
97 u32 WOL_CTRL;
98 u32 WOL_ADDR_MASK;
99};
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103
104#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001
105#define PCH_GBE_INT_RX_VALID 0x00000002
106#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004
107#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008
108#define PCH_GBE_INT_RX_DMA_ERR 0x00000010
109#define PCH_GBE_INT_RX_DSC_EMP 0x00000020
110#define PCH_GBE_INT_TX_CMPLT 0x00000100
111#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200
112#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400
113#define PCH_GBE_INT_TX_DMA_ERR 0x00000800
114#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000
115#define PCH_GBE_INT_MIIM_CMPLT 0x00010000
116#define PCH_GBE_INT_PHY_INT 0x00100000
117#define PCH_GBE_INT_WOL_DET 0x01000000
118#define PCH_GBE_INT_TCPIP_ERR 0x10000000
119
120
121#define PCH_GBE_MODE_MII_ETHER 0x00000000
122#define PCH_GBE_MODE_GMII_ETHER 0x80000000
123#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000
124#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000
125#define PCH_GBE_MODE_FR_BST 0x04000000
126
127
128#define PCH_GBE_ALL_RST 0x80000000
129#define PCH_GBE_TX_RST 0x00008000
130#define PCH_GBE_RX_RST 0x00004000
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132
133#define PCH_GBE_EX_LIST_EN 0x00000008
134#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004
135#define PCH_GBE_TX_TCPIPACC_EN 0x00000002
136#define PCH_GBE_RX_TCPIPACC_EN 0x00000001
137
138
139#define PCH_GBE_MRE_MAC_RX_EN 0x00000001
140
141
142#define PCH_GBE_FL_CTRL_EN 0x80000000
143
144
145#define PCH_GBE_PS_PKT_RQ 0x80000000
146
147
148#define PCH_GBE_ADD_FIL_EN 0x80000000
149
150#define PCH_GBE_MLT_FIL_EN 0x40000000
151
152#define PCH_GBE_RH_ALM_EMP_4 0x00000000
153#define PCH_GBE_RH_ALM_EMP_8 0x00004000
154#define PCH_GBE_RH_ALM_EMP_16 0x00008000
155#define PCH_GBE_RH_ALM_EMP_32 0x0000C000
156
157#define PCH_GBE_RH_ALM_FULL_4 0x00000000
158#define PCH_GBE_RH_ALM_FULL_8 0x00001000
159#define PCH_GBE_RH_ALM_FULL_16 0x00002000
160#define PCH_GBE_RH_ALM_FULL_32 0x00003000
161
162#define PCH_GBE_RH_RD_TRG_4 0x00000000
163#define PCH_GBE_RH_RD_TRG_8 0x00000200
164#define PCH_GBE_RH_RD_TRG_16 0x00000400
165#define PCH_GBE_RH_RD_TRG_32 0x00000600
166#define PCH_GBE_RH_RD_TRG_64 0x00000800
167#define PCH_GBE_RH_RD_TRG_128 0x00000A00
168#define PCH_GBE_RH_RD_TRG_256 0x00000C00
169#define PCH_GBE_RH_RD_TRG_512 0x00000E00
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171
172#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
173#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
174#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
175#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000C0
176#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
177#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
178#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
179#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
180#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
181#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
182#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
183#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
184#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
185#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
186#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
187#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
188#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
189#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
190#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
191#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
192#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
193#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
194
195
196#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
197#define PCH_GBE_TXD_CTRL_ITAG 0x0004
198#define PCH_GBE_TXD_CTRL_ICRC 0x0002
199#define PCH_GBE_TXD_CTRL_APAD 0x0001
200#define PCH_GBE_TXD_WORDS_SHIFT 2
201#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
202#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
203#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
204#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
205#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
206#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
207#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
208#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
209#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
210#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
211#define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK 0x000F
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213
214#define PCH_GBE_TM_NO_RTRY 0x80000000
215#define PCH_GBE_TM_LONG_PKT 0x40000000
216#define PCH_GBE_TM_ST_AND_FD 0x20000000
217#define PCH_GBE_TM_SHORT_PKT 0x10000000
218#define PCH_GBE_TM_LTCOL_RETX 0x08000000
219
220#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000
221#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000
222#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000
223#define PCH_GBE_TM_TH_TX_STRT_32 0x0000C000
224
225#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000
226#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800
227#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000
228#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800
229#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000
230#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800
231#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000
232#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800
233
234#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000
235#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200
236#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400
237#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600
238
239
240#define PCH_GBE_RF_ALM_FULL 0x80000000
241#define PCH_GBE_RF_ALM_EMP 0x40000000
242#define PCH_GBE_RF_RD_TRG 0x20000000
243#define PCH_GBE_RF_STRWD 0x1FFE0000
244#define PCH_GBE_RF_RCVING 0x00010000
245
246
247#define PCH_GBE_BUSY 0x80000000
248
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250#define PCH_GBE_MIIM_OPER_WRITE 0x04000000
251#define PCH_GBE_MIIM_OPER_READ 0x00000000
252#define PCH_GBE_MIIM_OPER_READY 0x04000000
253#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
254#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
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257#define PCH_GBE_LINK_UP 0x80000008
258#define PCH_GBE_RXC_SPEED_MSK 0x00000006
259#define PCH_GBE_RXC_SPEED_2_5M 0x00000000
260#define PCH_GBE_RXC_SPEED_25M 0x00000002
261#define PCH_GBE_RXC_SPEED_125M 0x00000004
262#define PCH_GBE_DUPLEX_FULL 0x00000001
263
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265#define PCH_GBE_CRS_SEL 0x00000010
266#define PCH_GBE_RGMII_RATE_125M 0x00000000
267#define PCH_GBE_RGMII_RATE_25M 0x00000008
268#define PCH_GBE_RGMII_RATE_2_5M 0x0000000C
269#define PCH_GBE_RGMII_MODE_GMII 0x00000000
270#define PCH_GBE_RGMII_MODE_RGMII 0x00000002
271#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
272#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
273
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275#define PCH_GBE_RX_DMA_EN 0x00000002
276#define PCH_GBE_TX_DMA_EN 0x00000001
277
278
279#define PCH_GBE_IDLE_CHECK 0xFFFFFFFE
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282#define PCH_GBE_WLS_BR 0x00000008
283#define PCH_GBE_WLS_MLT 0x00000004
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286#define PCH_GBE_WLS_IND 0x00000002
287#define PCH_GBE_WLS_MP 0x00000001
288
289
290#define PCH_GBE_WLC_WOL_MODE 0x00010000
291#define PCH_GBE_WLC_IGN_TLONG 0x00000100
292#define PCH_GBE_WLC_IGN_TSHRT 0x00000080
293#define PCH_GBE_WLC_IGN_OCTER 0x00000040
294#define PCH_GBE_WLC_IGN_NBLER 0x00000020
295#define PCH_GBE_WLC_IGN_CRCER 0x00000010
296#define PCH_GBE_WLC_BR 0x00000008
297#define PCH_GBE_WLC_MLT 0x00000004
298#define PCH_GBE_WLC_IND 0x00000002
299#define PCH_GBE_WLC_MP 0x00000001
300
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302#define PCH_GBE_WLA_BUSY 0x80000000
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307#define PCH_GBE_MAX_TXD 4096
308#define PCH_GBE_DEFAULT_TXD 256
309#define PCH_GBE_MIN_TXD 8
310#define PCH_GBE_MAX_RXD 4096
311#define PCH_GBE_DEFAULT_RXD 256
312#define PCH_GBE_MIN_RXD 8
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315#define PCH_GBE_TX_DESC_MULTIPLE 8
316#define PCH_GBE_RX_DESC_MULTIPLE 8
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318
319#define PCH_GBE_HAL_MIIM_READ ((u32)0x00000000)
320#define PCH_GBE_HAL_MIIM_WRITE ((u32)0x04000000)
321
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323#define PCH_GBE_FC_NONE 0
324#define PCH_GBE_FC_RX_PAUSE 1
325#define PCH_GBE_FC_TX_PAUSE 2
326#define PCH_GBE_FC_FULL 3
327#define PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL
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330struct pch_gbe_hw;
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343struct pch_gbe_functions {
344 void (*get_bus_info) (struct pch_gbe_hw *);
345 s32 (*init_hw) (struct pch_gbe_hw *);
346 s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
347 s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
348 void (*reset_phy) (struct pch_gbe_hw *);
349 void (*sw_reset_phy) (struct pch_gbe_hw *);
350 void (*power_up_phy) (struct pch_gbe_hw *hw);
351 void (*power_down_phy) (struct pch_gbe_hw *hw);
352 s32 (*read_mac_addr) (struct pch_gbe_hw *);
353};
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367struct pch_gbe_mac_info {
368 u8 addr[6];
369 u8 fc;
370 u8 fc_autoneg;
371 u8 tx_fc_enable;
372 u32 max_frame_size;
373 u32 min_frame_size;
374 u8 autoneg;
375 u16 link_speed;
376 u16 link_duplex;
377};
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387struct pch_gbe_phy_info {
388 u32 addr;
389 u32 id;
390 u32 revision;
391 u32 reset_delay_us;
392 u16 autoneg_advertised;
393};
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400struct pch_gbe_bus_info {
401 u8 type;
402 u8 speed;
403 u8 width;
404};
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411struct pch_gbe_hw {
412 void *back;
413
414 struct pch_gbe_regs __iomem *reg;
415 spinlock_t miim_lock;
416
417 const struct pch_gbe_functions *func;
418 struct pch_gbe_mac_info mac;
419 struct pch_gbe_phy_info phy;
420 struct pch_gbe_bus_info bus;
421};
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433struct pch_gbe_rx_desc {
434 u32 buffer_addr;
435 u32 tcp_ip_status;
436 u16 rx_words_eob;
437 u16 gbec_status;
438 u8 dma_status;
439 u8 reserved1;
440 u16 reserved2;
441};
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454struct pch_gbe_tx_desc {
455 u32 buffer_addr;
456 u16 length;
457 u16 reserved1;
458 u16 tx_words_eob;
459 u16 tx_frame_ctrl;
460 u8 dma_status;
461 u8 reserved2;
462 u16 gbec_status;
463};
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473struct pch_gbe_buffer {
474 struct sk_buff *skb;
475 dma_addr_t dma;
476 unsigned char *rx_buffer;
477 unsigned long time_stamp;
478 u16 length;
479 bool mapped;
480};
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492struct pch_gbe_tx_ring {
493 struct pch_gbe_tx_desc *desc;
494 dma_addr_t dma;
495 unsigned int size;
496 unsigned int count;
497 unsigned int next_to_use;
498 unsigned int next_to_clean;
499 struct pch_gbe_buffer *buffer_info;
500};
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512struct pch_gbe_rx_ring {
513 struct pch_gbe_rx_desc *desc;
514 dma_addr_t dma;
515 unsigned char *rx_buff_pool;
516 dma_addr_t rx_buff_pool_logic;
517 unsigned int rx_buff_pool_size;
518 unsigned int size;
519 unsigned int count;
520 unsigned int next_to_use;
521 unsigned int next_to_clean;
522 struct pch_gbe_buffer *buffer_info;
523};
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553struct pch_gbe_hw_stats {
554 u32 rx_packets;
555 u32 tx_packets;
556 u32 rx_bytes;
557 u32 tx_bytes;
558 u32 rx_errors;
559 u32 tx_errors;
560 u32 rx_dropped;
561 u32 tx_dropped;
562 u32 multicast;
563 u32 collisions;
564 u32 rx_crc_errors;
565 u32 rx_frame_errors;
566 u32 rx_alloc_buff_failed;
567 u32 tx_length_errors;
568 u32 tx_aborted_errors;
569 u32 tx_carrier_errors;
570 u32 tx_timeout_count;
571 u32 tx_restart_count;
572 u32 intr_rx_dsc_empty_count;
573 u32 intr_rx_frame_err_count;
574 u32 intr_rx_fifo_err_count;
575 u32 intr_rx_dma_err_count;
576 u32 intr_tx_fifo_err_count;
577 u32 intr_tx_dma_err_count;
578 u32 intr_tcpip_err_count;
579};
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588struct pch_gbe_privdata {
589 bool phy_tx_clk_delay;
590 bool phy_disable_hibernate;
591 int (*platform_init)(struct pci_dev *pdev);
592};
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620struct pch_gbe_adapter {
621 spinlock_t stats_lock;
622 spinlock_t ethtool_lock;
623 atomic_t irq_sem;
624 struct net_device *netdev;
625 struct pci_dev *pdev;
626 struct net_device *polling_netdev;
627 struct napi_struct napi;
628 struct pch_gbe_hw hw;
629 struct pch_gbe_hw_stats stats;
630 struct work_struct reset_task;
631 struct mii_if_info mii;
632 struct timer_list watchdog_timer;
633 u32 wake_up_evt;
634 u32 *config_space;
635 unsigned long led_status;
636 struct pch_gbe_tx_ring *tx_ring;
637 struct pch_gbe_rx_ring *rx_ring;
638 unsigned long rx_buffer_len;
639 unsigned long tx_queue_len;
640 bool have_msi;
641 bool rx_stop_flag;
642 int hwts_tx_en;
643 int hwts_rx_en;
644 struct pci_dev *ptp_pdev;
645 struct pch_gbe_privdata *pdata;
646};
647
648#define pch_gbe_hw_to_adapter(hw) container_of(hw, struct pch_gbe_adapter, hw)
649
650extern const char pch_driver_version[];
651
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653int pch_gbe_up(struct pch_gbe_adapter *adapter);
654void pch_gbe_down(struct pch_gbe_adapter *adapter);
655void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
656void pch_gbe_reset(struct pch_gbe_adapter *adapter);
657int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
658 struct pch_gbe_tx_ring *txdr);
659int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
660 struct pch_gbe_rx_ring *rxdr);
661void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
662 struct pch_gbe_tx_ring *tx_ring);
663void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
664 struct pch_gbe_rx_ring *rx_ring);
665void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
666u32 pch_ch_control_read(struct pci_dev *pdev);
667void pch_ch_control_write(struct pci_dev *pdev, u32 val);
668u32 pch_ch_event_read(struct pci_dev *pdev);
669void pch_ch_event_write(struct pci_dev *pdev, u32 val);
670u32 pch_src_uuid_lo_read(struct pci_dev *pdev);
671u32 pch_src_uuid_hi_read(struct pci_dev *pdev);
672u64 pch_rx_snap_read(struct pci_dev *pdev);
673u64 pch_tx_snap_read(struct pci_dev *pdev);
674int pch_set_station_address(u8 *addr, struct pci_dev *pdev);
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677void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
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680void pch_gbe_set_ethtool_ops(struct net_device *netdev);
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683s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
684s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw);
685u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
686 u16 data);
687#endif
688