LXR linux/drivers/net/fjes/fjes

   1/*
   2 *  FUJITSU Extended Socket Network Device driver
   3 *  Copyright (c) 2015 FUJITSU LIMITED
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms and conditions of the GNU General Public License,
   7 * version 2, as published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, see <http://www.gnu.org/licenses/>.
  16 *
  17 * The full GNU General Public License is included in this distribution in
  18 * the file called "COPYING".
  19 *
  20 */
  21
  22#ifndef FJES_REGS_H_
  23#define FJES_REGS_H_
  24
  25#include <linux/bitops.h>
  26
  27#define XSCT_DEVICE_REGISTER_SIZE 0x1000
  28
  29/* register offset */
  30/* Information registers */
  31#define XSCT_OWNER_EPID     0x0000  /* Owner EPID */
  32#define XSCT_MAX_EP         0x0004  /* Maximum EP */
  33
  34/* Device Control registers */
  35#define XSCT_DCTL           0x0010  /* Device Control */
  36
  37/* Command Control registers */
  38#define XSCT_CR             0x0020  /* Command request */
  39#define XSCT_CS             0x0024  /* Command status */
  40#define XSCT_SHSTSAL        0x0028  /* Share status address Low */
  41#define XSCT_SHSTSAH        0x002C  /* Share status address High */
  42
  43#define XSCT_REQBL          0x0034  /* Request Buffer length */
  44#define XSCT_REQBAL         0x0038  /* Request Buffer Address Low */
  45#define XSCT_REQBAH         0x003C  /* Request Buffer Address High */
  46
  47#define XSCT_RESPBL         0x0044  /* Response Buffer Length */
  48#define XSCT_RESPBAL        0x0048  /* Response Buffer Address Low */
  49#define XSCT_RESPBAH        0x004C  /* Response Buffer Address High */
  50
  51/* Interrupt Control registers */
  52#define XSCT_IS             0x0080  /* Interrupt status */
  53#define XSCT_IMS            0x0084  /* Interrupt mask set */
  54#define XSCT_IMC            0x0088  /* Interrupt mask clear */
  55#define XSCT_IG             0x008C  /* Interrupt generator */
  56#define XSCT_ICTL           0x0090  /* Interrupt control */
  57
  58/* register structure */
  59/* Information registers */
  60union REG_OWNER_EPID {
  61        struct {
  62                __le32 epid:16;
  63                __le32:16;
  64        } bits;
  65        __le32 reg;
  66};
  67
  68union REG_MAX_EP {
  69        struct {
  70                __le32 maxep:16;
  71                __le32:16;
  72        } bits;
  73        __le32 reg;
  74};
  75
  76/* Device Control registers */
  77union REG_DCTL {
  78        struct {
  79                __le32 reset:1;
  80                __le32 rsv0:15;
  81                __le32 rsv1:16;
  82        } bits;
  83        __le32 reg;
  84};
  85
  86/* Command Control registers */
  87union REG_CR {
  88        struct {
  89                __le32 req_code:16;
  90                __le32 err_info:14;
  91                __le32 error:1;
  92                __le32 req_start:1;
  93        } bits;
  94        __le32 reg;
  95};
  96
  97union REG_CS {
  98        struct {
  99                __le32 req_code:16;
 100                __le32 rsv0:14;
 101                __le32 busy:1;
 102                __le32 complete:1;
 103        } bits;
 104        __le32 reg;
 105};
 106
 107/* Interrupt Control registers */
 108union REG_ICTL {
 109        struct {
 110                __le32 automak:1;
 111                __le32 rsv0:31;
 112        } bits;
 113        __le32 reg;
 114};
 115
 116enum REG_ICTL_MASK {
 117        REG_ICTL_MASK_INFO_UPDATE     = 1 << 20,
 118        REG_ICTL_MASK_DEV_STOP_REQ    = 1 << 19,
 119        REG_ICTL_MASK_TXRX_STOP_REQ   = 1 << 18,
 120        REG_ICTL_MASK_TXRX_STOP_DONE  = 1 << 17,
 121        REG_ICTL_MASK_RX_DATA         = 1 << 16,
 122        REG_ICTL_MASK_ALL             = GENMASK(20, 16),
 123};
 124
 125enum REG_IS_MASK {
 126        REG_IS_MASK_IS_ASSERT   = 1 << 31,
 127        REG_IS_MASK_EPID        = GENMASK(15, 0),
 128};
 129
 130struct fjes_hw;
 131
 132u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg);
 133
 134#define wr32(reg, val) \
 135do { \
 136        u8 *base = hw->base; \
 137        writel((val), &base[(reg)]); \
 138} while (0)
 139
 140#define rd32(reg) (fjes_hw_rd32(hw, reg))
 141
 142#endif /* FJES_REGS_H_ */
 143