linux/drivers/net/wan/n2.c
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   1/*
   2 * SDL Inc. RISCom/N2 synchronous serial card driver for Linux
   3 *
   4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License
   8 * as published by the Free Software Foundation.
   9 *
  10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
  11 *
  12 * Note: integrated CSU/DSU/DDS are not supported by this driver
  13 *
  14 * Sources of information:
  15 *    Hitachi HD64570 SCA User's Manual
  16 *    SDL Inc. PPP/HDLC/CISCO driver
  17 */
  18
  19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21#include <linux/module.h>
  22#include <linux/kernel.h>
  23#include <linux/capability.h>
  24#include <linux/slab.h>
  25#include <linux/types.h>
  26#include <linux/fcntl.h>
  27#include <linux/in.h>
  28#include <linux/string.h>
  29#include <linux/errno.h>
  30#include <linux/init.h>
  31#include <linux/ioport.h>
  32#include <linux/moduleparam.h>
  33#include <linux/netdevice.h>
  34#include <linux/hdlc.h>
  35#include <asm/io.h>
  36#include "hd64570.h"
  37
  38
  39static const char* version = "SDL RISCom/N2 driver version: 1.15";
  40static const char* devname = "RISCom/N2";
  41
  42#undef DEBUG_PKT
  43#define DEBUG_RINGS
  44
  45#define USE_WINDOWSIZE 16384
  46#define USE_BUS16BITS 1
  47#define CLOCK_BASE 9830400      /* 9.8304 MHz */
  48#define MAX_PAGES      16       /* 16 RAM pages at max */
  49#define MAX_RAM_SIZE 0x80000    /* 512 KB */
  50#if MAX_RAM_SIZE > MAX_PAGES * USE_WINDOWSIZE
  51#undef MAX_RAM_SIZE
  52#define MAX_RAM_SIZE (MAX_PAGES * USE_WINDOWSIZE)
  53#endif
  54#define N2_IOPORTS 0x10
  55#define NEED_DETECT_RAM
  56#define NEED_SCA_MSCI_INTR
  57#define MAX_TX_BUFFERS 10
  58
  59static char *hw;        /* pointer to hw=xxx command line string */
  60
  61/* RISCom/N2 Board Registers */
  62
  63/* PC Control Register */
  64#define N2_PCR 0
  65#define PCR_RUNSCA 1     /* Run 64570 */
  66#define PCR_VPM    2     /* Enable VPM - needed if using RAM above 1 MB */
  67#define PCR_ENWIN  4     /* Open window */
  68#define PCR_BUS16  8     /* 16-bit bus */
  69
  70
  71/* Memory Base Address Register */
  72#define N2_BAR 2
  73
  74
  75/* Page Scan Register  */
  76#define N2_PSR 4
  77#define WIN16K       0x00
  78#define WIN32K       0x20
  79#define WIN64K       0x40
  80#define PSR_WINBITS  0x60
  81#define PSR_DMAEN    0x80
  82#define PSR_PAGEBITS 0x0F
  83
  84
  85/* Modem Control Reg */
  86#define N2_MCR 6
  87#define CLOCK_OUT_PORT1 0x80
  88#define CLOCK_OUT_PORT0 0x40
  89#define TX422_PORT1     0x20
  90#define TX422_PORT0     0x10
  91#define DSR_PORT1       0x08
  92#define DSR_PORT0       0x04
  93#define DTR_PORT1       0x02
  94#define DTR_PORT0       0x01
  95
  96
  97typedef struct port_s {
  98        struct net_device *dev;
  99        struct card_s *card;
 100        spinlock_t lock;        /* TX lock */
 101        sync_serial_settings settings;
 102        int valid;              /* port enabled */
 103        int rxpart;             /* partial frame received, next frame invalid*/
 104        unsigned short encoding;
 105        unsigned short parity;
 106        u16 rxin;               /* rx ring buffer 'in' pointer */
 107        u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
 108        u16 txlast;
 109        u8 rxs, txs, tmc;       /* SCA registers */
 110        u8 phy_node;            /* physical port # - 0 or 1 */
 111        u8 log_node;            /* logical port # */
 112}port_t;
 113
 114
 115
 116typedef struct card_s {
 117        u8 __iomem *winbase;            /* ISA window base address */
 118        u32 phy_winbase;        /* ISA physical base address */
 119        u32 ram_size;           /* number of bytes */
 120        u16 io;                 /* IO Base address */
 121        u16 buff_offset;        /* offset of first buffer of first channel */
 122        u16 rx_ring_buffers;    /* number of buffers in a ring */
 123        u16 tx_ring_buffers;
 124        u8 irq;                 /* IRQ (3-15) */
 125
 126        port_t ports[2];
 127        struct card_s *next_card;
 128}card_t;
 129
 130
 131static card_t *first_card;
 132static card_t **new_card = &first_card;
 133
 134
 135#define sca_reg(reg, card) (0x8000 | (card)->io | \
 136                            ((reg) & 0x0F) | (((reg) & 0xF0) << 6))
 137#define sca_in(reg, card)               inb(sca_reg(reg, card))
 138#define sca_out(value, reg, card)       outb(value, sca_reg(reg, card))
 139#define sca_inw(reg, card)              inw(sca_reg(reg, card))
 140#define sca_outw(value, reg, card)      outw(value, sca_reg(reg, card))
 141
 142#define port_to_card(port)              ((port)->card)
 143#define log_node(port)                  ((port)->log_node)
 144#define phy_node(port)                  ((port)->phy_node)
 145#define winsize(card)                   (USE_WINDOWSIZE)
 146#define winbase(card)                   ((card)->winbase)
 147#define get_port(card, port)            ((card)->ports[port].valid ? \
 148                                         &(card)->ports[port] : NULL)
 149
 150
 151static __inline__ u8 sca_get_page(card_t *card)
 152{
 153        return inb(card->io + N2_PSR) & PSR_PAGEBITS;
 154}
 155
 156
 157static __inline__ void openwin(card_t *card, u8 page)
 158{
 159        u8 psr = inb(card->io + N2_PSR);
 160        outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR);
 161}
 162
 163
 164#include "hd64570.c"
 165
 166
 167static void n2_set_iface(port_t *port)
 168{
 169        card_t *card = port->card;
 170        int io = card->io;
 171        u8 mcr = inb(io + N2_MCR);
 172        u8 msci = get_msci(port);
 173        u8 rxs = port->rxs & CLK_BRG_MASK;
 174        u8 txs = port->txs & CLK_BRG_MASK;
 175
 176        switch(port->settings.clock_type) {
 177        case CLOCK_INT:
 178                mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
 179                rxs |= CLK_BRG_RX; /* BRG output */
 180                txs |= CLK_RXCLK_TX; /* RX clock */
 181                break;
 182
 183        case CLOCK_TXINT:
 184                mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
 185                rxs |= CLK_LINE_RX; /* RXC input */
 186                txs |= CLK_BRG_TX; /* BRG output */
 187                break;
 188
 189        case CLOCK_TXFROMRX:
 190                mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
 191                rxs |= CLK_LINE_RX; /* RXC input */
 192                txs |= CLK_RXCLK_TX; /* RX clock */
 193                break;
 194
 195        default:                /* Clock EXTernal */
 196                mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0;
 197                rxs |= CLK_LINE_RX; /* RXC input */
 198                txs |= CLK_LINE_TX; /* TXC input */
 199        }
 200
 201        outb(mcr, io + N2_MCR);
 202        port->rxs = rxs;
 203        port->txs = txs;
 204        sca_out(rxs, msci + RXS, card);
 205        sca_out(txs, msci + TXS, card);
 206        sca_set_port(port);
 207}
 208
 209
 210
 211static int n2_open(struct net_device *dev)
 212{
 213        port_t *port = dev_to_port(dev);
 214        int io = port->card->io;
 215        u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0);
 216        int result;
 217
 218        result = hdlc_open(dev);
 219        if (result)
 220                return result;
 221
 222        mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */
 223        outb(mcr, io + N2_MCR);
 224
 225        outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */
 226        outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */
 227        sca_open(dev);
 228        n2_set_iface(port);
 229        return 0;
 230}
 231
 232
 233
 234static int n2_close(struct net_device *dev)
 235{
 236        port_t *port = dev_to_port(dev);
 237        int io = port->card->io;
 238        u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0);
 239
 240        sca_close(dev);
 241        mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */
 242        outb(mcr, io + N2_MCR);
 243        hdlc_close(dev);
 244        return 0;
 245}
 246
 247
 248
 249static int n2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 250{
 251        const size_t size = sizeof(sync_serial_settings);
 252        sync_serial_settings new_line;
 253        sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
 254        port_t *port = dev_to_port(dev);
 255
 256#ifdef DEBUG_RINGS
 257        if (cmd == SIOCDEVPRIVATE) {
 258                sca_dump_rings(dev);
 259                return 0;
 260        }
 261#endif
 262        if (cmd != SIOCWANDEV)
 263                return hdlc_ioctl(dev, ifr, cmd);
 264
 265        switch(ifr->ifr_settings.type) {
 266        case IF_GET_IFACE:
 267                ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
 268                if (ifr->ifr_settings.size < size) {
 269                        ifr->ifr_settings.size = size; /* data size wanted */
 270                        return -ENOBUFS;
 271                }
 272                if (copy_to_user(line, &port->settings, size))
 273                        return -EFAULT;
 274                return 0;
 275
 276        case IF_IFACE_SYNC_SERIAL:
 277                if(!capable(CAP_NET_ADMIN))
 278                        return -EPERM;
 279
 280                if (copy_from_user(&new_line, line, size))
 281                        return -EFAULT;
 282
 283                if (new_line.clock_type != CLOCK_EXT &&
 284                    new_line.clock_type != CLOCK_TXFROMRX &&
 285                    new_line.clock_type != CLOCK_INT &&
 286                    new_line.clock_type != CLOCK_TXINT)
 287                        return -EINVAL; /* No such clock setting */
 288
 289                if (new_line.loopback != 0 && new_line.loopback != 1)
 290                        return -EINVAL;
 291
 292                memcpy(&port->settings, &new_line, size); /* Update settings */
 293                n2_set_iface(port);
 294                return 0;
 295
 296        default:
 297                return hdlc_ioctl(dev, ifr, cmd);
 298        }
 299}
 300
 301
 302
 303static void n2_destroy_card(card_t *card)
 304{
 305        int cnt;
 306
 307        for (cnt = 0; cnt < 2; cnt++)
 308                if (card->ports[cnt].card) {
 309                        struct net_device *dev = port_to_dev(&card->ports[cnt]);
 310                        unregister_hdlc_device(dev);
 311                }
 312
 313        if (card->irq)
 314                free_irq(card->irq, card);
 315
 316        if (card->winbase) {
 317                iounmap(card->winbase);
 318                release_mem_region(card->phy_winbase, USE_WINDOWSIZE);
 319        }
 320
 321        if (card->io)
 322                release_region(card->io, N2_IOPORTS);
 323        if (card->ports[0].dev)
 324                free_netdev(card->ports[0].dev);
 325        if (card->ports[1].dev)
 326                free_netdev(card->ports[1].dev);
 327        kfree(card);
 328}
 329
 330static const struct net_device_ops n2_ops = {
 331        .ndo_open       = n2_open,
 332        .ndo_stop       = n2_close,
 333        .ndo_start_xmit = hdlc_start_xmit,
 334        .ndo_do_ioctl   = n2_ioctl,
 335};
 336
 337static int __init n2_run(unsigned long io, unsigned long irq,
 338                         unsigned long winbase, long valid0, long valid1)
 339{
 340        card_t *card;
 341        u8 cnt, pcr;
 342        int i;
 343
 344        if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) {
 345                pr_err("invalid I/O port value\n");
 346                return -ENODEV;
 347        }
 348
 349        if (irq < 3 || irq > 15 || irq == 6) /* FIXME */ {
 350                pr_err("invalid IRQ value\n");
 351                return -ENODEV;
 352        }
 353
 354        if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) {
 355                pr_err("invalid RAM value\n");
 356                return -ENODEV;
 357        }
 358
 359        card = kzalloc(sizeof(card_t), GFP_KERNEL);
 360        if (card == NULL)
 361                return -ENOBUFS;
 362
 363        card->ports[0].dev = alloc_hdlcdev(&card->ports[0]);
 364        card->ports[1].dev = alloc_hdlcdev(&card->ports[1]);
 365        if (!card->ports[0].dev || !card->ports[1].dev) {
 366                pr_err("unable to allocate memory\n");
 367                n2_destroy_card(card);
 368                return -ENOMEM;
 369        }
 370
 371        if (!request_region(io, N2_IOPORTS, devname)) {
 372                pr_err("I/O port region in use\n");
 373                n2_destroy_card(card);
 374                return -EBUSY;
 375        }
 376        card->io = io;
 377
 378        if (request_irq(irq, sca_intr, 0, devname, card)) {
 379                pr_err("could not allocate IRQ\n");
 380                n2_destroy_card(card);
 381                return -EBUSY;
 382        }
 383        card->irq = irq;
 384
 385        if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) {
 386                pr_err("could not request RAM window\n");
 387                n2_destroy_card(card);
 388                return -EBUSY;
 389        }
 390        card->phy_winbase = winbase;
 391        card->winbase = ioremap(winbase, USE_WINDOWSIZE);
 392        if (!card->winbase) {
 393                pr_err("ioremap() failed\n");
 394                n2_destroy_card(card);
 395                return -EFAULT;
 396        }
 397
 398        outb(0, io + N2_PCR);
 399        outb(winbase >> 12, io + N2_BAR);
 400
 401        switch (USE_WINDOWSIZE) {
 402        case 16384:
 403                outb(WIN16K, io + N2_PSR);
 404                break;
 405
 406        case 32768:
 407                outb(WIN32K, io + N2_PSR);
 408                break;
 409
 410        case 65536:
 411                outb(WIN64K, io + N2_PSR);
 412                break;
 413
 414        default:
 415                pr_err("invalid window size\n");
 416                n2_destroy_card(card);
 417                return -ENODEV;
 418        }
 419
 420        pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0);
 421        outb(pcr, io + N2_PCR);
 422
 423        card->ram_size = sca_detect_ram(card, card->winbase, MAX_RAM_SIZE);
 424
 425        /* number of TX + RX buffers for one port */
 426        i = card->ram_size / ((valid0 + valid1) * (sizeof(pkt_desc) +
 427                                                   HDLC_MAX_MRU));
 428
 429        card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
 430        card->rx_ring_buffers = i - card->tx_ring_buffers;
 431
 432        card->buff_offset = (valid0 + valid1) * sizeof(pkt_desc) *
 433                (card->tx_ring_buffers + card->rx_ring_buffers);
 434
 435        pr_info("RISCom/N2 %u KB RAM, IRQ%u, using %u TX + %u RX packets rings\n",
 436                card->ram_size / 1024, card->irq,
 437                card->tx_ring_buffers, card->rx_ring_buffers);
 438
 439        if (card->tx_ring_buffers < 1) {
 440                pr_err("RAM test failed\n");
 441                n2_destroy_card(card);
 442                return -EIO;
 443        }
 444
 445        pcr |= PCR_RUNSCA;              /* run SCA */
 446        outb(pcr, io + N2_PCR);
 447        outb(0, io + N2_MCR);
 448
 449        sca_init(card, 0);
 450        for (cnt = 0; cnt < 2; cnt++) {
 451                port_t *port = &card->ports[cnt];
 452                struct net_device *dev = port_to_dev(port);
 453                hdlc_device *hdlc = dev_to_hdlc(dev);
 454
 455                if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1))
 456                        continue;
 457
 458                port->phy_node = cnt;
 459                port->valid = 1;
 460
 461                if ((cnt == 1) && valid0)
 462                        port->log_node = 1;
 463
 464                spin_lock_init(&port->lock);
 465                dev->irq = irq;
 466                dev->mem_start = winbase;
 467                dev->mem_end = winbase + USE_WINDOWSIZE - 1;
 468                dev->tx_queue_len = 50;
 469                dev->netdev_ops = &n2_ops;
 470                hdlc->attach = sca_attach;
 471                hdlc->xmit = sca_xmit;
 472                port->settings.clock_type = CLOCK_EXT;
 473                port->card = card;
 474
 475                if (register_hdlc_device(dev)) {
 476                        pr_warn("unable to register hdlc device\n");
 477                        port->card = NULL;
 478                        n2_destroy_card(card);
 479                        return -ENOBUFS;
 480                }
 481                sca_init_port(port); /* Set up SCA memory */
 482
 483                netdev_info(dev, "RISCom/N2 node %d\n", port->phy_node);
 484        }
 485
 486        *new_card = card;
 487        new_card = &card->next_card;
 488
 489        return 0;
 490}
 491
 492
 493
 494static int __init n2_init(void)
 495{
 496        if (hw==NULL) {
 497#ifdef MODULE
 498                pr_info("no card initialized\n");
 499#endif
 500                return -EINVAL; /* no parameters specified, abort */
 501        }
 502
 503        pr_info("%s\n", version);
 504
 505        do {
 506                unsigned long io, irq, ram;
 507                long valid[2] = { 0, 0 }; /* Default = both ports disabled */
 508
 509                io = simple_strtoul(hw, &hw, 0);
 510
 511                if (*hw++ != ',')
 512                        break;
 513                irq = simple_strtoul(hw, &hw, 0);
 514
 515                if (*hw++ != ',')
 516                        break;
 517                ram = simple_strtoul(hw, &hw, 0);
 518
 519                if (*hw++ != ',')
 520                        break;
 521                while(1) {
 522                        if (*hw == '0' && !valid[0])
 523                                valid[0] = 1; /* Port 0 enabled */
 524                        else if (*hw == '1' && !valid[1])
 525                                valid[1] = 1; /* Port 1 enabled */
 526                        else
 527                                break;
 528                        hw++;
 529                }
 530
 531                if (!valid[0] && !valid[1])
 532                        break;  /* at least one port must be used */
 533
 534                if (*hw == ':' || *hw == '\x0')
 535                        n2_run(io, irq, ram, valid[0], valid[1]);
 536
 537                if (*hw == '\x0')
 538                        return first_card ? 0 : -EINVAL;
 539        }while(*hw++ == ':');
 540
 541        pr_err("invalid hardware parameters\n");
 542        return first_card ? 0 : -EINVAL;
 543}
 544
 545
 546static void __exit n2_cleanup(void)
 547{
 548        card_t *card = first_card;
 549
 550        while (card) {
 551                card_t *ptr = card;
 552                card = card->next_card;
 553                n2_destroy_card(ptr);
 554        }
 555}
 556
 557
 558module_init(n2_init);
 559module_exit(n2_cleanup);
 560
 561MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 562MODULE_DESCRIPTION("RISCom/N2 serial port driver");
 563MODULE_LICENSE("GPL v2");
 564module_param(hw, charp, 0444);
 565MODULE_PARM_DESC(hw, "io,irq,ram,ports:io,irq,...");
 566