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18#ifndef _CORE_H_
19#define _CORE_H_
20
21#include <linux/completion.h>
22#include <linux/if_ether.h>
23#include <linux/types.h>
24#include <linux/pci.h>
25#include <linux/uuid.h>
26#include <linux/time.h>
27
28#include "htt.h"
29#include "htc.h"
30#include "hw.h"
31#include "targaddrs.h"
32#include "wmi.h"
33#include "../ath.h"
34#include "../regd.h"
35#include "../dfs_pattern_detector.h"
36#include "spectral.h"
37#include "thermal.h"
38#include "wow.h"
39#include "swap.h"
40
41#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
42#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
43#define WO(_f) ((_f##_OFFSET) >> 2)
44
45#define ATH10K_SCAN_ID 0
46#define WMI_READY_TIMEOUT (5 * HZ)
47#define ATH10K_FLUSH_TIMEOUT_HZ (5 * HZ)
48#define ATH10K_CONNECTION_LOSS_HZ (3 * HZ)
49#define ATH10K_NUM_CHANS 40
50
51
52#define ATH10K_DEFAULT_NOISE_FLOOR -95
53
54#define ATH10K_MAX_NUM_MGMT_PENDING 128
55
56
57#define ATH10K_KICKOUT_THRESHOLD (20 * 16)
58
59
60
61
62
63
64#define ATH10K_KEEPALIVE_MIN_IDLE 3747
65#define ATH10K_KEEPALIVE_MAX_IDLE 3895
66#define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
67
68
69#define ATH10K_NAPI_BUDGET 64
70#define ATH10K_NAPI_QUOTA_LIMIT 60
71
72
73#define ATH10K_SMBIOS_BDF_EXT_TYPE 0xF8
74
75
76#define ATH10K_SMBIOS_BDF_EXT_LENGTH 0x9
77
78
79#define ATH10K_SMBIOS_BDF_EXT_OFFSET 0x8
80
81
82
83
84#define ATH10K_SMBIOS_BDF_EXT_STR_LENGTH 0x20
85
86
87#define ATH10K_SMBIOS_BDF_EXT_MAGIC "BDF_"
88
89struct ath10k;
90
91enum ath10k_bus {
92 ATH10K_BUS_PCI,
93 ATH10K_BUS_AHB,
94};
95
96static inline const char *ath10k_bus_str(enum ath10k_bus bus)
97{
98 switch (bus) {
99 case ATH10K_BUS_PCI:
100 return "pci";
101 case ATH10K_BUS_AHB:
102 return "ahb";
103 }
104
105 return "unknown";
106}
107
108enum ath10k_skb_flags {
109 ATH10K_SKB_F_NO_HWCRYPT = BIT(0),
110 ATH10K_SKB_F_DTIM_ZERO = BIT(1),
111 ATH10K_SKB_F_DELIVER_CAB = BIT(2),
112 ATH10K_SKB_F_MGMT = BIT(3),
113 ATH10K_SKB_F_QOS = BIT(4),
114};
115
116struct ath10k_skb_cb {
117 dma_addr_t paddr;
118 u8 flags;
119 u8 eid;
120 u16 msdu_id;
121 struct ieee80211_vif *vif;
122 struct ieee80211_txq *txq;
123} __packed;
124
125struct ath10k_skb_rxcb {
126 dma_addr_t paddr;
127 struct hlist_node hlist;
128};
129
130static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
131{
132 BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
133 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
134 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
135}
136
137static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb)
138{
139 BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb));
140 return (struct ath10k_skb_rxcb *)skb->cb;
141}
142
143#define ATH10K_RXCB_SKB(rxcb) \
144 container_of((void *)rxcb, struct sk_buff, cb)
145
146static inline u32 host_interest_item_address(u32 item_offset)
147{
148 return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
149}
150
151struct ath10k_bmi {
152 bool done_sent;
153};
154
155struct ath10k_mem_chunk {
156 void *vaddr;
157 dma_addr_t paddr;
158 u32 len;
159 u32 req_id;
160};
161
162struct ath10k_wmi {
163 enum ath10k_htc_ep_id eid;
164 struct completion service_ready;
165 struct completion unified_ready;
166 struct completion barrier;
167 wait_queue_head_t tx_credits_wq;
168 DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX);
169 struct wmi_cmd_map *cmd;
170 struct wmi_vdev_param_map *vdev_param;
171 struct wmi_pdev_param_map *pdev_param;
172 const struct wmi_ops *ops;
173 const struct wmi_peer_flags_map *peer_flags;
174
175 u32 num_mem_chunks;
176 u32 rx_decap_mode;
177 struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
178};
179
180struct ath10k_fw_stats_peer {
181 struct list_head list;
182
183 u8 peer_macaddr[ETH_ALEN];
184 u32 peer_rssi;
185 u32 peer_tx_rate;
186 u32 peer_rx_rate;
187 u32 rx_duration;
188};
189
190struct ath10k_fw_extd_stats_peer {
191 struct list_head list;
192
193 u8 peer_macaddr[ETH_ALEN];
194 u32 rx_duration;
195};
196
197struct ath10k_fw_stats_vdev {
198 struct list_head list;
199
200 u32 vdev_id;
201 u32 beacon_snr;
202 u32 data_snr;
203 u32 num_tx_frames[4];
204 u32 num_rx_frames;
205 u32 num_tx_frames_retries[4];
206 u32 num_tx_frames_failures[4];
207 u32 num_rts_fail;
208 u32 num_rts_success;
209 u32 num_rx_err;
210 u32 num_rx_discard;
211 u32 num_tx_not_acked;
212 u32 tx_rate_history[10];
213 u32 beacon_rssi_history[10];
214};
215
216struct ath10k_fw_stats_pdev {
217 struct list_head list;
218
219
220 s32 ch_noise_floor;
221 u32 tx_frame_count;
222 u32 rx_frame_count;
223 u32 rx_clear_count;
224 u32 cycle_count;
225 u32 phy_err_count;
226 u32 chan_tx_power;
227 u32 ack_rx_bad;
228 u32 rts_bad;
229 u32 rts_good;
230 u32 fcs_bad;
231 u32 no_beacons;
232 u32 mib_int_count;
233
234
235 s32 comp_queued;
236 s32 comp_delivered;
237 s32 msdu_enqued;
238 s32 mpdu_enqued;
239 s32 wmm_drop;
240 s32 local_enqued;
241 s32 local_freed;
242 s32 hw_queued;
243 s32 hw_reaped;
244 s32 underrun;
245 u32 hw_paused;
246 s32 tx_abort;
247 s32 mpdus_requed;
248 u32 tx_ko;
249 u32 data_rc;
250 u32 self_triggers;
251 u32 sw_retry_failure;
252 u32 illgl_rate_phy_err;
253 u32 pdev_cont_xretry;
254 u32 pdev_tx_timeout;
255 u32 pdev_resets;
256 u32 phy_underrun;
257 u32 txop_ovf;
258 u32 seq_posted;
259 u32 seq_failed_queueing;
260 u32 seq_completed;
261 u32 seq_restarted;
262 u32 mu_seq_posted;
263 u32 mpdus_sw_flush;
264 u32 mpdus_hw_filter;
265 u32 mpdus_truncated;
266 u32 mpdus_ack_failed;
267 u32 mpdus_expired;
268
269
270 s32 mid_ppdu_route_change;
271 s32 status_rcvd;
272 s32 r0_frags;
273 s32 r1_frags;
274 s32 r2_frags;
275 s32 r3_frags;
276 s32 htt_msdus;
277 s32 htt_mpdus;
278 s32 loc_msdus;
279 s32 loc_mpdus;
280 s32 oversize_amsdu;
281 s32 phy_errs;
282 s32 phy_err_drop;
283 s32 mpdu_errs;
284 s32 rx_ovfl_errs;
285};
286
287struct ath10k_fw_stats {
288 bool extended;
289 struct list_head pdevs;
290 struct list_head vdevs;
291 struct list_head peers;
292 struct list_head peers_extd;
293};
294
295#define ATH10K_TPC_TABLE_TYPE_FLAG 1
296#define ATH10K_TPC_PREAM_TABLE_END 0xFFFF
297
298struct ath10k_tpc_table {
299 u32 pream_idx[WMI_TPC_RATE_MAX];
300 u8 rate_code[WMI_TPC_RATE_MAX];
301 char tpc_value[WMI_TPC_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
302};
303
304struct ath10k_tpc_stats {
305 u32 reg_domain;
306 u32 chan_freq;
307 u32 phy_mode;
308 u32 twice_antenna_reduction;
309 u32 twice_max_rd_power;
310 s32 twice_antenna_gain;
311 u32 power_limit;
312 u32 num_tx_chain;
313 u32 ctl;
314 u32 rate_max;
315 u8 flag[WMI_TPC_FLAG];
316 struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG];
317};
318
319struct ath10k_dfs_stats {
320 u32 phy_errors;
321 u32 pulses_total;
322 u32 pulses_detected;
323 u32 pulses_discarded;
324 u32 radar_detected;
325};
326
327#define ATH10K_MAX_NUM_PEER_IDS (1 << 11)
328
329struct ath10k_peer {
330 struct list_head list;
331 struct ieee80211_vif *vif;
332 struct ieee80211_sta *sta;
333
334 bool removed;
335 int vdev_id;
336 u8 addr[ETH_ALEN];
337 DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
338
339
340 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
341};
342
343struct ath10k_txq {
344 struct list_head list;
345 unsigned long num_fw_queued;
346 unsigned long num_push_allowed;
347};
348
349struct ath10k_sta {
350 struct ath10k_vif *arvif;
351
352
353 u32 changed;
354 u32 bw;
355 u32 nss;
356 u32 smps;
357 u16 peer_id;
358 struct rate_info txrate;
359
360 struct work_struct update_wk;
361
362#ifdef CONFIG_MAC80211_DEBUGFS
363
364 bool aggr_mode;
365 u64 rx_duration;
366#endif
367};
368
369#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ)
370
371enum ath10k_beacon_state {
372 ATH10K_BEACON_SCHEDULED = 0,
373 ATH10K_BEACON_SENDING,
374 ATH10K_BEACON_SENT,
375};
376
377struct ath10k_vif {
378 struct list_head list;
379
380 u32 vdev_id;
381 u16 peer_id;
382 enum wmi_vdev_type vdev_type;
383 enum wmi_vdev_subtype vdev_subtype;
384 u32 beacon_interval;
385 u32 dtim_period;
386 struct sk_buff *beacon;
387
388 enum ath10k_beacon_state beacon_state;
389 void *beacon_buf;
390 dma_addr_t beacon_paddr;
391 unsigned long tx_paused;
392
393 struct ath10k *ar;
394 struct ieee80211_vif *vif;
395
396 bool is_started;
397 bool is_up;
398 bool spectral_enabled;
399 bool ps;
400 u32 aid;
401 u8 bssid[ETH_ALEN];
402
403 struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
404 s8 def_wep_key_idx;
405
406 u16 tx_seq_no;
407
408 union {
409 struct {
410 u32 uapsd;
411 } sta;
412 struct {
413
414 u8 tim_bitmap[64];
415 u8 tim_len;
416 u32 ssid_len;
417 u8 ssid[IEEE80211_MAX_SSID_LEN];
418 bool hidden_ssid;
419
420 u32 noa_len;
421 u8 *noa_data;
422 } ap;
423 } u;
424
425 bool use_cts_prot;
426 bool nohwcrypt;
427 int num_legacy_stations;
428 int txpower;
429 struct wmi_wmm_params_all_arg wmm_params;
430 struct work_struct ap_csa_work;
431 struct delayed_work connection_loss_work;
432 struct cfg80211_bitrate_mask bitrate_mask;
433};
434
435struct ath10k_vif_iter {
436 u32 vdev_id;
437 struct ath10k_vif *arvif;
438};
439
440
441struct ath10k_ce_crash_data {
442 __le32 base_addr;
443 __le32 src_wr_idx;
444 __le32 src_r_idx;
445 __le32 dst_wr_idx;
446 __le32 dst_r_idx;
447};
448
449struct ath10k_ce_crash_hdr {
450 __le32 ce_count;
451 __le32 reserved[3];
452 struct ath10k_ce_crash_data entries[];
453};
454
455
456struct ath10k_fw_crash_data {
457 bool crashed_since_read;
458
459 uuid_le uuid;
460 struct timespec timestamp;
461 __le32 registers[REG_DUMP_COUNT_QCA988X];
462 struct ath10k_ce_crash_data ce_crash_data[CE_COUNT_MAX];
463};
464
465struct ath10k_debug {
466 struct dentry *debugfs_phy;
467
468 struct ath10k_fw_stats fw_stats;
469 struct completion fw_stats_complete;
470 bool fw_stats_done;
471
472 unsigned long htt_stats_mask;
473 struct delayed_work htt_stats_dwork;
474 struct ath10k_dfs_stats dfs_stats;
475 struct ath_dfs_pool_stats dfs_pool_stats;
476
477
478 struct ath10k_tpc_stats *tpc_stats;
479
480 struct completion tpc_complete;
481
482
483 u64 fw_dbglog_mask;
484 u32 fw_dbglog_level;
485 u32 pktlog_filter;
486 u32 reg_addr;
487 u32 nf_cal_period;
488 void *cal_data;
489
490 struct ath10k_fw_crash_data *fw_crash_data;
491};
492
493enum ath10k_state {
494 ATH10K_STATE_OFF = 0,
495 ATH10K_STATE_ON,
496
497
498
499
500
501
502
503
504
505
506 ATH10K_STATE_RESTARTING,
507 ATH10K_STATE_RESTARTED,
508
509
510
511
512
513
514 ATH10K_STATE_WEDGED,
515
516
517 ATH10K_STATE_UTF,
518};
519
520enum ath10k_firmware_mode {
521
522 ATH10K_FIRMWARE_MODE_NORMAL,
523
524
525 ATH10K_FIRMWARE_MODE_UTF,
526};
527
528enum ath10k_fw_features {
529
530 ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
531
532
533 ATH10K_FW_FEATURE_WMI_10X = 1,
534
535
536 ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
537
538
539 ATH10K_FW_FEATURE_NO_P2P = 3,
540
541
542
543
544
545 ATH10K_FW_FEATURE_WMI_10_2 = 4,
546
547
548
549
550
551 ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5,
552
553
554
555
556
557 ATH10K_FW_FEATURE_WOWLAN_SUPPORT = 6,
558
559
560 ATH10K_FW_FEATURE_IGNORE_OTP_RESULT = 7,
561
562
563
564
565 ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING = 8,
566
567
568 ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9,
569
570
571
572
573 ATH10K_FW_FEATURE_RAW_MODE_SUPPORT = 10,
574
575
576 ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11,
577
578
579 ATH10K_FW_FEATURE_MFP_SUPPORT = 12,
580
581
582
583
584
585
586
587
588 ATH10K_FW_FEATURE_PEER_FLOW_CONTROL = 13,
589
590
591
592
593
594
595 ATH10K_FW_FEATURE_BTCOEX_PARAM = 14,
596
597
598
599
600 ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR = 15,
601
602
603
604
605
606
607 ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST = 16,
608
609
610 ATH10K_FW_FEATURE_COUNT,
611};
612
613enum ath10k_dev_flags {
614
615 ATH10K_CAC_RUNNING,
616 ATH10K_FLAG_CORE_REGISTERED,
617
618
619
620
621 ATH10K_FLAG_CRASH_FLUSH,
622
623
624
625
626
627 ATH10K_FLAG_RAW_MODE,
628
629
630 ATH10K_FLAG_HW_CRYPTO_DISABLED,
631
632
633 ATH10K_FLAG_BTCOEX,
634
635
636 ATH10K_FLAG_PEER_STATS,
637};
638
639enum ath10k_cal_mode {
640 ATH10K_CAL_MODE_FILE,
641 ATH10K_CAL_MODE_OTP,
642 ATH10K_CAL_MODE_DT,
643 ATH10K_PRE_CAL_MODE_FILE,
644 ATH10K_PRE_CAL_MODE_DT,
645 ATH10K_CAL_MODE_EEPROM,
646};
647
648enum ath10k_crypt_mode {
649
650 ATH10K_CRYPT_MODE_HW,
651
652 ATH10K_CRYPT_MODE_SW,
653};
654
655static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode)
656{
657 switch (mode) {
658 case ATH10K_CAL_MODE_FILE:
659 return "file";
660 case ATH10K_CAL_MODE_OTP:
661 return "otp";
662 case ATH10K_CAL_MODE_DT:
663 return "dt";
664 case ATH10K_PRE_CAL_MODE_FILE:
665 return "pre-cal-file";
666 case ATH10K_PRE_CAL_MODE_DT:
667 return "pre-cal-dt";
668 case ATH10K_CAL_MODE_EEPROM:
669 return "eeprom";
670 }
671
672 return "unknown";
673}
674
675enum ath10k_scan_state {
676 ATH10K_SCAN_IDLE,
677 ATH10K_SCAN_STARTING,
678 ATH10K_SCAN_RUNNING,
679 ATH10K_SCAN_ABORTING,
680};
681
682static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
683{
684 switch (state) {
685 case ATH10K_SCAN_IDLE:
686 return "idle";
687 case ATH10K_SCAN_STARTING:
688 return "starting";
689 case ATH10K_SCAN_RUNNING:
690 return "running";
691 case ATH10K_SCAN_ABORTING:
692 return "aborting";
693 }
694
695 return "unknown";
696}
697
698enum ath10k_tx_pause_reason {
699 ATH10K_TX_PAUSE_Q_FULL,
700 ATH10K_TX_PAUSE_MAX,
701};
702
703struct ath10k_fw_file {
704 const struct firmware *firmware;
705
706 char fw_version[ETHTOOL_FWVERS_LEN];
707
708 DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
709
710 enum ath10k_fw_wmi_op_version wmi_op_version;
711 enum ath10k_fw_htt_op_version htt_op_version;
712
713 const void *firmware_data;
714 size_t firmware_len;
715
716 const void *otp_data;
717 size_t otp_len;
718
719 const void *codeswap_data;
720 size_t codeswap_len;
721
722
723
724
725
726
727
728
729 struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info;
730};
731
732struct ath10k_fw_components {
733 const struct firmware *board;
734 const void *board_data;
735 size_t board_len;
736
737 struct ath10k_fw_file fw_file;
738};
739
740struct ath10k_per_peer_tx_stats {
741 u32 succ_bytes;
742 u32 retry_bytes;
743 u32 failed_bytes;
744 u8 ratecode;
745 u8 flags;
746 u16 peer_id;
747 u16 succ_pkts;
748 u16 retry_pkts;
749 u16 failed_pkts;
750 u16 duration;
751 u32 reserved1;
752 u32 reserved2;
753};
754
755struct ath10k {
756 struct ath_common ath_common;
757 struct ieee80211_hw *hw;
758 struct ieee80211_ops *ops;
759 struct device *dev;
760 u8 mac_addr[ETH_ALEN];
761
762 enum ath10k_hw_rev hw_rev;
763 u16 dev_id;
764 u32 chip_id;
765 u32 target_version;
766 u8 fw_version_major;
767 u32 fw_version_minor;
768 u16 fw_version_release;
769 u16 fw_version_build;
770 u32 fw_stats_req_mask;
771 u32 phy_capability;
772 u32 hw_min_tx_power;
773 u32 hw_max_tx_power;
774 u32 hw_eeprom_rd;
775 u32 ht_cap_info;
776 u32 vht_cap_info;
777 u32 num_rf_chains;
778 u32 max_spatial_stream;
779
780 u32 low_5ghz_chan;
781 u32 high_5ghz_chan;
782 bool ani_enabled;
783
784 bool p2p;
785
786 struct {
787 enum ath10k_bus bus;
788 const struct ath10k_hif_ops *ops;
789 } hif;
790
791 struct completion target_suspend;
792
793 const struct ath10k_hw_regs *regs;
794 const struct ath10k_hw_values *hw_values;
795 struct ath10k_bmi bmi;
796 struct ath10k_wmi wmi;
797 struct ath10k_htc htc;
798 struct ath10k_htt htt;
799
800 struct ath10k_hw_params hw_params;
801
802
803 struct ath10k_fw_components normal_mode_fw;
804
805
806
807
808 const struct ath10k_fw_components *running_fw;
809
810 const struct firmware *pre_cal_file;
811 const struct firmware *cal_file;
812
813 struct {
814 u32 vendor;
815 u32 device;
816 u32 subsystem_vendor;
817 u32 subsystem_device;
818
819 bool bmi_ids_valid;
820 u8 bmi_board_id;
821 u8 bmi_chip_id;
822
823 char bdf_ext[ATH10K_SMBIOS_BDF_EXT_STR_LENGTH];
824 } id;
825
826 int fw_api;
827 int bd_api;
828 enum ath10k_cal_mode cal_mode;
829
830 struct {
831 struct completion started;
832 struct completion completed;
833 struct completion on_channel;
834 struct delayed_work timeout;
835 enum ath10k_scan_state state;
836 bool is_roc;
837 int vdev_id;
838 int roc_freq;
839 bool roc_notify;
840 } scan;
841
842 struct {
843 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
844 } mac;
845
846
847 struct ieee80211_channel *rx_channel;
848
849
850 struct ieee80211_channel *scan_channel;
851
852
853 struct cfg80211_chan_def chandef;
854
855
856 struct ieee80211_channel *tgt_oper_chan;
857
858 unsigned long long free_vdev_map;
859 struct ath10k_vif *monitor_arvif;
860 bool monitor;
861 int monitor_vdev_id;
862 bool monitor_started;
863 unsigned int filter_flags;
864 unsigned long dev_flags;
865 bool dfs_block_radar_events;
866
867
868 bool radar_enabled;
869 int num_started_vdevs;
870
871
872 u8 cfg_tx_chainmask;
873 u8 cfg_rx_chainmask;
874
875 struct completion install_key_done;
876
877 struct completion vdev_setup_done;
878
879 struct workqueue_struct *workqueue;
880
881 struct workqueue_struct *workqueue_aux;
882
883
884 struct mutex conf_mutex;
885
886
887 spinlock_t data_lock;
888
889 spinlock_t txqs_lock;
890
891 struct list_head txqs;
892 struct list_head arvifs;
893 struct list_head peers;
894 struct ath10k_peer *peer_map[ATH10K_MAX_NUM_PEER_IDS];
895 wait_queue_head_t peer_mapping_wq;
896
897
898 int num_peers;
899 int num_stations;
900
901 int max_num_peers;
902 int max_num_stations;
903 int max_num_vdevs;
904 int max_num_tdls_vdevs;
905 int num_active_peers;
906 int num_tids;
907
908 struct work_struct svc_rdy_work;
909 struct sk_buff *svc_rdy_skb;
910
911 struct work_struct offchan_tx_work;
912 struct sk_buff_head offchan_tx_queue;
913 struct completion offchan_tx_completed;
914 struct sk_buff *offchan_tx_skb;
915
916 struct work_struct wmi_mgmt_tx_work;
917 struct sk_buff_head wmi_mgmt_tx_queue;
918
919 enum ath10k_state state;
920
921 struct work_struct register_work;
922 struct work_struct restart_work;
923
924
925
926
927 u32 survey_last_rx_clear_count;
928 u32 survey_last_cycle_count;
929 struct survey_info survey[ATH10K_NUM_CHANS];
930
931
932
933
934
935
936
937 bool ch_info_can_report_survey;
938 struct completion bss_survey_done;
939
940 struct dfs_pattern_detector *dfs_detector;
941
942 unsigned long tx_paused;
943
944#ifdef CONFIG_ATH10K_DEBUGFS
945 struct ath10k_debug debug;
946 struct {
947
948 struct rchan *rfs_chan_spec_scan;
949
950
951 enum ath10k_spectral_mode mode;
952 struct ath10k_spec_scan config;
953 } spectral;
954#endif
955
956 struct {
957
958 struct ath10k_fw_components utf_mode_fw;
959
960
961 bool utf_monitor;
962 } testmode;
963
964 struct {
965
966 u32 fw_crash_counter;
967 u32 fw_warm_reset_counter;
968 u32 fw_cold_reset_counter;
969 } stats;
970
971 struct ath10k_thermal thermal;
972 struct ath10k_wow wow;
973 struct ath10k_per_peer_tx_stats peer_tx_stats;
974
975
976 struct net_device napi_dev;
977 struct napi_struct napi;
978
979 struct work_struct set_coverage_class_work;
980
981 struct {
982
983 s16 coverage_class;
984
985 u32 reg_phyclk;
986 u32 reg_slottime_conf;
987 u32 reg_slottime_orig;
988 u32 reg_ack_cts_timeout_conf;
989 u32 reg_ack_cts_timeout_orig;
990 } fw_coverage;
991
992
993 u8 drv_priv[0] __aligned(sizeof(void *));
994};
995
996static inline bool ath10k_peer_stats_enabled(struct ath10k *ar)
997{
998 if (test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags) &&
999 test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map))
1000 return true;
1001
1002 return false;
1003}
1004
1005struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
1006 enum ath10k_bus bus,
1007 enum ath10k_hw_rev hw_rev,
1008 const struct ath10k_hif_ops *hif_ops);
1009void ath10k_core_destroy(struct ath10k *ar);
1010void ath10k_core_get_fw_features_str(struct ath10k *ar,
1011 char *buf,
1012 size_t max_len);
1013int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
1014 struct ath10k_fw_file *fw_file);
1015
1016int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
1017 const struct ath10k_fw_components *fw_components);
1018int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
1019void ath10k_core_stop(struct ath10k *ar);
1020int ath10k_core_register(struct ath10k *ar, u32 chip_id);
1021void ath10k_core_unregister(struct ath10k *ar);
1022
1023#endif
1024