1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26#ifndef __RTL8821AE_REG_H__ 27#define __RTL8821AE_REG_H__ 28 29#define TXPKT_BUF_SELECT 0x69 30#define RXPKT_BUF_SELECT 0xA5 31#define DISABLE_TRXPKT_BUF_ACCESS 0x0 32 33#define REG_SYS_ISO_CTRL 0x0000 34#define REG_SYS_FUNC_EN 0x0002 35#define REG_APS_FSMCO 0x0004 36#define REG_SYS_CLKR 0x0008 37#define REG_9346CR 0x000A 38#define REG_EE_VPD 0x000C 39#define REG_AFE_MISC 0x0010 40#define REG_SPS0_CTRL 0x0011 41#define REG_SPS_OCP_CFG 0x0018 42#define REG_RSV_CTRL 0x001C 43#define REG_RF_CTRL 0x001F 44#define REG_LDOA15_CTRL 0x0020 45#define REG_LDOV12D_CTRL 0x0021 46#define REG_LDOHCI12_CTRL 0x0022 47#define REG_LPLDO_CTRL 0x0023 48#define REG_AFE_XTAL_CTRL 0x0024 49 /* 1.5v for 8188EE test chip, 1.4v for MP chip */ 50#define REG_AFE_LDO_CTRL 0x0027 51#define REG_AFE_PLL_CTRL 0x0028 52#define REG_MAC_PHY_CTRL 0x002c 53#define REG_EFUSE_CTRL 0x0030 54#define REG_EFUSE_TEST 0x0034 55#define REG_PWR_DATA 0x0038 56#define REG_CAL_TIMER 0x003C 57#define REG_ACLK_MON 0x003E 58#define REG_GPIO_MUXCFG 0x0040 59#define REG_GPIO_IO_SEL 0x0042 60#define REG_MAC_PINMUX_CFG 0x0043 61#define REG_GPIO_PIN_CTRL 0x0044 62#define REG_GPIO_INTM 0x0048 63#define REG_LEDCFG0 0x004C 64#define REG_LEDCFG1 0x004D 65#define REG_LEDCFG2 0x004E 66#define REG_LEDCFG3 0x004F 67#define REG_FSIMR 0x0050 68#define REG_FSISR 0x0054 69#define REG_HSIMR 0x0058 70#define REG_HSISR 0x005c 71#define REG_GPIO_PIN_CTRL_2 0x0060 72#define REG_GPIO_IO_SEL_2 0x0062 73#define REG_MULTI_FUNC_CTRL 0x0068 74#define REG_GPIO_OUTPUT 0x006c 75#define REG_OPT_CTRL 0x0074 76#define REG_AFE_XTAL_CTRL_EXT 0x0078 77#define REG_XCK_OUT_CTRL 0x007c 78#define REG_MCUFWDL 0x0080 79#define REG_WOL_EVENT 0x0081 80#define REG_MCUTSTCFG 0x0084 81 82#define REG_HIMR 0x00B0 83#define REG_HISR 0x00B4 84#define REG_HIMRE 0x00B8 85#define REG_HISRE 0x00BC 86 87#define REG_PMC_DBG_CTRL2 0x00CC 88 89#define REG_EFUSE_ACCESS 0x00CF 90 91#define REG_BIST_SCAN 0x00D0 92#define REG_BIST_RPT 0x00D4 93#define REG_BIST_ROM_RPT 0x00D8 94#define REG_USB_SIE_INTF 0x00E0 95#define REG_PCIE_MIO_INTF 0x00E4 96#define REG_PCIE_MIO_INTD 0x00E8 97#define REG_HPON_FSM 0x00EC 98#define REG_SYS_CFG 0x00F0 99#define REG_GPIO_OUTSTS 0x00F4 100#define REG_MAC_PHY_CTRL_NORMAL 0x00F8 101#define REG_SYS_CFG1 0x00FC 102#define REG_ROM_VERSION 0x00FD 103 104#define REG_CR 0x0100 105#define REG_PBP 0x0104 106#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 107#define REG_TRXDMA_CTRL 0x010C 108#define REG_TRXFF_BNDY 0x0114 109#define REG_TRXFF_STATUS 0x0118 110#define REG_RXFF_PTR 0x011C 111 112#define REG_CPWM 0x012F 113#define REG_FWIMR 0x0130 114#define REG_FWISR 0x0134 115#define REG_FTISR 0x013C 116#define REG_PKTBUF_DBG_CTRL 0x0140 117#define REG_PKTBUF_DBG_DATA_L 0x0144 118#define REG_PKTBUF_DBG_DATA_H 0x0148 119#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) 120 121#define REG_TC0_CTRL 0x0150 122#define REG_TC1_CTRL 0x0154 123#define REG_TC2_CTRL 0x0158 124#define REG_TC3_CTRL 0x015C 125#define REG_TC4_CTRL 0x0160 126#define REG_TCUNIT_BASE 0x0164 127#define REG_MBIST_START 0x0174 128#define REG_MBIST_DONE 0x0178 129#define REG_MBIST_FAIL 0x017C 130#define REG_32K_CTRL 0x0194 131#define REG_C2HEVT_MSG_NORMAL 0x01A0 132#define REG_C2HEVT_CLEAR 0x01AF 133#define REG_C2HEVT_MSG_TEST 0x01B8 134#define REG_MCUTST_1 0x01c0 135#define REG_MCUTST_WOWLAN 0x01C7 136#define REG_FMETHR 0x01C8 137#define REG_HMETFR 0x01CC 138#define REG_HMEBOX_0 0x01D0 139#define REG_HMEBOX_1 0x01D4 140#define REG_HMEBOX_2 0x01D8 141#define REG_HMEBOX_3 0x01DC 142 143#define REG_LLT_INIT 0x01E0 144#define REG_BB_ACCEESS_CTRL 0x01E8 145#define REG_BB_ACCESS_DATA 0x01EC 146 147#define REG_HMEBOX_EXT_0 0x01F0 148#define REG_HMEBOX_EXT_1 0x01F4 149#define REG_HMEBOX_EXT_2 0x01F8 150#define REG_HMEBOX_EXT_3 0x01FC 151 152#define REG_RQPN 0x0200 153#define REG_FIFOPAGE 0x0204 154#define REG_TDECTRL 0x0208 155#define REG_TXDMA_OFFSET_CHK 0x020C 156#define REG_TXDMA_STATUS 0x0210 157#define REG_RQPN_NPQ 0x0214 158 159#define REG_RXDMA_AGG_PG_TH 0x0280 160 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 161#define REG_FW_UPD_RDPTR 0x0284 162 /* Control the RX DMA.*/ 163#define REG_RXDMA_CONTROL 0x0286 164/* The number of packets in RXPKTBUF. */ 165#define REG_RXPKT_NUM 0x0287 166 167#define REG_PCIE_CTRL_REG 0x0300 168#define REG_INT_MIG 0x0304 169#define REG_BCNQ_DESA 0x0308 170#define REG_HQ_DESA 0x0310 171#define REG_MGQ_DESA 0x0318 172#define REG_VOQ_DESA 0x0320 173#define REG_VIQ_DESA 0x0328 174#define REG_BEQ_DESA 0x0330 175#define REG_BKQ_DESA 0x0338 176#define REG_RX_DESA 0x0340 177 178#define REG_DBI_WDATA 0x0348 179#define REG_DBI_RDATA 0x034C 180#define REG_DBI_CTRL 0x0350 181#define REG_DBI_ADDR 0x0350 182#define REG_DBI_FLAG 0x0352 183#define REG_MDIO_WDATA 0x0354 184#define REG_MDIO_RDATA 0x0356 185#define REG_MDIO_CTL 0x0358 186#define REG_DBG_SEL 0x0360 187#define REG_PCIE_HRPWM 0x0361 188#define REG_PCIE_HCPWM 0x0363 189#define REG_UART_CTRL 0x0364 190#define REG_WATCH_DOG 0x0368 191#define REG_UART_TX_DESA 0x0370 192#define REG_UART_RX_DESA 0x0378 193 194#define REG_HDAQ_DESA_NODEF 0x0000 195#define REG_CMDQ_DESA_NODEF 0x0000 196 197#define REG_VOQ_INFORMATION 0x0400 198#define REG_VIQ_INFORMATION 0x0404 199#define REG_BEQ_INFORMATION 0x0408 200#define REG_BKQ_INFORMATION 0x040C 201#define REG_MGQ_INFORMATION 0x0410 202#define REG_HGQ_INFORMATION 0x0414 203#define REG_BCNQ_INFORMATION 0x0418 204#define REG_TXPKT_EMPTY 0x041A 205 206#define REG_CPU_MGQ_INFORMATION 0x041C 207#define REG_FWHW_TXQ_CTRL 0x0420 208#define REG_HWSEQ_CTRL 0x0423 209#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 210#define REG_TXPKTBUF_MGQ_BDNY 0x0425 211#define REG_MULTI_BCNQ_EN 0x0426 212#define REG_MULTI_BCNQ_OFFSET 0x0427 213#define REG_SPEC_SIFS 0x0428 214#define REG_RL 0x042A 215#define REG_DARFRC 0x0430 216#define REG_RARFRC 0x0438 217#define REG_RRSR 0x0440 218#define REG_ARFR0 0x0444 219#define REG_ARFR1 0x044C 220#define REG_CCK_CHECK 0x0454 221#define REG_AMPDU_MAX_TIME 0x0456 222#define REG_AGGLEN_LMT 0x0458 223#define REG_AMPDU_MIN_SPACE 0x045C 224#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 225#define REG_FAST_EDCA_CTRL 0x0460 226#define REG_RD_RESP_PKT_TH 0x0463 227#define REG_INIRTS_RATE_SEL 0x0480 228#define REG_INIDATA_RATE_SEL 0x0484 229#define REG_ARFR2 0x048C 230#define REG_ARFR3 0x0494 231#define REG_POWER_STATUS 0x04A4 232#define REG_POWER_STAGE1 0x04B4 233#define REG_POWER_STAGE2 0x04B8 234#define REG_PKT_LIFE_TIME 0x04C0 235#define REG_STBC_SETTING 0x04C4 236#define REG_HT_SINGLE_AMPDU 0x04C7 237#define REG_PROT_MODE_CTRL 0x04C8 238#define REG_MAX_AGGR_NUM 0x04CA 239#define REG_BAR_MODE_CTRL 0x04CC 240#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 241#define REG_EARLY_MODE_CONTROL 0x04D0 242#define REG_NQOS_SEQ 0x04DC 243#define REG_QOS_SEQ 0x04DE 244#define REG_NEED_CPU_HANDLE 0x04E0 245#define REG_PKT_LOSE_RPT 0x04E1 246#define REG_PTCL_ERR_STATUS 0x04E2 247#define REG_TX_RPT_CTRL 0x04EC 248#define REG_TX_RPT_TIME 0x04F0 249#define REG_DUMMY 0x04FC 250 251#define REG_EDCA_VO_PARAM 0x0500 252#define REG_EDCA_VI_PARAM 0x0504 253#define REG_EDCA_BE_PARAM 0x0508 254#define REG_EDCA_BK_PARAM 0x050C 255#define REG_BCNTCFG 0x0510 256#define REG_PIFS 0x0512 257#define REG_RDG_PIFS 0x0513 258#define REG_SIFS_CTX 0x0514 259#define REG_SIFS_TRX 0x0516 260#define REG_AGGR_BREAK_TIME 0x051A 261#define REG_SLOT 0x051B 262#define REG_TX_PTCL_CTRL 0x0520 263#define REG_TXPAUSE 0x0522 264#define REG_DIS_TXREQ_CLR 0x0523 265#define REG_RD_CTRL 0x0524 266#define REG_TBTT_PROHIBIT 0x0540 267#define REG_RD_NAV_NXT 0x0544 268#define REG_NAV_PROT_LEN 0x0546 269#define REG_BCN_CTRL 0x0550 270#define REG_USTIME_TSF 0x0551 271#define REG_MBID_NUM 0x0552 272#define REG_DUAL_TSF_RST 0x0553 273#define REG_BCN_INTERVAL 0x0554 274#define REG_MBSSID_BCN_SPACE 0x0554 275#define REG_DRVERLYINT 0x0558 276#define REG_BCNDMATIM 0x0559 277#define REG_ATIMWND 0x055A 278#define REG_BCN_MAX_ERR 0x055D 279#define REG_RXTSF_OFFSET_CCK 0x055E 280#define REG_RXTSF_OFFSET_OFDM 0x055F 281#define REG_TSFTR 0x0560 282#define REG_INIT_TSFTR 0x0564 283#define REG_SECONDARY_CCA_CTRL 0x0577 284#define REG_PSTIMER 0x0580 285#define REG_TIMER0 0x0584 286#define REG_TIMER1 0x0588 287#define REG_ACMHWCTRL 0x05C0 288#define REG_ACMRSTCTRL 0x05C1 289#define REG_ACMAVG 0x05C2 290#define REG_VO_ADMTIME 0x05C4 291#define REG_VI_ADMTIME 0x05C6 292#define REG_BE_ADMTIME 0x05C8 293#define REG_EDCA_RANDOM_GEN 0x05CC 294#define REG_NOA_DESC_SEL 0x05CF 295#define REG_NOA_DESC_DURATION 0x05E0 296#define REG_NOA_DESC_INTERVAL 0x05E4 297#define REG_NOA_DESC_START 0x05E8 298#define REG_NOA_DESC_COUNT 0x05EC 299#define REG_SCH_TXCMD 0x05F8 300 301#define REG_APSD_CTRL 0x0600 302#define REG_BWOPMODE 0x0603 303#define REG_TCR 0x0604 304#define REG_RCR 0x0608 305#define REG_RX_PKT_LIMIT 0x060C 306#define REG_RX_DLK_TIME 0x060D 307#define REG_RX_DRVINFO_SZ 0x060F 308 309#define REG_MACID 0x0610 310#define REG_BSSID 0x0618 311#define REG_MAR 0x0620 312#define REG_MBIDCAMCFG 0x0628 313 314#define REG_USTIME_EDCA 0x0638 315#define REG_MAC_SPEC_SIFS 0x063A 316#define REG_RESP_SIFS_CCK 0x063C 317#define REG_RESP_SIFS_OFDM 0x063E 318#define REG_ACKTO 0x0640 319#define REG_CTS2TO 0x0641 320#define REG_EIFS 0x0642 321 322#define REG_NAV_CTRL 0x0650 323#define REG_NAV_UPPER 0x0652 324#define REG_BACAMCMD 0x0654 325#define REG_BACAMCONTENT 0x0658 326#define REG_LBDLY 0x0660 327#define REG_FWDLY 0x0661 328#define REG_RXERR_RPT 0x0664 329#define REG_TRXPTCL_CTL 0x0668 330 331#define REG_CAMCMD 0x0670 332#define REG_CAMWRITE 0x0674 333#define REG_CAMREAD 0x0678 334#define REG_CAMDBG 0x067C 335#define REG_SECCFG 0x0680 336 337#define REG_WOW_CTRL 0x0690 338#define REG_PSSTATUS 0x0691 339#define REG_PS_RX_INFO 0x0692 340#define REG_UAPSD_TID 0x0693 341#define REG_LPNAV_CTRL 0x0694 342#define REG_WKFMCAM_NUM 0x0698 343#define REG_WKFMCAM_RWD 0x069C 344#define REG_RXFLTMAP0 0x06A0 345#define REG_RXFLTMAP1 0x06A2 346#define REG_RXFLTMAP2 0x06A4 347#define REG_BCN_PSR_RPT 0x06A8 348#define REG_CALB32K_CTRL 0x06AC 349#define REG_PKT_MON_CTRL 0x06B4 350#define REG_BT_COEX_TABLE 0x06C0 351#define REG_WMAC_RESP_TXINFO 0x06D8 352 353#define REG_USB_INFO 0xFE17 354#define REG_USB_SPECIAL_OPTION 0xFE55 355#define REG_USB_DMA_AGG_TO 0xFE5B 356#define REG_USB_AGG_TO 0xFE5C 357#define REG_USB_AGG_TH 0xFE5D 358 359#define REG_TEST_USB_TXQS 0xFE48 360#define REG_TEST_SIE_VID 0xFE60 361#define REG_TEST_SIE_PID 0xFE62 362#define REG_TEST_SIE_OPTIONAL 0xFE64 363#define REG_TEST_SIE_CHIRP_K 0xFE65 364#define REG_TEST_SIE_PHY 0xFE66 365#define REG_TEST_SIE_MAC_ADDR 0xFE70 366#define REG_TEST_SIE_STRING 0xFE80 367 368#define REG_NORMAL_SIE_VID 0xFE60 369#define REG_NORMAL_SIE_PID 0xFE62 370#define REG_NORMAL_SIE_OPTIONAL 0xFE64 371#define REG_NORMAL_SIE_EP 0xFE65 372#define REG_NORMAL_SIE_PHY 0xFE68 373#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 374#define REG_NORMAL_SIE_STRING 0xFE80 375 376#define CR9346 REG_9346CR 377#define MSR (REG_CR + 2) 378#define ISR REG_HISR 379#define TSFR REG_TSFTR 380 381#define MACIDR0 REG_MACID 382#define MACIDR4 (REG_MACID + 4) 383 384#define PBP REG_PBP 385 386#define IDR0 MACIDR0 387#define IDR4 MACIDR4 388 389#define UNUSED_REGISTER 0x1BF 390#define DCAM UNUSED_REGISTER 391#define PSR UNUSED_REGISTER 392#define BBADDR UNUSED_REGISTER 393#define PHYDATAR UNUSED_REGISTER 394 395#define INVALID_BBRF_VALUE 0x12345678 396 397#define MAX_MSS_DENSITY_2T 0x13 398#define MAX_MSS_DENSITY_1T 0x0A 399 400#define CMDEEPROM_EN BIT(5) 401#define CMDEEPROM_SEL BIT(4) 402#define CMD9346CR_9356SEL BIT(4) 403#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 404#define AUTOLOAD_EFUSE CMDEEPROM_EN 405 406#define GPIOSEL_GPIO 0 407#define GPIOSEL_ENBT BIT(5) 408 409#define GPIO_IN REG_GPIO_PIN_CTRL 410#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 411#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 412#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 413 414/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ 415#define HSIMR_GPIO12_0_INT_EN BIT(0) 416#define HSIMR_SPS_OCP_INT_EN BIT(5) 417#define HSIMR_RON_INT_EN BIT(6) 418#define HSIMR_PDN_INT_EN BIT(7) 419#define HSIMR_GPIO9_INT_EN BIT(25) 420 421/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ 422#define HSISR_GPIO12_0_INT BIT(0) 423#define HSISR_SPS_OCP_INT BIT(5) 424#define HSISR_RON_INT_EN BIT(6) 425#define HSISR_PDNINT BIT(7) 426#define HSISR_GPIO9_INT BIT(25) 427 428#define MSR_NOLINK 0x00 429#define MSR_ADHOC 0x01 430#define MSR_INFRA 0x02 431#define MSR_AP 0x03 432#define MSR_MASK 0x03 433 434#define RRSR_RSC_OFFSET 21 435#define RRSR_SHORT_OFFSET 23 436#define RRSR_RSC_BW_40M 0x600000 437#define RRSR_RSC_UPSUBCHNL 0x400000 438#define RRSR_RSC_LOWSUBCHNL 0x200000 439#define RRSR_SHORT 0x800000 440#define RRSR_1M BIT(0) 441#define RRSR_2M BIT(1) 442#define RRSR_5_5M BIT(2) 443#define RRSR_11M BIT(3) 444#define RRSR_6M BIT(4) 445#define RRSR_9M BIT(5) 446#define RRSR_12M BIT(6) 447#define RRSR_18M BIT(7) 448#define RRSR_24M BIT(8) 449#define RRSR_36M BIT(9) 450#define RRSR_48M BIT(10) 451#define RRSR_54M BIT(11) 452#define RRSR_MCS0 BIT(12) 453#define RRSR_MCS1 BIT(13) 454#define RRSR_MCS2 BIT(14) 455#define RRSR_MCS3 BIT(15) 456#define RRSR_MCS4 BIT(16) 457#define RRSR_MCS5 BIT(17) 458#define RRSR_MCS6 BIT(18) 459#define RRSR_MCS7 BIT(19) 460#define BRSR_ACKSHORTPMB BIT(23) 461 462#define RATR_1M 0x00000001 463#define RATR_2M 0x00000002 464#define RATR_55M 0x00000004 465#define RATR_11M 0x00000008 466#define RATR_6M 0x00000010 467#define RATR_9M 0x00000020 468#define RATR_12M 0x00000040 469#define RATR_18M 0x00000080 470#define RATR_24M 0x00000100 471#define RATR_36M 0x00000200 472#define RATR_48M 0x00000400 473#define RATR_54M 0x00000800 474#define RATR_MCS0 0x00001000 475#define RATR_MCS1 0x00002000 476#define RATR_MCS2 0x00004000 477#define RATR_MCS3 0x00008000 478#define RATR_MCS4 0x00010000 479#define RATR_MCS5 0x00020000 480#define RATR_MCS6 0x00040000 481#define RATR_MCS7 0x00080000 482#define RATR_MCS8 0x00100000 483#define RATR_MCS9 0x00200000 484#define RATR_MCS10 0x00400000 485#define RATR_MCS11 0x00800000 486#define RATR_MCS12 0x01000000 487#define RATR_MCS13 0x02000000 488#define RATR_MCS14 0x04000000 489#define RATR_MCS15 0x08000000 490 491#define RATE_1M BIT(0) 492#define RATE_2M BIT(1) 493#define RATE_5_5M BIT(2) 494#define RATE_11M BIT(3) 495#define RATE_6M BIT(4) 496#define RATE_9M BIT(5) 497#define RATE_12M BIT(6) 498#define RATE_18M BIT(7) 499#define RATE_24M BIT(8) 500#define RATE_36M BIT(9) 501#define RATE_48M BIT(10) 502#define RATE_54M BIT(11) 503#define RATE_MCS0 BIT(12) 504#define RATE_MCS1 BIT(13) 505#define RATE_MCS2 BIT(14) 506#define RATE_MCS3 BIT(15) 507#define RATE_MCS4 BIT(16) 508#define RATE_MCS5 BIT(17) 509#define RATE_MCS6 BIT(18) 510#define RATE_MCS7 BIT(19) 511#define RATE_MCS8 BIT(20) 512#define RATE_MCS9 BIT(21) 513#define RATE_MCS10 BIT(22) 514#define RATE_MCS11 BIT(23) 515#define RATE_MCS12 BIT(24) 516#define RATE_MCS13 BIT(25) 517#define RATE_MCS14 BIT(26) 518#define RATE_MCS15 BIT(27) 519 520#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 521#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ 522 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 523#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\ 524 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\ 525 RATR_MCS6 | RATR_MCS7) 526#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\ 527 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\ 528 RATR_MCS14 | RATR_MCS15) 529 530#define BW_OPMODE_20MHZ BIT(2) 531#define BW_OPMODE_5G BIT(1) 532#define BW_OPMODE_11J BIT(0) 533 534#define CAM_VALID BIT(15) 535#define CAM_NOTVALID 0x0000 536#define CAM_USEDK BIT(5) 537 538#define CAM_NONE 0x0 539#define CAM_WEP40 0x01 540#define CAM_TKIP 0x02 541#define CAM_AES 0x04 542#define CAM_WEP104 0x05 543 544#define TOTAL_CAM_ENTRY 32 545#define HALF_CAM_ENTRY 16 546 547#define CAM_WRITE BIT(16) 548#define CAM_READ 0x00000000 549#define CAM_POLLINIG BIT(31) 550 551#define SCR_USEDK 0x01 552#define SCR_TXSEC_ENABLE 0x02 553#define SCR_RXSEC_ENABLE 0x04 554 555#define WOW_PMEN BIT(0) 556#define WOW_WOMEN BIT(1) 557#define WOW_MAGIC BIT(2) 558#define WOW_UWF BIT(3) 559 560/********************************************* 561* 8188 IMR/ISR bits 562**********************************************/ 563#define IMR_DISABLED 0x0 564/* IMR DW0(0x0060-0063) Bit 0-31 */ 565/* TXRPT interrupt when CCX bit of the packet is set */ 566#define IMR_TXCCK BIT(30) 567/* Power Save Time Out Interrupt */ 568#define IMR_PSTIMEOUT BIT(29) 569/* When GTIMER4 expires, this bit is set to 1 */ 570#define IMR_GTINT4 BIT(28) 571/* When GTIMER3 expires, this bit is set to 1 */ 572#define IMR_GTINT3 BIT(27) 573/* Transmit Beacon0 Error */ 574#define IMR_TBDER BIT(26) 575/* Transmit Beacon0 OK */ 576#define IMR_TBDOK BIT(25) 577/* TSF Timer BIT32 toggle indication interrupt */ 578#define IMR_TSF_BIT32_TOGGLE BIT(24) 579/* Beacon DMA Interrupt 0 */ 580#define IMR_BCNDMAINT0 BIT(20) 581/* Beacon Queue DMA OK0 */ 582#define IMR_BCNDOK0 BIT(16) 583/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 584#define IMR_HSISR_IND_ON_INT BIT(15) 585/* Beacon DMA Interrupt Extension for Win7 */ 586#define IMR_BCNDMAINT_E BIT(14) 587/* CTWidnow End or ATIM Window End */ 588#define IMR_ATIMEND BIT(12) 589/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/ 590#define IMR_HISR1_IND_INT BIT(11) 591/* CPU to Host Command INT Status, Write 1 clear */ 592#define IMR_C2HCMD BIT(10) 593/* CPU power Mode exchange INT Status, Write 1 clear */ 594#define IMR_CPWM2 BIT(9) 595/* CPU power Mode exchange INT Status, Write 1 clear */ 596#define IMR_CPWM BIT(8) 597/* High Queue DMA OK */ 598#define IMR_HIGHDOK BIT(7) 599/* Management Queue DMA OK */ 600#define IMR_MGNTDOK BIT(6) 601/* AC_BK DMA OK */ 602#define IMR_BKDOK BIT(5) 603/* AC_BE DMA OK */ 604#define IMR_BEDOK BIT(4) 605/* AC_VI DMA OK */ 606#define IMR_VIDOK BIT(3) 607/* AC_VO DMA OK */ 608#define IMR_VODOK BIT(2) 609/* Rx Descriptor Unavailable */ 610#define IMR_RDU BIT(1) 611#define IMR_ROK BIT(0) /* Receive DMA OK */ 612 613/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 614/* Beacon DMA Interrupt 7 */ 615#define IMR_BCNDMAINT7 BIT(27) 616/* Beacon DMA Interrupt 6 */ 617#define IMR_BCNDMAINT6 BIT(26) 618/* Beacon DMA Interrupt 5 */ 619#define IMR_BCNDMAINT5 BIT(25) 620/* Beacon DMA Interrupt 4 */ 621#define IMR_BCNDMAINT4 BIT(24) 622/* Beacon DMA Interrupt 3 */ 623#define IMR_BCNDMAINT3 BIT(23) 624/* Beacon DMA Interrupt 2 */ 625#define IMR_BCNDMAINT2 BIT(22) 626/* Beacon DMA Interrupt 1 */ 627#define IMR_BCNDMAINT1 BIT(21) 628/* Beacon Queue DMA OK Interrup 7 */ 629#define IMR_BCNDOK7 BIT(20) 630/* Beacon Queue DMA OK Interrup 6 */ 631#define IMR_BCNDOK6 BIT(19) 632/* Beacon Queue DMA OK Interrup 5 */ 633#define IMR_BCNDOK5 BIT(18) 634/* Beacon Queue DMA OK Interrup 4 */ 635#define IMR_BCNDOK4 BIT(17) 636/* Beacon Queue DMA OK Interrup 3 */ 637#define IMR_BCNDOK3 BIT(16) 638/* Beacon Queue DMA OK Interrup 2 */ 639#define IMR_BCNDOK2 BIT(15) 640/* Beacon Queue DMA OK Interrup 1 */ 641#define IMR_BCNDOK1 BIT(14) 642/* ATIM Window End Extension for Win7 */ 643#define IMR_ATIMEND_E BIT(13) 644/* Tx Error Flag Interrupt Status, write 1 clear. */ 645#define IMR_TXERR BIT(11) 646/* Rx Error Flag INT Status, Write 1 clear */ 647#define IMR_RXERR BIT(10) 648/* Transmit FIFO Overflow */ 649#define IMR_TXFOVW BIT(9) 650/* Receive FIFO Overflow */ 651#define IMR_RXFOVW BIT(8) 652 653#define HWSET_MAX_SIZE 512 654#define EFUSE_MAX_SECTION 64 655#define EFUSE_REAL_CONTENT_LEN 256 656/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/ 657#define EFUSE_OOB_PROTECT_BYTES 18 658 659#define EEPROM_DEFAULT_TSSI 0x0 660#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 661#define EEPROM_DEFAULT_CRYSTALCAP 0x5 662#define EEPROM_DEFAULT_BOARDTYPE 0x02 663#define EEPROM_DEFAULT_TXPOWER 0x1010 664#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 665 666#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 667#define EEPROM_DEFAULT_THERMALMETER 0x18 668#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 669#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 670#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 671#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 672#define EEPROM_DEFAULT_HT20_DIFF 2 673#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 674#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 675#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 676 677#define RF_OPTION1 0x79 678#define RF_OPTION2 0x7A 679#define RF_OPTION3 0x7B 680#define RF_OPTION4 0xC3 681 682#define EEPROM_DEFAULT_PID 0x1234 683#define EEPROM_DEFAULT_VID 0x5678 684#define EEPROM_DEFAULT_CUSTOMERID 0xAB 685#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 686#define EEPROM_DEFAULT_VERSION 0 687 688#define EEPROM_CHANNEL_PLAN_FCC 0x0 689#define EEPROM_CHANNEL_PLAN_IC 0x1 690#define EEPROM_CHANNEL_PLAN_ETSI 0x2 691#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 692#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 693#define EEPROM_CHANNEL_PLAN_MKK 0x5 694#define EEPROM_CHANNEL_PLAN_MKK1 0x6 695#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 696#define EEPROM_CHANNEL_PLAN_TELEC 0x8 697#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 698#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 699#define EEPROM_CHANNEL_PLAN_NCC 0xB 700#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 701 702#define EEPROM_CID_DEFAULT 0x0 703#define EEPROM_CID_TOSHIBA 0x4 704#define EEPROM_CID_CCX 0x10 705#define EEPROM_CID_QMI 0x0D 706#define EEPROM_CID_WHQL 0xFE 707 708#define RTL_EEPROM_ID 0x8129 709 710#define EEPROM_HPON 0x02 711#define EEPROM_CLK 0x06 712#define EEPROM_TESTR 0x08 713 714#define EEPROM_TXPOWERCCK 0x10 715#define EEPROM_TXPOWERHT40_1S 0x16 716#define EEPROM_TXPOWERHT20DIFF 0x1B 717#define EEPROM_TXPOWER_OFDMDIFF 0x1B 718 719#define EEPROM_TX_PWR_INX 0x10 720 721#define EEPROM_CHANNELPLAN 0xB8 722#define EEPROM_XTAL_8821AE 0xB9 723#define EEPROM_THERMAL_METER 0xBA 724#define EEPROM_IQK_LCK_88E 0xBB 725 726#define EEPROM_RF_BOARD_OPTION 0xC1 727#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 728#define EEPROM_RF_BT_SETTING 0xC3 729#define EEPROM_VERSION 0xC4 730#define EEPROM_CUSTOMER_ID 0xC5 731#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 732#define EEPROM_RFE_OPTION 0xCA 733 734#define EEPROM_MAC_ADDR 0xD0 735#define EEPROM_VID 0xD6 736#define EEPROM_DID 0xD8 737#define EEPROM_SVID 0xDA 738#define EEPROM_SMID 0xDC 739 740#define STOPBECON BIT(6) 741#define STOPHIGHT BIT(5) 742#define STOPMGT BIT(4) 743#define STOPVO BIT(3) 744#define STOPVI BIT(2) 745#define STOPBE BIT(1) 746#define STOPBK BIT(0) 747 748#define RCR_APPFCS BIT(31) 749#define RCR_APP_MIC BIT(30) 750#define RCR_APP_ICV BIT(29) 751#define RCR_APP_PHYST_RXFF BIT(28) 752#define RCR_APP_BA_SSN BIT(27) 753#define RCR_NONQOS_VHT BIT(26) 754#define RCR_ENMBID BIT(24) 755#define RCR_LSIGEN BIT(23) 756#define RCR_MFBEN BIT(22) 757#define RCR_HTC_LOC_CTRL BIT(14) 758#define RCR_AMF BIT(13) 759#define RCR_ACF BIT(12) 760#define RCR_ADF BIT(11) 761#define RCR_AICV BIT(9) 762#define RCR_ACRC32 BIT(8) 763#define RCR_CBSSID_BCN BIT(7) 764#define RCR_CBSSID_DATA BIT(6) 765#define RCR_CBSSID RCR_CBSSID_DATA 766#define RCR_APWRMGT BIT(5) 767#define RCR_ADD3 BIT(4) 768#define RCR_AB BIT(3) 769#define RCR_AM BIT(2) 770#define RCR_APM BIT(1) 771#define RCR_AAP BIT(0) 772#define RCR_MXDMA_OFFSET 8 773#define RCR_FIFO_OFFSET 13 774 775#define RSV_CTRL 0x001C 776#define RD_CTRL 0x0524 777 778#define REG_USB_INFO 0xFE17 779#define REG_USB_SPECIAL_OPTION 0xFE55 780#define REG_USB_DMA_AGG_TO 0xFE5B 781#define REG_USB_AGG_TO 0xFE5C 782#define REG_USB_AGG_TH 0xFE5D 783 784#define REG_USB_VID 0xFE60 785#define REG_USB_PID 0xFE62 786#define REG_USB_OPTIONAL 0xFE64 787#define REG_USB_CHIRP_K 0xFE65 788#define REG_USB_PHY 0xFE66 789#define REG_USB_MAC_ADDR 0xFE70 790#define REG_USB_HRPWM 0xFE58 791#define REG_USB_HCPWM 0xFE57 792 793#define SW18_FPWM BIT(3) 794 795#define ISO_MD2PP BIT(0) 796#define ISO_UA2USB BIT(1) 797#define ISO_UD2CORE BIT(2) 798#define ISO_PA2PCIE BIT(3) 799#define ISO_PD2CORE BIT(4) 800#define ISO_IP2MAC BIT(5) 801#define ISO_DIOP BIT(6) 802#define ISO_DIOE BIT(7) 803#define ISO_EB2CORE BIT(8) 804#define ISO_DIOR BIT(9) 805 806#define PWC_EV25V BIT(14) 807#define PWC_EV12V BIT(15) 808 809#define FEN_BBRSTB BIT(0) 810#define FEN_BB_GLB_RSTN BIT(1) 811#define FEN_USBA BIT(2) 812#define FEN_UPLL BIT(3) 813#define FEN_USBD BIT(4) 814#define FEN_DIO_PCIE BIT(5) 815#define FEN_PCIEA BIT(6) 816#define FEN_PPLL BIT(7) 817#define FEN_PCIED BIT(8) 818#define FEN_DIOE BIT(9) 819#define FEN_CPUEN BIT(10) 820#define FEN_DCORE BIT(11) 821#define FEN_ELDR BIT(12) 822#define FEN_DIO_RF BIT(13) 823#define FEN_HWPDN BIT(14) 824#define FEN_MREGEN BIT(15) 825 826#define PFM_LDALL BIT(0) 827#define PFM_ALDN BIT(1) 828#define PFM_LDKP BIT(2) 829#define PFM_WOWL BIT(3) 830#define ENPDN BIT(4) 831#define PDN_PL BIT(5) 832#define APFM_ONMAC BIT(8) 833#define APFM_OFF BIT(9) 834#define APFM_RSM BIT(10) 835#define AFSM_HSUS BIT(11) 836#define AFSM_PCIE BIT(12) 837#define APDM_MAC BIT(13) 838#define APDM_HOST BIT(14) 839#define APDM_HPDN BIT(15) 840#define RDY_MACON BIT(16) 841#define SUS_HOST BIT(17) 842#define ROP_ALD BIT(20) 843#define ROP_PWR BIT(21) 844#define ROP_SPS BIT(22) 845#define SOP_MRST BIT(25) 846#define SOP_FUSE BIT(26) 847#define SOP_ABG BIT(27) 848#define SOP_AMB BIT(28) 849#define SOP_RCK BIT(29) 850#define SOP_A8M BIT(30) 851#define XOP_BTCK BIT(31) 852 853#define ANAD16V_EN BIT(0) 854#define ANA8M BIT(1) 855#define MACSLP BIT(4) 856#define LOADER_CLK_EN BIT(5) 857#define _80M_SSC_DIS BIT(7) 858#define _80M_SSC_EN_HO BIT(8) 859#define PHY_SSC_RSTB BIT(9) 860#define SEC_CLK_EN BIT(10) 861#define MAC_CLK_EN BIT(11) 862#define SYS_CLK_EN BIT(12) 863#define RING_CLK_EN BIT(13) 864 865#define BOOT_FROM_EEPROM BIT(4) 866#define EEPROM_EN BIT(5) 867 868#define AFE_BGEN BIT(0) 869#define AFE_MBEN BIT(1) 870#define MAC_ID_EN BIT(7) 871 872#define WLOCK_ALL BIT(0) 873#define WLOCK_00 BIT(1) 874#define WLOCK_04 BIT(2) 875#define WLOCK_08 BIT(3) 876#define WLOCK_40 BIT(4) 877#define R_DIS_PRST_0 BIT(5) 878#define R_DIS_PRST_1 BIT(6) 879#define LOCK_ALL_EN BIT(7) 880 881#define RF_EN BIT(0) 882#define RF_RSTB BIT(1) 883#define RF_SDMRSTB BIT(2) 884 885#define LDA15_EN BIT(0) 886#define LDA15_STBY BIT(1) 887#define LDA15_OBUF BIT(2) 888#define LDA15_REG_VOS BIT(3) 889#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 890 891#define LDV12_EN BIT(0) 892#define LDV12_SDBY BIT(1) 893#define LPLDO_HSM BIT(2) 894#define LPLDO_LSM_DIS BIT(3) 895#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 896 897#define XTAL_EN BIT(0) 898#define XTAL_BSEL BIT(1) 899#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 900#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 901#define XTAL_GATE_USB BIT(8) 902#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 903#define XTAL_GATE_AFE BIT(11) 904#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 905#define XTAL_RF_GATE BIT(14) 906#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 907#define XTAL_GATE_DIG BIT(17) 908#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 909#define XTAL_BT_GATE BIT(20) 910#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 911#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 912 913#define CKDLY_AFE BIT(26) 914#define CKDLY_USB BIT(27) 915#define CKDLY_DIG BIT(28) 916#define CKDLY_BT BIT(29) 917 918#define APLL_EN BIT(0) 919#define APLL_320_EN BIT(1) 920#define APLL_FREF_SEL BIT(2) 921#define APLL_EDGE_SEL BIT(3) 922#define APLL_WDOGB BIT(4) 923#define APLL_LPFEN BIT(5) 924 925#define APLL_REF_CLK_13MHZ 0x1 926#define APLL_REF_CLK_19_2MHZ 0x2 927#define APLL_REF_CLK_20MHZ 0x3 928#define APLL_REF_CLK_25MHZ 0x4 929#define APLL_REF_CLK_26MHZ 0x5 930#define APLL_REF_CLK_38_4MHZ 0x6 931#define APLL_REF_CLK_40MHZ 0x7 932 933#define APLL_320EN BIT(14) 934#define APLL_80EN BIT(15) 935#define APLL_1MEN BIT(24) 936 937#define ALD_EN BIT(18) 938#define EF_PD BIT(19) 939#define EF_FLAG BIT(31) 940 941#define EF_TRPT BIT(7) 942#define LDOE25_EN BIT(31) 943 944#define RSM_EN BIT(0) 945#define TIMER_EN BIT(4) 946 947#define TRSW0EN BIT(2) 948#define TRSW1EN BIT(3) 949#define EROM_EN BIT(4) 950#define ENBT BIT(5) 951#define ENUART BIT(8) 952#define UART_910 BIT(9) 953#define ENPMAC BIT(10) 954#define SIC_SWRST BIT(11) 955#define ENSIC BIT(12) 956#define SIC_23 BIT(13) 957#define ENHDP BIT(14) 958#define SIC_LBK BIT(15) 959 960#define LED0PL BIT(4) 961#define LED1PL BIT(12) 962#define LED0DIS BIT(7) 963 964#define MCUFWDL_EN BIT(0) 965#define MCUFWDL_RDY BIT(1) 966#define FWDL_CHKSUM_RPT BIT(2) 967#define MACINI_RDY BIT(3) 968#define BBINI_RDY BIT(4) 969#define RFINI_RDY BIT(5) 970#define WINTINI_RDY BIT(6) 971#define CPRST BIT(23) 972 973#define XCLK_VLD BIT(0) 974#define ACLK_VLD BIT(1) 975#define UCLK_VLD BIT(2) 976#define PCLK_VLD BIT(3) 977#define PCIRSTB BIT(4) 978#define V15_VLD BIT(5) 979#define TRP_B15V_EN BIT(7) 980#define SIC_IDLE BIT(8) 981#define BD_MAC2 BIT(9) 982#define BD_MAC1 BIT(10) 983#define IC_MACPHY_MODE BIT(11) 984#define VENDOR_ID BIT(19) 985#define PAD_HWPD_IDN BIT(22) 986#define TRP_VAUX_EN BIT(23) 987#define TRP_BT_EN BIT(24) 988#define BD_PKG_SEL BIT(25) 989#define BD_HCI_SEL BIT(26) 990#define TYPE_ID BIT(27) 991 992#define CHIP_VER_RTL_MASK 0xF000 993#define CHIP_VER_RTL_SHIFT 12 994 995#define REG_LBMODE (REG_CR + 3) 996 997#define HCI_TXDMA_EN BIT(0) 998#define HCI_RXDMA_EN BIT(1) 999#define TXDMA_EN BIT(2) 1000#define RXDMA_EN BIT(3)
1001#define PROTOCOL_EN BIT(4) 1002#define SCHEDULE_EN BIT(5) 1003#define MACTXEN BIT(6) 1004#define MACRXEN BIT(7) 1005#define ENSWBCN BIT(8) 1006#define ENSEC BIT(9) 1007 1008#define _NETTYPE(x) (((x) & 0x3) << 16) 1009#define MASK_NETTYPE 0x30000 1010#define NT_NO_LINK 0x0 1011#define NT_LINK_AD_HOC 0x1 1012#define NT_LINK_AP 0x2 1013#define NT_AS_AP 0x3 1014 1015#define _LBMODE(x) (((x) & 0xF) << 24) 1016#define MASK_LBMODE 0xF000000 1017#define LOOPBACK_NORMAL 0x0 1018#define LOOPBACK_IMMEDIATELY 0xB 1019#define LOOPBACK_MAC_DELAY 0x3 1020#define LOOPBACK_PHY 0x1 1021#define LOOPBACK_DMA 0x7 1022 1023#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 1024#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 1025#define _PSRX_MASK 0xF 1026#define _PSTX_MASK 0xF0 1027#define _PSRX(x) (x) 1028#define _PSTX(x) ((x) << 4) 1029 1030#define PBP_64 0x0 1031#define PBP_128 0x1 1032#define PBP_256 0x2 1033#define PBP_512 0x3 1034#define PBP_1024 0x4 1035 1036#define RXDMA_ARBBW_EN BIT(0) 1037#define RXSHFT_EN BIT(1) 1038#define RXDMA_AGG_EN BIT(2) 1039#define QS_VO_QUEUE BIT(8) 1040#define QS_VI_QUEUE BIT(9) 1041#define QS_BE_QUEUE BIT(10) 1042#define QS_BK_QUEUE BIT(11) 1043#define QS_MANAGER_QUEUE BIT(12) 1044#define QS_HIGH_QUEUE BIT(13) 1045 1046#define HQSEL_VOQ BIT(0) 1047#define HQSEL_VIQ BIT(1) 1048#define HQSEL_BEQ BIT(2) 1049#define HQSEL_BKQ BIT(3) 1050#define HQSEL_MGTQ BIT(4) 1051#define HQSEL_HIQ BIT(5) 1052 1053#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 1054#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 1055#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 1056#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 1057#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 1058#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 1059 1060#define QUEUE_LOW 1 1061#define QUEUE_NORMAL 2 1062#define QUEUE_HIGH 3 1063 1064#define _LLT_NO_ACTIVE 0x0 1065#define _LLT_WRITE_ACCESS 0x1 1066#define _LLT_READ_ACCESS 0x2 1067 1068#define _LLT_INIT_DATA(x) ((x) & 0xFF) 1069#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1070#define _LLT_OP(x) (((x) & 0x3) << 30) 1071#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1072 1073#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1074#define BB_WRITE_EN BIT(30) 1075#define BB_READ_EN BIT(31) 1076 1077#define _HPQ(x) ((x) & 0xFF) 1078#define _LPQ(x) (((x) & 0xFF) << 8) 1079#define _PUBQ(x) (((x) & 0xFF) << 16) 1080#define _NPQ(x) ((x) & 0xFF) 1081 1082#define HPQ_PUBLIC_DIS BIT(24) 1083#define LPQ_PUBLIC_DIS BIT(25) 1084#define LD_RQPN BIT(31) 1085 1086#define BCN_VALID BIT(16) 1087#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1088#define BCN_HEAD_MASK 0xFF00 1089 1090#define BLK_DESC_NUM_SHIFT 4 1091#define BLK_DESC_NUM_MASK 0xF 1092 1093#define DROP_DATA_EN BIT(9) 1094 1095#define EN_AMPDU_RTY_NEW BIT(7) 1096 1097#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1098 1099#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1100#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1101 1102#define RATE_REG_BITMAP_ALL 0xFFFFF 1103 1104#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1105 1106#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1107#define RRSR_RSC_RESERVED 0x0 1108#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1109#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1110#define RRSR_RSC_DUPLICATE_MODE 0x3 1111 1112#define USE_SHORT_G1 BIT(20) 1113 1114#define _AGGLMT_MCS0(x) ((x) & 0xF) 1115#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1116#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1117#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1118#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1119#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1120#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1121#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1122 1123#define RETRY_LIMIT_SHORT_SHIFT 8 1124#define RETRY_LIMIT_LONG_SHIFT 0 1125 1126#define _DARF_RC1(x) ((x) & 0x1F) 1127#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1128#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1129#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1130#define _DARF_RC5(x) ((x) & 0x1F) 1131#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1132#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1133#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1134 1135#define _RARF_RC1(x) ((x) & 0x1F) 1136#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1137#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1138#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1139#define _RARF_RC5(x) ((x) & 0x1F) 1140#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1141#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1142#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1143 1144#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1145#define AC_PARAM_ECW_MAX_OFFSET 12 1146#define AC_PARAM_ECW_MIN_OFFSET 8 1147#define AC_PARAM_AIFS_OFFSET 0 1148 1149#define _AIFS(x) (x) 1150#define _ECW_MAX_MIN(x) ((x) << 8) 1151#define _TXOP_LIMIT(x) ((x) << 16) 1152 1153#define _BCNIFS(x) ((x) & 0xFF) 1154#define _BCNECW(x) ((((x) & 0xF)) << 8) 1155 1156#define _LRL(x) ((x) & 0x3F) 1157#define _SRL(x) (((x) & 0x3F) << 8) 1158 1159#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1160#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 1161 1162#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1163#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 1164 1165#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1166 1167#define DIS_EDCA_CNT_DWN BIT(11) 1168 1169#define EN_MBSSID BIT(1) 1170#define EN_TXBCN_RPT BIT(2) 1171#define EN_BCN_FUNCTION BIT(3) 1172 1173#define TSFTR_RST BIT(0) 1174#define TSFTR1_RST BIT(1) 1175 1176#define STOP_BCNQ BIT(6) 1177 1178#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1179#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1180 1181#define ACMHW_HWEN BIT(0) 1182#define ACMHW_BEQEN BIT(1) 1183#define ACMHW_VIQEN BIT(2) 1184#define ACMHW_VOQEN BIT(3) 1185#define ACMHW_BEQSTATUS BIT(4) 1186#define ACMHW_VIQSTATUS BIT(5) 1187#define ACMHW_VOQSTATUS BIT(6) 1188 1189#define APSDOFF BIT(6) 1190#define APSDOFF_STATUS BIT(7) 1191 1192#define BW_20MHZ BIT(2) 1193 1194#define RATE_BITMAP_ALL 0xFFFFF 1195 1196#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1197 1198#define TSFRST BIT(0) 1199#define DIS_GCLK BIT(1) 1200#define PAD_SEL BIT(2) 1201#define PWR_ST BIT(6) 1202#define PWRBIT_OW_EN BIT(7) 1203#define ACRC BIT(8) 1204#define CFENDFORM BIT(9) 1205#define ICV BIT(10) 1206 1207#define AAP BIT(0) 1208#define APM BIT(1) 1209#define AM BIT(2) 1210#define AB BIT(3) 1211#define ADD3 BIT(4) 1212#define APWRMGT BIT(5) 1213#define CBSSID BIT(6) 1214#define CBSSID_DATA BIT(6) 1215#define CBSSID_BCN BIT(7) 1216#define ACRC32 BIT(8) 1217#define AICV BIT(9) 1218#define ADF BIT(11) 1219#define ACF BIT(12) 1220#define AMF BIT(13) 1221#define HTC_LOC_CTRL BIT(14) 1222#define UC_DATA_EN BIT(16) 1223#define BM_DATA_EN BIT(17) 1224#define MFBEN BIT(22) 1225#define LSIGEN BIT(23) 1226#define ENMBID BIT(24) 1227#define APP_BASSN BIT(27) 1228#define APP_PHYSTS BIT(28) 1229#define APP_ICV BIT(29) 1230#define APP_MIC BIT(30) 1231#define APP_FCS BIT(31) 1232 1233#define _MIN_SPACE(x) ((x) & 0x7) 1234#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1235 1236#define RXERR_TYPE_OFDM_PPDU 0 1237#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1238#define RXERR_TYPE_OFDM_MPDU_OK 2 1239#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1240#define RXERR_TYPE_CCK_PPDU 4 1241#define RXERR_TYPE_CCK_FALSE_ALARM 5 1242#define RXERR_TYPE_CCK_MPDU_OK 6 1243#define RXERR_TYPE_CCK_MPDU_FAIL 7 1244#define RXERR_TYPE_HT_PPDU 8 1245#define RXERR_TYPE_HT_FALSE_ALARM 9 1246#define RXERR_TYPE_HT_MPDU_TOTAL 10 1247#define RXERR_TYPE_HT_MPDU_OK 11 1248#define RXERR_TYPE_HT_MPDU_FAIL 12 1249#define RXERR_TYPE_RX_FULL_DROP 15 1250 1251#define RXERR_COUNTER_MASK 0xFFFFF 1252#define RXERR_RPT_RST BIT(27) 1253#define _RXERR_RPT_SEL(type) ((type) << 28) 1254 1255#define SCR_TXUSEDK BIT(0) 1256#define SCR_RXUSEDK BIT(1) 1257#define SCR_TXENCENABLE BIT(2) 1258#define SCR_RXDECENABLE BIT(3) 1259#define SCR_SKBYA2 BIT(4) 1260#define SCR_NOSKMC BIT(5) 1261#define SCR_TXBCUSEDK BIT(6) 1262#define SCR_RXBCUSEDK BIT(7) 1263 1264#define XCLK_VLD BIT(0) 1265#define ACLK_VLD BIT(1) 1266#define UCLK_VLD BIT(2) 1267#define PCLK_VLD BIT(3) 1268#define PCIRSTB BIT(4) 1269#define V15_VLD BIT(5) 1270#define TRP_B15V_EN BIT(7) 1271#define SIC_IDLE BIT(8) 1272#define BD_MAC2 BIT(9) 1273#define BD_MAC1 BIT(10) 1274#define IC_MACPHY_MODE BIT(11) 1275#define BT_FUNC BIT(16) 1276#define VENDOR_ID BIT(19) 1277#define PAD_HWPD_IDN BIT(22) 1278#define TRP_VAUX_EN BIT(23) 1279#define TRP_BT_EN BIT(24) 1280#define BD_PKG_SEL BIT(25) 1281#define BD_HCI_SEL BIT(26) 1282#define TYPE_ID BIT(27) 1283 1284#define USB_IS_HIGH_SPEED 0 1285#define USB_IS_FULL_SPEED 1 1286#define USB_SPEED_MASK BIT(5) 1287 1288#define USB_NORMAL_SIE_EP_MASK 0xF 1289#define USB_NORMAL_SIE_EP_SHIFT 4 1290 1291#define USB_TEST_EP_MASK 0x30 1292#define USB_TEST_EP_SHIFT 4 1293 1294#define USB_AGG_EN BIT(3) 1295 1296#define MAC_ADDR_LEN 6 1297#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1298 1299#define POLLING_LLT_THRESHOLD 20 1300#define POLLING_READY_TIMEOUT_COUNT 3000 1301 1302#define MAX_MSS_DENSITY_2T 0x13 1303#define MAX_MSS_DENSITY_1T 0x0A 1304 1305#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1306#define EPROM_CMD_CONFIG 0x3 1307#define EPROM_CMD_LOAD 1 1308 1309#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1310 1311#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1312 1313#define RA_LSSIWRITE_8821A 0xc90 1314#define RB_LSSIWRITE_8821A 0xe90 1315 1316#define RA_PIREAD_8821A 0xd04 1317#define RB_PIREAD_8821A 0xd44 1318#define RA_SIREAD_8821A 0xd08 1319#define RB_SIREAD_8821A 0xd48 1320 1321#define RPMAC_RESET 0x100 1322#define RPMAC_TXSTART 0x104 1323#define RPMAC_TXLEGACYSIG 0x108 1324#define RPMAC_TXHTSIG1 0x10c 1325#define RPMAC_TXHTSIG2 0x110 1326#define RPMAC_PHYDEBUG 0x114 1327#define RPMAC_TXPACKETNUM 0x118 1328#define RPMAC_TXIDLE 0x11c 1329#define RPMAC_TXMACHEADER0 0x120 1330#define RPMAC_TXMACHEADER1 0x124 1331#define RPMAC_TXMACHEADER2 0x128 1332#define RPMAC_TXMACHEADER3 0x12c 1333#define RPMAC_TXMACHEADER4 0x130 1334#define RPMAC_TXMACHEADER5 0x134 1335#define RPMAC_TXDADATYPE 0x138 1336#define RPMAC_TXRANDOMSEED 0x13c 1337#define RPMAC_CCKPLCPPREAMBLE 0x140 1338#define RPMAC_CCKPLCPHEADER 0x144 1339#define RPMAC_CCKCRC16 0x148 1340#define RPMAC_OFDMRXCRC32OK 0x170 1341#define RPMAC_OFDMRXCRC32ER 0x174 1342#define RPMAC_OFDMRXPARITYER 0x178 1343#define RPMAC_OFDMRXCRC8ER 0x17c 1344#define RPMAC_CCKCRXRC16ER 0x180 1345#define RPMAC_CCKCRXRC32ER 0x184 1346#define RPMAC_CCKCRXRC32OK 0x188 1347#define RPMAC_TXSTATUS 0x18c 1348 1349#define RFPGA0_RFMOD 0x800 1350 1351#define RFPGA0_TXINFO 0x804 1352#define RFPGA0_PSDFUNCTION 0x808 1353 1354#define RFPGA0_TXGAINSTAGE 0x80c 1355 1356#define RFPGA0_RFTIMING1 0x810 1357#define RFPGA0_RFTIMING2 0x814 1358 1359#define RFPGA0_XA_HSSIPARAMETER1 0x820 1360#define RFPGA0_XA_HSSIPARAMETER2 0x824 1361#define RFPGA0_XB_HSSIPARAMETER1 0x828 1362#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1363#define RCCAONSEC 0x838 1364 1365#define RFPGA0_XA_LSSIPARAMETER 0x840 1366#define RFPGA0_XB_LSSIPARAMETER 0x844 1367#define RL1PEAKTH 0x848 1368 1369#define RFPGA0_RFWAKEUPPARAMETER 0x850 1370#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1371 1372#define RFPGA0_XAB_SWITCHCONTROL 0x858 1373#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1374 1375#define RFPGA0_XA_RFINTERFACEOE 0x860 1376#define RFC_AREA 0x860 1377#define RFPGA0_XB_RFINTERFACEOE 0x864 1378 1379#define RFPGA0_XAB_RFINTERFACESW 0x870 1380#define RFPGA0_XCD_RFINTERFACESW 0x874 1381 1382#define RFPGA0_XAB_RFPARAMETER 0x878 1383#define RFPGA0_XCD_RFPARAMETER 0x87c 1384 1385#define RFPGA0_ANALOGPARAMETER1 0x880 1386#define RFPGA0_ANALOGPARAMETER2 0x884 1387#define RFPGA0_ANALOGPARAMETER3 0x888 1388#define RFPGA0_ANALOGPARAMETER4 0x88c 1389 1390#define RFPGA0_XA_LSSIREADBACK 0x8a0 1391#define RFPGA0_XB_LSSIREADBACK 0x8a4 1392#define RFPGA0_XC_LSSIREADBACK 0x8a8 1393#define RRFMOD 0x8ac 1394#define RHSSIREAD_8821AE 0x8b0 1395 1396#define RFPGA0_PSDREPORT 0x8b4 1397#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1398#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1399#define RADC_BUF_CLK 0x8c4 1400#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1401#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1402 1403#define RFPGA1_RFMOD 0x900 1404 1405#define RFPGA1_TXBLOCK 0x904 1406#define RFPGA1_DEBUGSELECT 0x908 1407#define RFPGA1_TXINFO 0x90c 1408 1409#define RCCK_SYSTEM 0xa00 1410#define BCCK_SYSTEM 0x10 1411 1412#define RCCK0_AFESETTING 0xa04 1413#define RCCK0_CCA 0xa08 1414 1415#define RCCK0_RXAGC1 0xa0c 1416#define RCCK0_RXAGC2 0xa10 1417 1418#define RCCK0_RXHP 0xa14 1419 1420#define RCCK0_DSPPARAMETER1 0xa18 1421#define RCCK0_DSPPARAMETER2 0xa1c 1422 1423#define RCCK0_TXFILTER1 0xa20 1424#define RCCK0_TXFILTER2 0xa24 1425#define RCCK0_DEBUGPORT 0xa28 1426#define RCCK0_FALSEALARMREPORT 0xa2c 1427#define RCCK0_TRSSIREPORT 0xa50 1428#define RCCK0_RXREPORT 0xa54 1429#define RCCK0_FACOUNTERLOWER 0xa5c 1430#define RCCK0_FACOUNTERUPPER 0xa58 1431#define RCCK0_CCA_CNT 0xa60 1432 1433/* PageB(0xB00) */ 1434#define RPDP_ANTA 0xb00 1435#define RPDP_ANTA_4 0xb04 1436#define RPDP_ANTA_8 0xb08 1437#define RPDP_ANTA_C 0xb0c 1438#define RPDP_ANTA_10 0xb10 1439#define RPDP_ANTA_14 0xb14 1440#define RPDP_ANTA_18 0xb18 1441#define RPDP_ANTA_1C 0xb1c 1442#define RPDP_ANTA_20 0xb20 1443#define RPDP_ANTA_24 0xb24 1444 1445#define RCONFIG_PMPD_ANTA 0xb28 1446#define RCONFIG_RAM64x16 0xb2c 1447 1448#define RBNDA 0xb30 1449#define RHSSIPAR 0xb34 1450 1451#define RCONFIG_ANTA 0xb68 1452#define RCONFIG_ANTB 0xb6c 1453 1454#define RPDP_ANTB 0xb70 1455#define RPDP_ANTB_4 0xb74 1456#define RPDP_ANTB_8 0xb78 1457#define RPDP_ANTB_C 0xb7c 1458#define RPDP_ANTB_10 0xb80 1459#define RPDP_ANTB_14 0xb84 1460#define RPDP_ANTB_18 0xb88 1461#define RPDP_ANTB_1C 0xb8c 1462#define RPDP_ANTB_20 0xb90 1463#define RPDP_ANTB_24 0xb94 1464 1465#define RCONFIG_PMPD_ANTB 0xb98 1466 1467#define RBNDB 0xba0 1468 1469#define RAPK 0xbd8 1470#define RPM_RX0_ANTA 0xbdc 1471#define RPM_RX1_ANTA 0xbe0 1472#define RPM_RX2_ANTA 0xbe4 1473#define RPM_RX3_ANTA 0xbe8 1474#define RPM_RX0_ANTB 0xbec 1475#define RPM_RX1_ANTB 0xbf0 1476#define RPM_RX2_ANTB 0xbf4 1477#define RPM_RX3_ANTB 0xbf8 1478 1479/*RSSI Dump*/ 1480#define RA_RSSI_DUMP 0xBF0 1481#define RB_RSSI_DUMP 0xBF1 1482#define RS1_RX_EVM_DUMP 0xBF4 1483#define RS2_RX_EVM_DUMP 0xBF5 1484#define RA_RX_SNR_DUMP 0xBF6 1485#define RB_RX_SNR_DUMP 0xBF7 1486#define RA_CFO_SHORT_DUMP 0xBF8 1487#define RB_CFO_SHORT_DUMP 0xBFA 1488#define RA_CFO_LONG_DUMP 0xBEC 1489#define RB_CFO_LONG_DUMP 0xBEE 1490 1491/*Page C*/ 1492#define ROFDM0_LSTF 0xc00 1493 1494#define ROFDM0_TRXPATHENABLE 0xc04 1495#define ROFDM0_TRMUXPAR 0xc08 1496#define ROFDM0_TRSWISOLATION 0xc0c 1497 1498#define ROFDM0_XARXAFE 0xc10 1499#define ROFDM0_XARXIQIMBALANCE 0xc14 1500#define ROFDM0_XBRXAFE 0xc18 1501#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1502#define ROFDM0_XCRXAFE 0xc20 1503#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1504#define ROFDM0_XDRXAFE 0xc28 1505#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1506 1507#define ROFDM0_RXDETECTOR1 0xc30 1508#define ROFDM0_RXDETECTOR2 0xc34 1509#define ROFDM0_RXDETECTOR3 0xc38 1510#define ROFDM0_RXDETECTOR4 0xc3c 1511 1512#define ROFDM0_RXDSP 0xc40 1513#define ROFDM0_CFOANDDAGC 0xc44 1514#define ROFDM0_CCADROPTHRESHOLD 0xc48 1515#define ROFDM0_ECCATHRESHOLD 0xc4c 1516 1517#define ROFDM0_XAAGCCORE1 0xc50 1518#define ROFDM0_XAAGCCORE2 0xc54 1519#define ROFDM0_XBAGCCORE1 0xc58 1520#define ROFDM0_XBAGCCORE2 0xc5c 1521#define ROFDM0_XCAGCCORE1 0xc60 1522#define ROFDM0_XCAGCCORE2 0xc64 1523#define ROFDM0_XDAGCCORE1 0xc68 1524#define ROFDM0_XDAGCCORE2 0xc6c 1525 1526#define ROFDM0_AGCPARAMETER1 0xc70 1527#define ROFDM0_AGCPARAMETER2 0xc74 1528#define ROFDM0_AGCRSSITABLE 0xc78 1529#define ROFDM0_HTSTFAGC 0xc7c 1530 1531#define ROFDM0_XATXIQIMBALANCE 0xc80 1532#define ROFDM0_XATXAFE 0xc84 1533#define ROFDM0_XBTXIQIMBALANCE 0xc88 1534#define ROFDM0_XBTXAFE 0xc8c 1535#define ROFDM0_XCTXIQIMBALANCE 0xc90 1536#define ROFDM0_XCTXAFE 0xc94 1537#define ROFDM0_XDTXIQIMBALANCE 0xc98 1538#define ROFDM0_XDTXAFE 0xc9c 1539 1540#define ROFDM0_RXIQEXTANTA 0xca0 1541#define ROFDM0_TXCOEFF1 0xca4 1542#define ROFDM0_TXCOEFF2 0xca8 1543#define ROFDM0_TXCOEFF3 0xcac 1544#define ROFDM0_TXCOEFF4 0xcb0 1545#define ROFDM0_TXCOEFF5 0xcb4 1546#define ROFDM0_TXCOEFF6 0xcb8 1547 1548/*Path_A RFE cotrol */ 1549#define RA_RFE_CTRL_8812 0xcb8 1550/*Path_B RFE control*/ 1551#define RB_RFE_CTRL_8812 0xeb8 1552 1553#define ROFDM0_RXHPPARAMETER 0xce0 1554#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1555#define ROFDM0_FRAMESYNC 0xcf0 1556#define ROFDM0_DFSREPORT 0xcf4 1557 1558#define ROFDM1_LSTF 0xd00 1559#define ROFDM1_TRXPATHENABLE 0xd04 1560 1561#define ROFDM1_CF0 0xd08 1562#define ROFDM1_CSI1 0xd10 1563#define ROFDM1_SBD 0xd14 1564#define ROFDM1_CSI2 0xd18 1565#define ROFDM1_CFOTRACKING 0xd2c 1566#define ROFDM1_TRXMESAURE1 0xd34 1567#define ROFDM1_INTFDET 0xd3c 1568#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1569#define ROFDM1_PSEUDONOISESTATECD 0xd54 1570#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1571 1572#define ROFDM_PHYCOUNTER1 0xda0 1573#define ROFDM_PHYCOUNTER2 0xda4 1574#define ROFDM_PHYCOUNTER3 0xda8 1575 1576#define ROFDM_SHORTCFOAB 0xdac 1577#define ROFDM_SHORTCFOCD 0xdb0 1578#define ROFDM_LONGCFOAB 0xdb4 1579#define ROFDM_LONGCFOCD 0xdb8 1580#define ROFDM_TAILCF0AB 0xdbc 1581#define ROFDM_TAILCF0CD 0xdc0 1582#define ROFDM_PWMEASURE1 0xdc4 1583#define ROFDM_PWMEASURE2 0xdc8 1584#define ROFDM_BWREPORT 0xdcc 1585#define ROFDM_AGCREPORT 0xdd0 1586#define ROFDM_RXSNR 0xdd4 1587#define ROFDM_RXEVMCSI 0xdd8 1588#define ROFDM_SIGREPORT 0xddc 1589 1590#define RTXAGC_A_CCK11_CCK1 0xc20 1591#define RTXAGC_A_OFDM18_OFDM6 0xc24 1592#define RTXAGC_A_OFDM54_OFDM24 0xc28 1593#define RTXAGC_A_MCS03_MCS00 0xc2c 1594#define RTXAGC_A_MCS07_MCS04 0xc30 1595#define RTXAGC_A_MCS11_MCS08 0xc34 1596#define RTXAGC_A_MCS15_MCS12 0xc38 1597#define RTXAGC_A_NSS1INDEX3_NSS1INDEX0 0xc3c 1598#define RTXAGC_A_NSS1INDEX7_NSS1INDEX4 0xc40 1599#define RTXAGC_A_NSS2INDEX1_NSS1INDEX8 0xc44 1600#define RTXAGC_A_NSS2INDEX5_NSS2INDEX2 0xc48 1601#define RTXAGC_A_NSS2INDEX9_NSS2INDEX6 0xc4c 1602#define RTXAGC_B_CCK11_CCK1 0xe20 1603#define RTXAGC_B_OFDM18_OFDM6 0xe24 1604#define RTXAGC_B_OFDM54_OFDM24 0xe28 1605#define RTXAGC_B_MCS03_MCS00 0xe2c 1606#define RTXAGC_B_MCS07_MCS04 0xe30 1607#define RTXAGC_B_MCS11_MCS08 0xe34 1608#define RTXAGC_B_MCS15_MCS12 0xe38 1609#define RTXAGC_B_NSS1INDEX3_NSS1INDEX0 0xe3c 1610#define RTXAGC_B_NSS1INDEX7_NSS1INDEX4 0xe40 1611#define RTXAGC_B_NSS2INDEX1_NSS1INDEX8 0xe44 1612#define RTXAGC_B_NSS2INDEX5_NSS2INDEX2 0xe48 1613#define RTXAGC_B_NSS2INDEX9_NSS2INDEX6 0xe4c 1614 1615#define RA_TXPWRTRAING 0xc54 1616#define RB_TXPWRTRAING 0xe54 1617 1618#define RFPGA0_IQK 0xe28 1619#define RTX_IQK_TONE_A 0xe30 1620#define RRX_IQK_TONE_A 0xe34 1621#define RTX_IQK_PI_A 0xe38 1622#define RRX_IQK_PI_A 0xe3c 1623 1624#define RTX_IQK 0xe40 1625#define RRX_IQK 0xe44 1626#define RIQK_AGC_PTS 0xe48 1627#define RIQK_AGC_RSP 0xe4c 1628#define RTX_IQK_TONE_B 0xe50 1629#define RRX_IQK_TONE_B 0xe54 1630#define RTX_IQK_PI_B 0xe58 1631#define RRX_IQK_PI_B 0xe5c 1632#define RIQK_AGC_CONT 0xe60 1633 1634#define RBLUE_TOOTH 0xe6c 1635#define RRX_WAIT_CCA 0xe70 1636#define RTX_CCK_RFON 0xe74 1637#define RTX_CCK_BBON 0xe78 1638#define RTX_OFDM_RFON 0xe7c 1639#define RTX_OFDM_BBON 0xe80 1640#define RTX_TO_RX 0xe84 1641#define RTX_TO_TX 0xe88 1642#define RRX_CCK 0xe8c 1643 1644#define RTX_POWER_BEFORE_IQK_A 0xe94 1645#define RTX_POWER_AFTER_IQK_A 0xe9c 1646 1647#define RRX_POWER_BEFORE_IQK_A 0xea0 1648#define RRX_POWER_BEFORE_IQK_A_2 0xea4 1649#define RRX_POWER_AFTER_IQK_A 0xea8 1650#define RRX_POWER_AFTER_IQK_A_2 0xeac 1651 1652#define RTX_POWER_BEFORE_IQK_B 0xeb4 1653#define RTX_POWER_AFTER_IQK_B 0xebc 1654 1655#define RRX_POER_BEFORE_IQK_B 0xec0 1656#define RRX_POER_BEFORE_IQK_B_2 0xec4 1657#define RRX_POWER_AFTER_IQK_B 0xec8 1658#define RRX_POWER_AFTER_IQK_B_2 0xecc 1659 1660#define RRX_OFDM 0xed0 1661#define RRX_WAIT_RIFS 0xed4 1662#define RRX_TO_RX 0xed8 1663#define RSTANDBY 0xedc 1664#define RSLEEP 0xee0 1665#define RPMPD_ANAEN 0xeec 1666 1667#define RZEBRA1_HSSIENABLE 0x0 1668#define RZEBRA1_TRXENABLE1 0x1 1669#define RZEBRA1_TRXENABLE2 0x2 1670#define RZEBRA1_AGC 0x4 1671#define RZEBRA1_CHARGEPUMP 0x5 1672#define RZEBRA1_CHANNEL 0x7 1673 1674#define RZEBRA1_TXGAIN 0x8 1675#define RZEBRA1_TXLPF 0x9 1676#define RZEBRA1_RXLPF 0xb 1677#define RZEBRA1_RXHPFCORNER 0xc 1678 1679#define RGLOBALCTRL 0 1680#define RRTL8256_TXLPF 19 1681#define RRTL8256_RXLPF 11 1682#define RRTL8258_TXLPF 0x11 1683#define RRTL8258_RXLPF 0x13 1684#define RRTL8258_RSSILPF 0xa 1685 1686#define RF_AC 0x00 1687 1688#define RF_IQADJ_G1 0x01 1689#define RF_IQADJ_G2 0x02 1690#define RF_POW_TRSW 0x05 1691 1692#define RF_GAIN_RX 0x06 1693#define RF_GAIN_TX 0x07 1694 1695#define RF_TXM_IDAC 0x08 1696#define RF_BS_IQGEN 0x0F 1697 1698#define RF_MODE1 0x10 1699#define RF_MODE2 0x11 1700 1701#define RF_RX_AGC_HP 0x12 1702#define RF_TX_AGC 0x13 1703#define RF_BIAS 0x14 1704#define RF_IPA 0x15 1705#define RF_POW_ABILITY 0x17 1706#define RF_MODE_AG 0x18 1707#define RRFCHANNEL 0x18 1708#define RF_CHNLBW 0x18 1709#define RF_TOP 0x19 1710 1711#define RF_RX_G1 0x1A 1712#define RF_RX_G2 0x1B 1713 1714#define RF_RX_BB2 0x1C 1715#define RF_RX_BB1 0x1D 1716 1717#define RF_RCK1 0x1E 1718#define RF_RCK2 0x1F 1719 1720#define RF_TX_G1 0x20 1721#define RF_TX_G2 0x21 1722#define RF_TX_G3 0x22 1723 1724#define RF_TX_BB1 0x23 1725#define RF_T_METER 0x24 1726#define RF_T_METER_88E 0x42 1727#define RF_T_METER_8812A 0x42 1728 1729#define RF_SYN_G1 0x25 1730#define RF_SYN_G2 0x26 1731#define RF_SYN_G3 0x27 1732#define RF_SYN_G4 0x28 1733#define RF_SYN_G5 0x29 1734#define RF_SYN_G6 0x2A 1735#define RF_SYN_G7 0x2B 1736#define RF_SYN_G8 0x2C 1737 1738#define RF_RCK_OS 0x30 1739#define RF_TXPA_G1 0x31 1740#define RF_TXPA_G2 0x32 1741#define RF_TXPA_G3 0x33 1742 1743#define RF_TX_BIAS_A 0x35 1744#define RF_TX_BIAS_D 0x36 1745#define RF_LOBF_9 0x38 1746#define RF_RXRF_A3 0x3C 1747#define RF_TRSW 0x3F 1748 1749#define RF_TXRF_A2 0x41 1750#define RF_TXPA_G4 0x46 1751#define RF_TXPA_A4 0x4B 1752 1753#define RF_APK 0x63 1754 1755#define RF_WE_LUT 0xEF 1756 1757#define BBBRESETB 0x100 1758#define BGLOBALRESETB 0x200 1759#define BOFDMTXSTART 0x4 1760#define BCCKTXSTART 0x8 1761#define BCRC32DEBUG 0x100 1762#define BPMACLOOPBACK 0x10 1763#define BTXLSIG 0xffffff 1764#define BOFDMTXRATE 0xf 1765#define BOFDMTXRESERVED 0x10 1766#define BOFDMTXLENGTH 0x1ffe0 1767#define BOFDMTXPARITY 0x20000 1768#define BTXHTSIG1 0xffffff 1769#define BTXHTMCSRATE 0x7f 1770#define BTXHTBW 0x80 1771#define BTXHTLENGTH 0xffff00 1772#define BTXHTSIG2 0xffffff 1773#define BTXHTSMOOTHING 0x1 1774#define BTXHTSOUNDING 0x2 1775#define BTXHTRESERVED 0x4 1776#define BTXHTAGGREATION 0x8 1777#define BTXHTSTBC 0x30 1778#define BTXHTADVANCECODING 0x40 1779#define BTXHTSHORTGI 0x80 1780#define BTXHTNUMBERHT_LTF 0x300 1781#define BTXHTCRC8 0x3fc00 1782#define BCOUNTERRESET 0x10000 1783#define BNUMOFOFDMTX 0xffff 1784#define BNUMOFCCKTX 0xffff0000 1785#define BTXIDLEINTERVAL 0xffff 1786#define BOFDMSERVICE 0xffff0000 1787#define BTXMACHEADER 0xffffffff 1788#define BTXDATAINIT 0xff 1789#define BTXHTMODE 0x100 1790#define BTXDATATYPE 0x30000 1791#define BTXRANDOMSEED 0xffffffff 1792#define BCCKTXPREAMBLE 0x1 1793#define BCCKTXSFD 0xffff0000 1794#define BCCKTXSIG 0xff 1795#define BCCKTXSERVICE 0xff00 1796#define BCCKLENGTHEXT 0x8000 1797#define BCCKTXLENGHT 0xffff0000 1798#define BCCKTXCRC16 0xffff 1799#define BCCKTXSTATUS 0x1 1800#define BOFDMTXSTATUS 0x2 1801#define IS_BB_REG_OFFSET_92S(__offset) \ 1802 ((__offset >= 0x800) && (__offset <= 0xfff)) 1803 1804#define BRFMOD 0x1 1805#define BJAPANMODE 0x2 1806#define BCCKTXSC 0x30 1807/* Block & Path enable*/ 1808#define ROFDMCCKEN 0x808 1809#define BCCKEN 0x10000000 1810#define BOFDMEN 0x20000000 1811/* Rx antenna*/ 1812#define RRXPATH 0x808 1813#define BRXPATH 0xff 1814/* Tx antenna*/ 1815#define RTXPATH 0x80c 1816#define BTXPATH 0x0fffffff 1817/* for cck rx path selection*/ 1818#define RCCK_RX 0xa04 1819#define BCCK_RX 0x0c000000 1820/* Use LSIG for VHT length*/ 1821#define RVHTLEN_USE_LSIG 0x8c3 1822 1823#define BOFDMRXADCPHASE 0x10000 1824#define BOFDMTXDACPHASE 0x40000 1825#define BXATXAGC 0x3f 1826 1827#define BXBTXAGC 0xf00 1828#define BXCTXAGC 0xf000 1829#define BXDTXAGC 0xf0000 1830 1831#define BPASTART 0xf0000000 1832#define BTRSTART 0x00f00000 1833#define BRFSTART 0x0000f000 1834#define BBBSTART 0x000000f0 1835#define BBBCCKSTART 0x0000000f 1836#define BPAEND 0xf 1837#define BTREND 0x0f000000 1838#define BRFEND 0x000f0000 1839#define BCCAMASK 0x000000f0 1840#define BR2RCCAMASK 0x00000f00 1841#define BHSSI_R2TDELAY 0xf8000000 1842#define BHSSI_T2RDELAY 0xf80000 1843#define BCONTXHSSI 0x400 1844#define BIGFROMCCK 0x200 1845#define BAGCADDRESS 0x3f 1846#define BRXHPTX 0x7000 1847#define BRXHP2RX 0x38000 1848#define BRXHPCCKINI 0xc0000 1849#define BAGCTXCODE 0xc00000 1850#define BAGCRXCODE 0x300000 1851 1852#define B3WIREDATALENGTH 0x800 1853#define B3WIREADDREAALENGTH 0x400 1854 1855#define B3WIRERFPOWERDOWN 0x1 1856#define B5GPAPEPOLARITY 0x40000000 1857#define B2GPAPEPOLARITY 0x80000000 1858#define BRFSW_TXDEFAULTANT 0x3 1859#define BRFSW_TXOPTIONANT 0x30 1860#define BRFSW_RXDEFAULTANT 0x300 1861#define BRFSW_RXOPTIONANT 0x3000 1862#define BRFSI_3WIREDATA 0x1 1863#define BRFSI_3WIRECLOCK 0x2 1864#define BRFSI_3WIRELOAD 0x4 1865#define BRFSI_3WIRERW 0x8 1866#define BRFSI_3WIRE 0xf 1867 1868#define BRFSI_RFENV 0x10 1869 1870#define BRFSI_TRSW 0x20 1871#define BRFSI_TRSWB 0x40 1872#define BRFSI_ANTSW 0x100 1873#define BRFSI_ANTSWB 0x200 1874#define BRFSI_PAPE 0x400 1875#define BRFSI_PAPE5G 0x800 1876#define BBANDSELECT 0x1 1877#define BHTSIG2_GI 0x80 1878#define BHTSIG2_SMOOTHING 0x01 1879#define BHTSIG2_SOUNDING 0x02 1880#define BHTSIG2_AGGREATON 0x08 1881#define BHTSIG2_STBC 0x30 1882#define BHTSIG2_ADVCODING 0x40 1883#define BHTSIG2_NUMOFHTLTF 0x300 1884#define BHTSIG2_CRC8 0x3fc 1885#define BHTSIG1_MCS 0x7f 1886#define BHTSIG1_BANDWIDTH 0x80 1887#define BHTSIG1_HTLENGTH 0xffff 1888#define BLSIG_RATE 0xf 1889#define BLSIG_RESERVED 0x10 1890#define BLSIG_LENGTH 0x1fffe 1891#define BLSIG_PARITY 0x20 1892#define BCCKRXPHASE 0x4 1893 1894#define BLSSIREADADDRESS 0x7f800000 1895#define BLSSIREADEDGE 0x80000000 1896 1897#define BLSSIREADBACKDATA 0xfffff 1898 1899#define BLSSIREADOKFLAG 0x1000 1900#define BCCKSAMPLERATE 0x8 1901#define BREGULATOR0STANDBY 0x1 1902#define BREGULATORPLLSTANDBY 0x2 1903#define BREGULATOR1STANDBY 0x4 1904#define BPLLPOWERUP 0x8 1905#define BDPLLPOWERUP 0x10 1906#define BDA10POWERUP 0x20 1907#define BAD7POWERUP 0x200 1908#define BDA6POWERUP 0x2000 1909#define BXTALPOWERUP 0x4000 1910#define B40MDCLKPOWERUP 0x8000 1911#define BDA6DEBUGMODE 0x20000 1912#define BDA6SWING 0x380000 1913 1914#define BADCLKPHASE 0x4000000 1915#define B80MCLKDELAY 0x18000000 1916#define BAFEWATCHDOGENABLE 0x20000000 1917 1918#define BXTALCAP01 0xc0000000 1919#define BXTALCAP23 0x3 1920#define BXTALCAP92X 0x0f000000 1921#define BXTALCAP 0x0f000000 1922 1923#define BINTDIFCLKENABLE 0x400 1924#define BEXTSIGCLKENABLE 0x800 1925#define BBANDGAP_MBIAS_POWERUP 0x10000 1926#define BAD11SH_GAIN 0xc0000 1927#define BAD11NPUT_RANGE 0x700000 1928#define BAD110P_CURRENT 0x3800000 1929#define BLPATH_LOOPBACK 0x4000000 1930#define BQPATH_LOOPBACK 0x8000000 1931#define BAFE_LOOPBACK 0x10000000 1932#define BDA10_SWING 0x7e0 1933#define BDA10_REVERSE 0x800 1934#define BDA_CLK_SOURCE 0x1000 1935#define BDA7INPUT_RANGE 0x6000 1936#define BDA7_GAIN 0x38000 1937#define BDA7OUTPUT_CM_MODE 0x40000 1938#define BDA7INPUT_CM_MODE 0x380000 1939#define BDA7CURRENT 0xc00000 1940#define BREGULATOR_ADJUST 0x7000000 1941#define BAD11POWERUP_ATTX 0x1 1942#define BDA10PS_ATTX 0x10 1943#define BAD11POWERUP_ATRX 0x100 1944#define BDA10PS_ATRX 0x1000 1945#define BCCKRX_AGC_FORMAT 0x200 1946#define BPSDFFT_SAMPLE_POINT 0xc000 1947#define BPSD_AVERAGE_NUM 0x3000 1948#define BIQPATH_CONTROL 0xc00 1949#define BPSD_FREQ 0x3ff 1950#define BPSD_ANTENNA_PATH 0x30 1951#define BPSD_IQ_SWITCH 0x40 1952#define BPSD_RX_TRIGGER 0x400000 1953#define BPSD_TX_TRIGGER 0x80000000 1954#define BPSD_SINE_TONE_SCALE 0x7f000000 1955#define BPSD_REPORT 0xffff 1956 1957#define BOFDM_TXSC 0x30000000 1958#define BCCK_TXON 0x1 1959#define BOFDM_TXON 0x2 1960#define BDEBUG_PAGE 0xfff 1961#define BDEBUG_ITEM 0xff 1962#define BANTL 0x10 1963#define BANT_NONHT 0x100 1964#define BANT_HT1 0x1000 1965#define BANT_HT2 0x10000 1966#define BANT_HT1S1 0x100000 1967#define BANT_NONHTS1 0x1000000 1968 1969#define BCCK_BBMODE 0x3 1970#define BCCK_TXPOWERSAVING 0x80 1971#define BCCK_RXPOWERSAVING 0x40 1972 1973#define BCCK_SIDEBAND 0x10 1974 1975#define BCCK_SCRAMBLE 0x8 1976#define BCCK_ANTDIVERSITY 0x8000 1977#define BCCK_CARRIER_RECOVERY 0x4000 1978#define BCCK_TXRATE 0x3000 1979#define BCCK_DCCANCEL 0x0800 1980#define BCCK_ISICANCEL 0x0400 1981#define BCCK_MATCH_FILTER 0x0200 1982#define BCCK_EQUALIZER 0x0100 1983#define BCCK_PREAMBLE_DETECT 0x800000 1984#define BCCK_FAST_FALSECCA 0x400000 1985#define BCCK_CH_ESTSTART 0x300000 1986#define BCCK_CCA_COUNT 0x080000 1987#define BCCK_CS_LIM 0x070000 1988#define BCCK_BIST_MODE 0x80000000 1989#define BCCK_CCAMASK 0x40000000 1990#define BCCK_TX_DAC_PHASE 0x4 1991#define BCCK_RX_ADC_PHASE 0x20000000 1992#define BCCKR_CP_MODE 0x0100 1993#define BCCK_TXDC_OFFSET 0xf0 1994#define BCCK_RXDC_OFFSET 0xf 1995#define BCCK_CCA_MODE 0xc000 1996#define BCCK_FALSECS_LIM 0x3f00 1997#define BCCK_CS_RATIO 0xc00000 1998#define BCCK_CORGBIT_SEL 0x300000 1999#define BCCK_PD_LIM 0x0f0000 2000#define BCCK_NEWCCA 0x80000000
2001#define BCCK_RXHP_OF_IG 0x8000 2002#define BCCK_RXIG 0x7f00 2003#define BCCK_LNA_POLARITY 0x800000 2004#define BCCK_RX1ST_BAIN 0x7f0000 2005#define BCCK_RF_EXTEND 0x20000000 2006#define BCCK_RXAGC_SATLEVEL 0x1f000000 2007#define BCCK_RXAGC_SATCOUNT 0xe0 2008#define BCCKRXRFSETTLE 0x1f 2009#define BCCK_FIXED_RXAGC 0x8000 2010#define BCCK_ANTENNA_POLARITY 0x2000 2011#define BCCK_TXFILTER_TYPE 0x0c00 2012#define BCCK_RXAGC_REPORTTYPE 0x0300 2013#define BCCK_RXDAGC_EN 0x80000000 2014#define BCCK_RXDAGC_PERIOD 0x20000000 2015#define BCCK_RXDAGC_SATLEVEL 0x1f000000 2016#define BCCK_TIMING_RECOVERY 0x800000 2017#define BCCK_TXC0 0x3f0000 2018#define BCCK_TXC1 0x3f000000 2019#define BCCK_TXC2 0x3f 2020#define BCCK_TXC3 0x3f00 2021#define BCCK_TXC4 0x3f0000 2022#define BCCK_TXC5 0x3f000000 2023#define BCCK_TXC6 0x3f 2024#define BCCK_TXC7 0x3f00 2025#define BCCK_DEBUGPORT 0xff0000 2026#define BCCK_DAC_DEBUG 0x0f000000 2027#define BCCK_FALSEALARM_ENABLE 0x8000 2028#define BCCK_FALSEALARM_READ 0x4000 2029#define BCCK_TRSSI 0x7f 2030#define BCCK_RXAGC_REPORT 0xfe 2031#define BCCK_RXREPORT_ANTSEL 0x80000000 2032#define BCCK_RXREPORT_MFOFF 0x40000000 2033#define BCCK_RXREPORT_SQLOSS 0x20000000 2034#define BCCK_RXREPORT_PKTLOSS 0x10000000 2035#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 2036#define BCCK_RXREPORT_RATEERROR 0x04000000 2037#define BCCK_RXREPORT_RXRATE 0x03000000 2038#define BCCK_RXFA_COUNTER_LOWER 0xff 2039#define BCCK_RXFA_COUNTER_UPPER 0xff000000 2040#define BCCK_RXHPAGC_START 0xe000 2041#define BCCK_RXHPAGC_FINAL 0x1c00 2042#define BCCK_RXFALSEALARM_ENABLE 0x8000 2043#define BCCK_FACOUNTER_FREEZE 0x4000 2044#define BCCK_TXPATH_SEL 0x10000000 2045#define BCCK_DEFAULT_RXPATH 0xc000000 2046#define BCCK_OPTION_RXPATH 0x3000000 2047 2048#define BNUM_OFSTF 0x3 2049#define BSHIFT_L 0xc0 2050#define BGI_TH 0xc 2051#define BRXPATH_A 0x1 2052#define BRXPATH_B 0x2 2053#define BRXPATH_C 0x4 2054#define BRXPATH_D 0x8 2055#define BTXPATH_A 0x1 2056#define BTXPATH_B 0x2 2057#define BTXPATH_C 0x4 2058#define BTXPATH_D 0x8 2059#define BTRSSI_FREQ 0x200 2060#define BADC_BACKOFF 0x3000 2061#define BDFIR_BACKOFF 0xc000 2062#define BTRSSI_LATCH_PHASE 0x10000 2063#define BRX_LDC_OFFSET 0xff 2064#define BRX_QDC_OFFSET 0xff00 2065#define BRX_DFIR_MODE 0x1800000 2066#define BRX_DCNF_TYPE 0xe000000 2067#define BRXIQIMB_A 0x3ff 2068#define BRXIQIMB_B 0xfc00 2069#define BRXIQIMB_C 0x3f0000 2070#define BRXIQIMB_D 0xffc00000 2071#define BDC_DC_NOTCH 0x60000 2072#define BRXNB_NOTCH 0x1f000000 2073#define BPD_TH 0xf 2074#define BPD_TH_OPT2 0xc000 2075#define BPWED_TH 0x700 2076#define BIFMF_WIN_L 0x800 2077#define BPD_OPTION 0x1000 2078#define BMF_WIN_L 0xe000 2079#define BBW_SEARCH_L 0x30000 2080#define BWIN_ENH_L 0xc0000 2081#define BBW_TH 0x700000 2082#define BED_TH2 0x3800000 2083#define BBW_OPTION 0x4000000 2084#define BRADIO_TH 0x18000000 2085#define BWINDOW_L 0xe0000000 2086#define BSBD_OPTION 0x1 2087#define BFRAME_TH 0x1c 2088#define BFS_OPTION 0x60 2089#define BDC_SLOPE_CHECK 0x80 2090#define BFGUARD_COUNTER_DC_L 0xe00 2091#define BFRAME_WEIGHT_SHORT 0x7000 2092#define BSUB_TUNE 0xe00000 2093#define BFRAME_DC_LENGTH 0xe000000 2094#define BSBD_START_OFFSET 0x30000000 2095#define BFRAME_TH_2 0x7 2096#define BFRAME_GI2_TH 0x38 2097#define BGI2_SYNC_EN 0x40 2098#define BSARCH_SHORT_EARLY 0x300 2099#define BSARCH_SHORT_LATE 0xc00 2100#define BSARCH_GI2_LATE 0x70000 2101#define BCFOANTSUM 0x1 2102#define BCFOACC 0x2 2103#define BCFOSTARTOFFSET 0xc 2104#define BCFOLOOPBACK 0x70 2105#define BCFOSUMWEIGHT 0x80 2106#define BDAGCENABLE 0x10000 2107#define BTXIQIMB_A 0x3ff 2108#define BTXIQIMB_b 0xfc00 2109#define BTXIQIMB_C 0x3f0000 2110#define BTXIQIMB_D 0xffc00000 2111#define BTXIDCOFFSET 0xff 2112#define BTXIQDCOFFSET 0xff00 2113#define BTXDFIRMODE 0x10000 2114#define BTXPESUDO_NOISEON 0x4000000 2115#define BTXPESUDO_NOISE_A 0xff 2116#define BTXPESUDO_NOISE_B 0xff00 2117#define BTXPESUDO_NOISE_C 0xff0000 2118#define BTXPESUDO_NOISE_D 0xff000000 2119#define BCCA_DROPOPTION 0x20000 2120#define BCCA_DROPTHRES 0xfff00000 2121#define BEDCCA_H 0xf 2122#define BEDCCA_L 0xf0 2123#define BLAMBDA_ED 0x300 2124#define BRX_INITIALGAIN 0x7f 2125#define BRX_ANTDIV_EN 0x80 2126#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 2127#define BRX_HIGHPOWER_FLOW 0x8000 2128#define BRX_AGC_FREEZE_THRES 0xc0000 2129#define BRX_FREEZESTEP_AGC1 0x300000 2130#define BRX_FREEZESTEP_AGC2 0xc00000 2131#define BRX_FREEZESTEP_AGC3 0x3000000 2132#define BRX_FREEZESTEP_AGC0 0xc000000 2133#define BRXRSSI_CMP_EN 0x10000000 2134#define BRXQUICK_AGCEN 0x20000000 2135#define BRXAGC_FREEZE_THRES_MODE 0x40000000 2136#define BRX_OVERFLOW_CHECKTYPE 0x80000000 2137#define BRX_AGCSHIFT 0x7f 2138#define BTRSW_TRI_ONLY 0x80 2139#define BPOWER_THRES 0x300 2140#define BRXAGC_EN 0x1 2141#define BRXAGC_TOGETHER_EN 0x2 2142#define BRXAGC_MIN 0x4 2143#define BRXHP_INI 0x7 2144#define BRXHP_TRLNA 0x70 2145#define BRXHP_RSSI 0x700 2146#define BRXHP_BBP1 0x7000 2147#define BRXHP_BBP2 0x70000 2148#define BRXHP_BBP3 0x700000 2149#define BRSSI_H 0x7f0000 2150#define BRSSI_GEN 0x7f000000 2151#define BRXSETTLE_TRSW 0x7 2152#define BRXSETTLE_LNA 0x38 2153#define BRXSETTLE_RSSI 0x1c0 2154#define BRXSETTLE_BBP 0xe00 2155#define BRXSETTLE_RXHP 0x7000 2156#define BRXSETTLE_ANTSW_RSSI 0x38000 2157#define BRXSETTLE_ANTSW 0xc0000 2158#define BRXPROCESS_TIME_DAGC 0x300000 2159#define BRXSETTLE_HSSI 0x400000 2160#define BRXPROCESS_TIME_BBPPW 0x800000 2161#define BRXANTENNA_POWER_SHIFT 0x3000000 2162#define BRSSI_TABLE_SELECT 0xc000000 2163#define BRXHP_FINAL 0x7000000 2164#define BRXHPSETTLE_BBP 0x7 2165#define BRXHTSETTLE_HSSI 0x8 2166#define BRXHTSETTLE_RXHP 0x70 2167#define BRXHTSETTLE_BBPPW 0x80 2168#define BRXHTSETTLE_IDLE 0x300 2169#define BRXHTSETTLE_RESERVED 0x1c00 2170#define BRXHT_RXHP_EN 0x8000 2171#define BRXAGC_FREEZE_THRES 0x30000 2172#define BRXAGC_TOGETHEREN 0x40000 2173#define BRXHTAGC_MIN 0x80000 2174#define BRXHTAGC_EN 0x100000 2175#define BRXHTDAGC_EN 0x200000 2176#define BRXHT_RXHP_BBP 0x1c00000 2177#define BRXHT_RXHP_FINAL 0xe0000000 2178#define BRXPW_RADIO_TH 0x3 2179#define BRXPW_RADIO_EN 0x4 2180#define BRXMF_HOLD 0x3800 2181#define BRXPD_DELAY_TH1 0x38 2182#define BRXPD_DELAY_TH2 0x1c0 2183#define BRXPD_DC_COUNT_MAX 0x600 2184#define BRXPD_DELAY_TH 0x8000 2185#define BRXPROCESS_DELAY 0xf0000 2186#define BRXSEARCHRANGE_GI2_EARLY 0x700000 2187#define BRXFRAME_FUARD_COUNTER_L 0x3800000 2188#define BRXSGI_GUARD_L 0xc000000 2189#define BRXSGI_SEARCH_L 0x30000000 2190#define BRXSGI_TH 0xc0000000 2191#define BDFSCNT0 0xff 2192#define BDFSCNT1 0xff00 2193#define BDFSFLAG 0xf0000 2194#define BMF_WEIGHT_SUM 0x300000 2195#define BMINIDX_TH 0x7f000000 2196#define BDAFORMAT 0x40000 2197#define BTXCH_EMU_ENABLE 0x01000000 2198#define BTRSW_ISOLATION_A 0x7f 2199#define BTRSW_ISOLATION_B 0x7f00 2200#define BTRSW_ISOLATION_C 0x7f0000 2201#define BTRSW_ISOLATION_D 0x7f000000 2202#define BEXT_LNA_GAIN 0x7c00 2203 2204#define BSTBC_EN 0x4 2205#define BANTENNA_MAPPING 0x10 2206#define BNSS 0x20 2207#define BCFO_ANTSUM_ID 0x200 2208#define BPHY_COUNTER_RESET 0x8000000 2209#define BCFO_REPORT_GET 0x4000000 2210#define BOFDM_CONTINUE_TX 0x10000000 2211#define BOFDM_SINGLE_CARRIER 0x20000000 2212#define BOFDM_SINGLE_TONE 0x40000000 2213#define BHT_DETECT 0x100 2214#define BCFOEN 0x10000 2215#define BCFOVALUE 0xfff00000 2216#define BSIGTONE_RE 0x3f 2217#define BSIGTONE_IM 0x7f00 2218#define BCOUNTER_CCA 0xffff 2219#define BCOUNTER_PARITYFAIL 0xffff0000 2220#define BCOUNTER_RATEILLEGAL 0xffff 2221#define BCOUNTER_CRC8FAIL 0xffff0000 2222#define BCOUNTER_MCSNOSUPPORT 0xffff 2223#define BCOUNTER_FASTSYNC 0xffff 2224#define BSHORTCFO 0xfff 2225#define BSHORTCFOT_LENGTH 12 2226#define BSHORTCFOF_LENGTH 11 2227#define BLONGCFO 0x7ff 2228#define BLONGCFOT_LENGTH 11 2229#define BLONGCFOF_LENGTH 11 2230#define BTAILCFO 0x1fff 2231#define BTAILCFOT_LENGTH 13 2232#define BTAILCFOF_LENGTH 12 2233#define BNOISE_EN_PWDB 0xffff 2234#define BCC_POWER_DB 0xffff0000 2235#define BMOISE_PWDB 0xffff 2236#define BPOWERMEAST_LENGTH 10 2237#define BPOWERMEASF_LENGTH 3 2238#define BRX_HT_BW 0x1 2239#define BRXSC 0x6 2240#define BRX_HT 0x8 2241#define BNB_INTF_DET_ON 0x1 2242#define BINTF_WIN_LEN_CFG 0x30 2243#define BNB_INTF_TH_CFG 0x1c0 2244#define BRFGAIN 0x3f 2245#define BTABLESEL 0x40 2246#define BTRSW 0x80 2247#define BRXSNR_A 0xff 2248#define BRXSNR_B 0xff00 2249#define BRXSNR_C 0xff0000 2250#define BRXSNR_D 0xff000000 2251#define BSNR_EVMT_LENGTH 8 2252#define BSNR_EVMF_LENGTH 1 2253#define BCSI1ST 0xff 2254#define BCSI2ND 0xff00 2255#define BRXEVM1ST 0xff0000 2256#define BRXEVM2ND 0xff000000 2257#define BSIGEVM 0xff 2258#define BPWDB 0xff00 2259#define BSGIEN 0x10000 2260 2261#define BSFACTOR_QMA1 0xf 2262#define BSFACTOR_QMA2 0xf0 2263#define BSFACTOR_QMA3 0xf00 2264#define BSFACTOR_QMA4 0xf000 2265#define BSFACTOR_QMA5 0xf0000 2266#define BSFACTOR_QMA6 0xf0000 2267#define BSFACTOR_QMA7 0xf00000 2268#define BSFACTOR_QMA8 0xf000000 2269#define BSFACTOR_QMA9 0xf0000000 2270#define BCSI_SCHEME 0x100000 2271 2272#define BNOISE_LVL_TOP_SET 0x3 2273#define BCHSMOOTH 0x4 2274#define BCHSMOOTH_CFG1 0x38 2275#define BCHSMOOTH_CFG2 0x1c0 2276#define BCHSMOOTH_CFG3 0xe00 2277#define BCHSMOOTH_CFG4 0x7000 2278#define BMRCMODE 0x800000 2279#define BTHEVMCFG 0x7000000 2280 2281#define BLOOP_FIT_TYPE 0x1 2282#define BUPD_CFO 0x40 2283#define BUPD_CFO_OFFDATA 0x80 2284#define BADV_UPD_CFO 0x100 2285#define BADV_TIME_CTRL 0x800 2286#define BUPD_CLKO 0x1000 2287#define BFC 0x6000 2288#define BTRACKING_MODE 0x8000 2289#define BPHCMP_ENABLE 0x10000 2290#define BUPD_CLKO_LTF 0x20000 2291#define BCOM_CH_CFO 0x40000 2292#define BCSI_ESTI_MODE 0x80000 2293#define BADV_UPD_EQZ 0x100000 2294#define BUCHCFG 0x7000000 2295#define BUPDEQZ 0x8000000 2296 2297#define BRX_PESUDO_NOISE_ON 0x20000000 2298#define BRX_PESUDO_NOISE_A 0xff 2299#define BRX_PESUDO_NOISE_B 0xff00 2300#define BRX_PESUDO_NOISE_C 0xff0000 2301#define BRX_PESUDO_NOISE_D 0xff000000 2302#define BRX_PESUDO_NOISESTATE_A 0xffff 2303#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2304#define BRX_PESUDO_NOISESTATE_C 0xffff 2305#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2306 2307#define BZEBRA1_HSSIENABLE 0x8 2308#define BZEBRA1_TRXCONTROL 0xc00 2309#define BZEBRA1_TRXGAINSETTING 0x07f 2310#define BZEBRA1_RXCOUNTER 0xc00 2311#define BZEBRA1_TXCHANGEPUMP 0x38 2312#define BZEBRA1_RXCHANGEPUMP 0x7 2313#define BZEBRA1_CHANNEL_NUM 0xf80 2314#define BZEBRA1_TXLPFBW 0x400 2315#define BZEBRA1_RXLPFBW 0x600 2316 2317#define BRTL8256REG_MODE_CTRL1 0x100 2318#define BRTL8256REG_MODE_CTRL0 0x40 2319#define BRTL8256REG_TXLPFBW 0x18 2320#define BRTL8256REG_RXLPFBW 0x600 2321 2322#define BRTL8258_TXLPFBW 0xc 2323#define BRTL8258_RXLPFBW 0xc00 2324#define BRTL8258_RSSILPFBW 0xc0 2325 2326#define BBYTE0 0x1 2327#define BBYTE1 0x2 2328#define BBYTE2 0x4 2329#define BBYTE3 0x8 2330#define BWORD0 0x3 2331#define BWORD1 0xc 2332#define BWORD 0xf 2333 2334#define MASKBYTE0 0xff 2335#define MASKBYTE1 0xff00 2336#define MASKBYTE2 0xff0000 2337#define MASKBYTE3 0xff000000 2338#define MASKHWORD 0xffff0000 2339#define MASKLWORD 0x0000ffff 2340#define MASKDWORD 0xffffffff 2341#define MASK12BITS 0xfff 2342#define MASKH4BITS 0xf0000000 2343#define MASKOFDM_D 0xffc00000 2344#define MASKCCK 0x3f3f3f3f 2345 2346#define MASK4BITS 0x0f 2347#define MASK20BITS 0xfffff 2348#define RFREG_OFFSET_MASK 0xfffff 2349 2350#define BENABLE 0x1 2351#define BDISABLE 0x0 2352 2353#define LEFT_ANTENNA 0x0 2354#define RIGHT_ANTENNA 0x1 2355 2356#define TCHECK_TXSTATUS 500 2357#define TUPDATE_RXCOUNTER 100 2358 2359#define REG_UN_used_register 0x01bf 2360 2361/* Path_A RFE cotrol pinmux*/ 2362#define RA_RFE_PINMUX 0xcb0 2363/* Path_B RFE control pinmux*/ 2364#define RB_RFE_PINMUX 0xeb0 2365 2366#define RA_RFE_INV 0xcb4 2367#define RB_RFE_INV 0xeb4 2368 2369/* RXIQC */ 2370/*RxIQ imblance matrix coeff. A & B*/ 2371#define RA_RXIQC_AB 0xc10 2372/*RxIQ imblance matrix coeff. C & D*/ 2373#define RA_RXIQC_CD 0xc14 2374/* Pah_A TX scaling factor*/ 2375#define RA_TXSCALE 0xc1c 2376/* Path_B TX scaling factor*/ 2377#define RB_TXSCALE 0xe1c 2378/*RxIQ imblance matrix coeff. A & B*/ 2379#define RB_RXIQC_AB 0xe10 2380/*RxIQ imblance matrix coeff. C & D*/ 2381#define RB_RXIQC_CD 0xe14 2382/*bit mask for IQC matrix element A & C*/ 2383#define RXIQC_AC 0x02ff 2384 /*bit mask for IQC matrix element A & C*/ 2385#define RXIQC_BD 0x02ff0000 2386 2387/* 2 EFUSE_TEST (For RTL8723 partially) */ 2388#define EFUSE_SEL(x) (((x) & 0x3) << 8) 2389#define EFUSE_SEL_MASK 0x300 2390#define EFUSE_WIFI_SEL_0 0x0 2391 2392/*REG_MULTI_FUNC_CTRL(For RTL8723 Only)*/ 2393/* Enable GPIO[9] as WiFi HW PDn source*/ 2394#define WL_HWPDN_EN BIT(0) 2395/* WiFi HW PDn polarity control*/ 2396#define WL_HWPDN_SL BIT(1) 2397/* WiFi function enable */ 2398#define WL_FUNC_EN BIT(2) 2399/* Enable GPIO[9] as WiFi RF HW PDn source */ 2400#define WL_HWROF_EN BIT(3) 2401/* Enable GPIO[11] as BT HW PDn source */ 2402#define BT_HWPDN_EN BIT(16) 2403/* BT HW PDn polarity control */ 2404#define BT_HWPDN_SL BIT(17) 2405/* BT function enable */ 2406#define BT_FUNC_EN BIT(18) 2407/* Enable GPIO[11] as BT/GPS RF HW PDn source */ 2408#define BT_HWROF_EN BIT(19) 2409/* Enable GPIO[10] as GPS HW PDn source */ 2410#define GPS_HWPDN_EN BIT(20) 2411/* GPS HW PDn polarity control */ 2412#define GPS_HWPDN_SL BIT(21) 2413/* GPS function enable */ 2414#define GPS_FUNC_EN BIT(22) 2415 2416#define BMASKBYTE0 0xff 2417#define BMASKBYTE1 0xff00 2418#define BMASKBYTE2 0xff0000 2419#define BMASKBYTE3 0xff000000 2420#define BMASKHWORD 0xffff0000 2421#define BMASKLWORD 0x0000ffff 2422#define BMASKDWORD 0xffffffff 2423#define BMASK12BITS 0xfff 2424#define BMASKH4BITS 0xf0000000 2425#define BMASKOFDM_D 0xffc00000 2426#define BMASKCCK 0x3f3f3f3f 2427#define BMASKRFEINV 0x3ff00000 2428 2429#define BRFREGOFFSETMASK 0xfffff 2430 2431#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 2432#define ODM_REG_BB_RX_PATH_11AC 0x808 2433/*PAGE 9*/ 2434#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 2435/*PAGE A*/ 2436#define ODM_REG_CCK_CCA_11AC 0xA0A 2437#define ODM_REG_CCK_FA_RST_11AC 0xA2C 2438#define ODM_REG_CCK_FA_11AC 0xA5C 2439/*PAGE C*/ 2440#define ODM_REG_IGI_A_11AC 0xC50 2441/*PAGE E*/ 2442#define ODM_REG_IGI_B_11AC 0xE50 2443/*PAGE F*/ 2444#define ODM_REG_OFDM_FA_11AC 0xF48 2445 2446/* 2 MAC REG LIST */ 2447 2448/* DIG Related */ 2449#define ODM_BIT_IGI_11AC 0xFFFFFFFF 2450#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16 2451#define ODM_BIT_BB_RX_PATH_11AC 0xF 2452 2453enum AGGRE_SIZE { 2454 HT_AGG_SIZE_8K = 0, 2455 HT_AGG_SIZE_16K = 1, 2456 HT_AGG_SIZE_32K = 2, 2457 HT_AGG_SIZE_64K = 3, 2458 VHT_AGG_SIZE_128K = 4, 2459 VHT_AGG_SIZE_256K = 5, 2460 VHT_AGG_SIZE_512K = 6, 2461 VHT_AGG_SIZE_1024K = 7, 2462}; 2463 2464#define REG_AMPDU_MAX_LENGTH_8812 0x0458 2465 2466#endif 2467