1/* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2012 Intel Corporation. All rights reserved. 8 * Copyright (C) 2015 EMC Corporation. All Rights Reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * BSD LICENSE 15 * 16 * Copyright(c) 2012 Intel Corporation. All rights reserved. 17 * Copyright (C) 2015 EMC Corporation. All Rights Reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 23 * * Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * * Redistributions in binary form must reproduce the above copy 26 * notice, this list of conditions and the following disclaimer in 27 * the documentation and/or other materials provided with the 28 * distribution. 29 * * Neither the name of Intel Corporation nor the names of its 30 * contributors may be used to endorse or promote products derived 31 * from this software without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 44 * 45 * Intel PCIe NTB Linux driver 46 * 47 * Contact Information: 48 * Jon Mason <jon.mason@intel.com> 49 */ 50 51#ifndef NTB_HW_INTEL_H 52#define NTB_HW_INTEL_H 53 54#include <linux/ntb.h> 55#include <linux/pci.h> 56 57#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725 58#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726 59#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727 60#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D 61#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E 62#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F 63#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D 64#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E 65#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F 66#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D 67#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E 68#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F 69#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E 70#define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D 71#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E 72#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F 73#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C 74 75/* Intel Xeon hardware */ 76 77#define XEON_PBAR23LMT_OFFSET 0x0000 78#define XEON_PBAR45LMT_OFFSET 0x0008 79#define XEON_PBAR4LMT_OFFSET 0x0008 80#define XEON_PBAR5LMT_OFFSET 0x000c 81#define XEON_PBAR23XLAT_OFFSET 0x0010 82#define XEON_PBAR45XLAT_OFFSET 0x0018 83#define XEON_PBAR4XLAT_OFFSET 0x0018 84#define XEON_PBAR5XLAT_OFFSET 0x001c 85#define XEON_SBAR23LMT_OFFSET 0x0020 86#define XEON_SBAR45LMT_OFFSET 0x0028 87#define XEON_SBAR4LMT_OFFSET 0x0028 88#define XEON_SBAR5LMT_OFFSET 0x002c 89#define XEON_SBAR23XLAT_OFFSET 0x0030 90#define XEON_SBAR45XLAT_OFFSET 0x0038 91#define XEON_SBAR4XLAT_OFFSET 0x0038 92#define XEON_SBAR5XLAT_OFFSET 0x003c 93#define XEON_SBAR0BASE_OFFSET 0x0040 94#define XEON_SBAR23BASE_OFFSET 0x0048 95#define XEON_SBAR45BASE_OFFSET 0x0050 96#define XEON_SBAR4BASE_OFFSET 0x0050 97#define XEON_SBAR5BASE_OFFSET 0x0054 98#define XEON_SBDF_OFFSET 0x005c 99#define XEON_NTBCNTL_OFFSET 0x0058 100#define XEON_PDOORBELL_OFFSET 0x0060 101#define XEON_PDBMSK_OFFSET 0x0062 102#define XEON_SDOORBELL_OFFSET 0x0064 103#define XEON_SDBMSK_OFFSET 0x0066 104#define XEON_USMEMMISS_OFFSET 0x0070 105#define XEON_SPAD_OFFSET 0x0080 106#define XEON_PBAR23SZ_OFFSET 0x00d0 107#define XEON_PBAR45SZ_OFFSET 0x00d1 108#define XEON_PBAR4SZ_OFFSET 0x00d1 109#define XEON_SBAR23SZ_OFFSET 0x00d2 110#define XEON_SBAR45SZ_OFFSET 0x00d3 111#define XEON_SBAR4SZ_OFFSET 0x00d3 112#define XEON_PPD_OFFSET 0x00d4 113#define XEON_PBAR5SZ_OFFSET 0x00d5 114#define XEON_SBAR5SZ_OFFSET 0x00d6 115#define XEON_WCCNTRL_OFFSET 0x00e0 116#define XEON_UNCERRSTS_OFFSET 0x014c 117#define XEON_CORERRSTS_OFFSET 0x0158 118#define XEON_LINK_STATUS_OFFSET 0x01a2 119#define XEON_SPCICMD_OFFSET 0x0504 120#define XEON_DEVCTRL_OFFSET 0x0598 121#define XEON_DEVSTS_OFFSET 0x059a 122#define XEON_SLINK_STATUS_OFFSET 0x05a2 123#define XEON_B2B_SPAD_OFFSET 0x0100 124#define XEON_B2B_DOORBELL_OFFSET 0x0140 125#define XEON_B2B_XLAT_OFFSETL 0x0144 126#define XEON_B2B_XLAT_OFFSETU 0x0148 127#define XEON_PPD_CONN_MASK 0x03 128#define XEON_PPD_CONN_TRANSPARENT 0x00 129#define XEON_PPD_CONN_B2B 0x01 130#define XEON_PPD_CONN_RP 0x02 131#define XEON_PPD_DEV_MASK 0x10 132#define XEON_PPD_DEV_USD 0x00 133#define XEON_PPD_DEV_DSD 0x10 134#define XEON_PPD_SPLIT_BAR_MASK 0x40 135 136#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK) 137#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD) 138#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD) 139#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD) 140#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD) 141#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD) 142#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD) 143 144#define XEON_MW_COUNT 2 145#define HSX_SPLIT_BAR_MW_COUNT 3 146#define XEON_DB_COUNT 15 147#define XEON_DB_LINK 15 148#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK) 149#define XEON_DB_MSIX_VECTOR_COUNT 4 150#define XEON_DB_MSIX_VECTOR_SHIFT 5 151#define XEON_DB_TOTAL_SHIFT 16 152#define XEON_SPAD_COUNT 16 153 154/* Intel Skylake Xeon hardware */ 155#define SKX_IMBAR1SZ_OFFSET 0x00d0 156#define SKX_IMBAR2SZ_OFFSET 0x00d1 157#define SKX_EMBAR1SZ_OFFSET 0x00d2 158#define SKX_EMBAR2SZ_OFFSET 0x00d3 159#define SKX_DEVCTRL_OFFSET 0x0098 160#define SKX_DEVSTS_OFFSET 0x009a 161#define SKX_UNCERRSTS_OFFSET 0x014c 162#define SKX_CORERRSTS_OFFSET 0x0158 163#define SKX_LINK_STATUS_OFFSET 0x01a2 164 165#define SKX_NTBCNTL_OFFSET 0x0000 166#define SKX_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */ 167#define SKX_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */ 168#define SKX_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */ 169#define SKX_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */ 170#define SKX_IM_INT_STATUS_OFFSET 0x0040 171#define SKX_IM_INT_DISABLE_OFFSET 0x0048 172#define SKX_IM_SPAD_OFFSET 0x0080 /* SPAD */ 173#define SKX_USMEMMISS_OFFSET 0x0070 174#define SKX_INTVEC_OFFSET 0x00d0 175#define SKX_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */ 176#define SKX_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */ 177#define SKX_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */ 178#define SKX_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */ 179#define SKX_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */ 180#define SKX_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */ 181#define SKX_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */ 182#define SKX_EM_INT_STATUS_OFFSET 0x4040 183#define SKX_EM_INT_DISABLE_OFFSET 0x4048 184#define SKX_EM_SPAD_OFFSET 0x4080 /* remote SPAD */ 185#define SKX_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */ 186#define SKX_SPCICMD_OFFSET 0x4504 /* SPCICMD */ 187#define SKX_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */ 188#define SKX_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */ 189#define SKX_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */ 190 191#define SKX_DB_COUNT 32 192#define SKX_DB_LINK 32 193#define SKX_DB_LINK_BIT BIT_ULL(SKX_DB_LINK) 194#define SKX_DB_MSIX_VECTOR_COUNT 33 195#define SKX_DB_MSIX_VECTOR_SHIFT 1 196#define SKX_DB_TOTAL_SHIFT 33 197#define SKX_SPAD_COUNT 16 198 199/* Intel Atom hardware */ 200 201#define ATOM_SBAR2XLAT_OFFSET 0x0008 202#define ATOM_PDOORBELL_OFFSET 0x0020 203#define ATOM_PDBMSK_OFFSET 0x0028 204#define ATOM_NTBCNTL_OFFSET 0x0060 205#define ATOM_SPAD_OFFSET 0x0080 206#define ATOM_PPD_OFFSET 0x00d4 207#define ATOM_PBAR2XLAT_OFFSET 0x8008 208#define ATOM_B2B_DOORBELL_OFFSET 0x8020 209#define ATOM_B2B_SPAD_OFFSET 0x8080 210#define ATOM_SPCICMD_OFFSET 0xb004 211#define ATOM_LINK_STATUS_OFFSET 0xb052 212#define ATOM_ERRCORSTS_OFFSET 0xb110 213#define ATOM_IP_BASE 0xc000 214#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024) 215#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180) 216#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040) 217#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324) 218#define ATOM_MODPHY_PCSREG4 0x1c004 219#define ATOM_MODPHY_PCSREG6 0x1c006 220 221#define ATOM_PPD_INIT_LINK 0x0008 222#define ATOM_PPD_CONN_MASK 0x0300 223#define ATOM_PPD_CONN_TRANSPARENT 0x0000 224#define ATOM_PPD_CONN_B2B 0x0100 225#define ATOM_PPD_CONN_RP 0x0200 226#define ATOM_PPD_DEV_MASK 0x1000 227#define ATOM_PPD_DEV_USD 0x0000 228#define ATOM_PPD_DEV_DSD 0x1000 229#define ATOM_PPD_TOPO_MASK (ATOM_PPD_CONN_MASK | ATOM_PPD_DEV_MASK) 230#define ATOM_PPD_TOPO_PRI_USD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_USD) 231#define ATOM_PPD_TOPO_PRI_DSD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_DSD) 232#define ATOM_PPD_TOPO_SEC_USD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_USD) 233#define ATOM_PPD_TOPO_SEC_DSD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_DSD) 234#define ATOM_PPD_TOPO_B2B_USD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_USD) 235#define ATOM_PPD_TOPO_B2B_DSD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_DSD) 236 237#define ATOM_MW_COUNT 2 238#define ATOM_DB_COUNT 34 239#define ATOM_DB_VALID_MASK (BIT_ULL(ATOM_DB_COUNT) - 1) 240#define ATOM_DB_MSIX_VECTOR_COUNT 34 241#define ATOM_DB_MSIX_VECTOR_SHIFT 1 242#define ATOM_DB_TOTAL_SHIFT 34 243#define ATOM_SPAD_COUNT 16 244 245#define ATOM_NTB_CTL_DOWN_BIT BIT(16) 246#define ATOM_NTB_CTL_ACTIVE(x) !(x & ATOM_NTB_CTL_DOWN_BIT) 247 248#define ATOM_DESKEWSTS_DBERR BIT(15) 249#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI BIT(20) 250#define ATOM_LTSSMSTATEJMP_FORCEDETECT BIT(2) 251#define ATOM_IBIST_ERR_OFLOW 0x7FFF7FFF 252 253#define ATOM_LINK_HB_TIMEOUT msecs_to_jiffies(1000) 254#define ATOM_LINK_RECOVERY_TIME msecs_to_jiffies(500) 255 256/* Ntb control and link status */ 257 258#define NTB_CTL_CFG_LOCK BIT(0) 259#define NTB_CTL_DISABLE BIT(1) 260#define NTB_CTL_S2P_BAR2_SNOOP BIT(2) 261#define NTB_CTL_P2S_BAR2_SNOOP BIT(4) 262#define NTB_CTL_S2P_BAR4_SNOOP BIT(6) 263#define NTB_CTL_P2S_BAR4_SNOOP BIT(8) 264#define NTB_CTL_S2P_BAR5_SNOOP BIT(12) 265#define NTB_CTL_P2S_BAR5_SNOOP BIT(14) 266 267#define NTB_LNK_STA_ACTIVE_BIT 0x2000 268#define NTB_LNK_STA_SPEED_MASK 0x000f 269#define NTB_LNK_STA_WIDTH_MASK 0x03f0 270#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT)) 271#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK) 272#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4) 273 274/* Use the following addresses for translation between b2b ntb devices in case 275 * the hardware default values are not reliable. */ 276#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull 277#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull 278#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull 279#define XEON_B2B_BAR4_ADDR32 0x20000000u 280#define XEON_B2B_BAR5_ADDR32 0x40000000u 281 282/* The peer ntb secondary config space is 32KB fixed size */ 283#define XEON_B2B_MIN_SIZE 0x8000 284 285/* flags to indicate hardware errata */ 286#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0) 287#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1) 288#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2) 289#define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3) 290 291/* flags to indicate unsafe api */ 292#define NTB_UNSAFE_DB BIT_ULL(0) 293#define NTB_UNSAFE_SPAD BIT_ULL(1) 294 295#define NTB_BAR_MASK_64 ~(0xfull) 296#define NTB_BAR_MASK_32 ~(0xfu) 297 298struct intel_ntb_dev; 299 300struct intel_ntb_reg { 301 int (*poll_link)(struct intel_ntb_dev *ndev); 302 int (*link_is_up)(struct intel_ntb_dev *ndev); 303 u64 (*db_ioread)(void __iomem *mmio); 304 void (*db_iowrite)(u64 db_bits, void __iomem *mmio); 305 unsigned long ntb_ctl; 306 resource_size_t db_size; 307 int mw_bar[]; 308}; 309 310struct intel_ntb_alt_reg { 311 unsigned long db_bell; 312 unsigned long db_mask; 313 unsigned long db_clear; 314 unsigned long spad; 315}; 316 317struct intel_ntb_xlat_reg { 318 unsigned long bar0_base; 319 unsigned long bar2_xlat; 320 unsigned long bar2_limit; 321}; 322 323struct intel_b2b_addr { 324 phys_addr_t bar0_addr; 325 phys_addr_t bar2_addr64; 326 phys_addr_t bar4_addr64; 327 phys_addr_t bar4_addr32; 328 phys_addr_t bar5_addr32; 329}; 330 331struct intel_ntb_vec { 332 struct intel_ntb_dev *ndev; 333 int num; 334}; 335 336struct intel_ntb_dev { 337 struct ntb_dev ntb; 338 339 /* offset of peer bar0 in b2b bar */ 340 unsigned long b2b_off; 341 /* mw idx used to access peer bar0 */ 342 unsigned int b2b_idx; 343 344 /* BAR45 is split into BAR4 and BAR5 */ 345 bool bar4_split; 346 347 u32 ntb_ctl; 348 u32 lnk_sta; 349 350 unsigned char mw_count; 351 unsigned char spad_count; 352 unsigned char db_count; 353 unsigned char db_vec_count; 354 unsigned char db_vec_shift; 355 356 u64 db_valid_mask; 357 u64 db_link_mask; 358 u64 db_mask; 359 360 /* synchronize rmw access of db_mask and hw reg */ 361 spinlock_t db_mask_lock; 362 363 struct msix_entry *msix; 364 struct intel_ntb_vec *vec; 365 366 const struct intel_ntb_reg *reg; 367 const struct intel_ntb_alt_reg *self_reg; 368 const struct intel_ntb_alt_reg *peer_reg; 369 const struct intel_ntb_xlat_reg *xlat_reg; 370 void __iomem *self_mmio; 371 void __iomem *peer_mmio; 372 phys_addr_t peer_addr; 373 374 unsigned long last_ts; 375 struct delayed_work hb_timer; 376 377 unsigned long hwerr_flags; 378 unsigned long unsafe_flags; 379 unsigned long unsafe_flags_ignore; 380 381 struct dentry *debugfs_dir; 382 struct dentry *debugfs_info; 383}; 384 385#define ndev_pdev(ndev) ((ndev)->ntb.pdev) 386#define ndev_name(ndev) pci_name(ndev_pdev(ndev)) 387#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev) 388#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb) 389#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \ 390 hb_timer.work) 391 392#endif 393