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15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/bitops.h>
19#include <linux/err.h>
20#include <linux/i2c.h>
21#include <linux/mfd/wm8350/core.h>
22#include <linux/mfd/wm8350/pmic.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/driver.h>
25#include <linux/regulator/machine.h>
26
27
28#define WM8350_DCDC_MAX_VSEL 0x66
29
30
31static const int isink_cur[] = {
32 4,
33 5,
34 6,
35 7,
36 8,
37 10,
38 11,
39 14,
40 16,
41 19,
42 23,
43 27,
44 32,
45 39,
46 46,
47 54,
48 65,
49 77,
50 92,
51 109,
52 130,
53 154,
54 183,
55 218,
56 259,
57 308,
58 367,
59 436,
60 518,
61 616,
62 733,
63 872,
64 1037,
65 1233,
66 1466,
67 1744,
68 2073,
69 2466,
70 2933,
71 3487,
72 4147,
73 4932,
74 5865,
75 6975,
76 8294,
77 9864,
78 11730,
79 13949,
80 16589,
81 19728,
82 23460,
83 27899,
84 33178,
85 39455,
86 46920,
87 55798,
88 66355,
89 78910,
90 93840,
91 111596,
92 132710,
93 157820,
94 187681,
95 223191
96};
97
98static int get_isink_val(int min_uA, int max_uA, u16 *setting)
99{
100 int i;
101
102 for (i = 0; i < ARRAY_SIZE(isink_cur); i++) {
103 if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
104 *setting = i;
105 return 0;
106 }
107 }
108 return -EINVAL;
109}
110
111static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
112 int max_uA)
113{
114 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
115 int isink = rdev_get_id(rdev);
116 u16 val, setting;
117 int ret;
118
119 ret = get_isink_val(min_uA, max_uA, &setting);
120 if (ret != 0)
121 return ret;
122
123 switch (isink) {
124 case WM8350_ISINK_A:
125 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
126 ~WM8350_CS1_ISEL_MASK;
127 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
128 val | setting);
129 break;
130 case WM8350_ISINK_B:
131 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
132 ~WM8350_CS1_ISEL_MASK;
133 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
134 val | setting);
135 break;
136 default:
137 return -EINVAL;
138 }
139
140 return 0;
141}
142
143static int wm8350_isink_get_current(struct regulator_dev *rdev)
144{
145 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
146 int isink = rdev_get_id(rdev);
147 u16 val;
148
149 switch (isink) {
150 case WM8350_ISINK_A:
151 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
152 WM8350_CS1_ISEL_MASK;
153 break;
154 case WM8350_ISINK_B:
155 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
156 WM8350_CS1_ISEL_MASK;
157 break;
158 default:
159 return 0;
160 }
161
162 return isink_cur[val];
163}
164
165
166static int wm8350_isink_enable(struct regulator_dev *rdev)
167{
168 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
169 int isink = rdev_get_id(rdev);
170
171 switch (isink) {
172 case WM8350_ISINK_A:
173 switch (wm8350->pmic.isink_A_dcdc) {
174 case WM8350_DCDC_2:
175 case WM8350_DCDC_5:
176 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
177 WM8350_CS1_ENA);
178 wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
179 WM8350_CS1_DRIVE);
180 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
181 1 << (wm8350->pmic.isink_A_dcdc -
182 WM8350_DCDC_1));
183 break;
184 default:
185 return -EINVAL;
186 }
187 break;
188 case WM8350_ISINK_B:
189 switch (wm8350->pmic.isink_B_dcdc) {
190 case WM8350_DCDC_2:
191 case WM8350_DCDC_5:
192 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
193 WM8350_CS2_ENA);
194 wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
195 WM8350_CS2_DRIVE);
196 wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
197 1 << (wm8350->pmic.isink_B_dcdc -
198 WM8350_DCDC_1));
199 break;
200 default:
201 return -EINVAL;
202 }
203 break;
204 default:
205 return -EINVAL;
206 }
207 return 0;
208}
209
210static int wm8350_isink_disable(struct regulator_dev *rdev)
211{
212 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
213 int isink = rdev_get_id(rdev);
214
215 switch (isink) {
216 case WM8350_ISINK_A:
217 switch (wm8350->pmic.isink_A_dcdc) {
218 case WM8350_DCDC_2:
219 case WM8350_DCDC_5:
220 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
221 1 << (wm8350->pmic.isink_A_dcdc -
222 WM8350_DCDC_1));
223 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
224 WM8350_CS1_ENA);
225 break;
226 default:
227 return -EINVAL;
228 }
229 break;
230 case WM8350_ISINK_B:
231 switch (wm8350->pmic.isink_B_dcdc) {
232 case WM8350_DCDC_2:
233 case WM8350_DCDC_5:
234 wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
235 1 << (wm8350->pmic.isink_B_dcdc -
236 WM8350_DCDC_1));
237 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
238 WM8350_CS2_ENA);
239 break;
240 default:
241 return -EINVAL;
242 }
243 break;
244 default:
245 return -EINVAL;
246 }
247 return 0;
248}
249
250static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
251{
252 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
253 int isink = rdev_get_id(rdev);
254
255 switch (isink) {
256 case WM8350_ISINK_A:
257 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
258 0x8000;
259 case WM8350_ISINK_B:
260 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
261 0x8000;
262 }
263 return -EINVAL;
264}
265
266static int wm8350_isink_enable_time(struct regulator_dev *rdev)
267{
268 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
269 int isink = rdev_get_id(rdev);
270 int reg;
271
272 switch (isink) {
273 case WM8350_ISINK_A:
274 reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL);
275 break;
276 case WM8350_ISINK_B:
277 reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL);
278 break;
279 default:
280 return -EINVAL;
281 }
282
283 if (reg & WM8350_CS1_FLASH_MODE) {
284 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
285 case 0:
286 return 0;
287 case 1:
288 return 1950;
289 case 2:
290 return 3910;
291 case 3:
292 return 7800;
293 }
294 } else {
295 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
296 case 0:
297 return 0;
298 case 1:
299 return 250000;
300 case 2:
301 return 500000;
302 case 3:
303 return 1000000;
304 }
305 }
306
307 return -EINVAL;
308}
309
310
311int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
312 u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
313 u16 drive)
314{
315 switch (isink) {
316 case WM8350_ISINK_A:
317 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
318 (mode ? WM8350_CS1_FLASH_MODE : 0) |
319 (trigger ? WM8350_CS1_TRIGSRC : 0) |
320 duration | on_ramp | off_ramp | drive);
321 break;
322 case WM8350_ISINK_B:
323 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
324 (mode ? WM8350_CS2_FLASH_MODE : 0) |
325 (trigger ? WM8350_CS2_TRIGSRC : 0) |
326 duration | on_ramp | off_ramp | drive);
327 break;
328 default:
329 return -EINVAL;
330 }
331 return 0;
332}
333EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
334
335static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
336{
337 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
338 int sel, volt_reg, dcdc = rdev_get_id(rdev);
339 u16 val;
340
341 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, uV / 1000);
342
343 switch (dcdc) {
344 case WM8350_DCDC_1:
345 volt_reg = WM8350_DCDC1_LOW_POWER;
346 break;
347 case WM8350_DCDC_3:
348 volt_reg = WM8350_DCDC3_LOW_POWER;
349 break;
350 case WM8350_DCDC_4:
351 volt_reg = WM8350_DCDC4_LOW_POWER;
352 break;
353 case WM8350_DCDC_6:
354 volt_reg = WM8350_DCDC6_LOW_POWER;
355 break;
356 case WM8350_DCDC_2:
357 case WM8350_DCDC_5:
358 default:
359 return -EINVAL;
360 }
361
362 sel = regulator_map_voltage_linear(rdev, uV, uV);
363 if (sel < 0)
364 return sel;
365
366
367 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
368 wm8350_reg_write(wm8350, volt_reg, val | sel);
369 return 0;
370}
371
372static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
373{
374 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
375 int dcdc = rdev_get_id(rdev);
376 u16 val;
377
378 switch (dcdc) {
379 case WM8350_DCDC_1:
380 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
381 & ~WM8350_DCDC_HIB_MODE_MASK;
382 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
383 val | wm8350->pmic.dcdc1_hib_mode);
384 break;
385 case WM8350_DCDC_3:
386 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
387 & ~WM8350_DCDC_HIB_MODE_MASK;
388 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
389 val | wm8350->pmic.dcdc3_hib_mode);
390 break;
391 case WM8350_DCDC_4:
392 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
393 & ~WM8350_DCDC_HIB_MODE_MASK;
394 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
395 val | wm8350->pmic.dcdc4_hib_mode);
396 break;
397 case WM8350_DCDC_6:
398 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
399 & ~WM8350_DCDC_HIB_MODE_MASK;
400 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
401 val | wm8350->pmic.dcdc6_hib_mode);
402 break;
403 case WM8350_DCDC_2:
404 case WM8350_DCDC_5:
405 default:
406 return -EINVAL;
407 }
408
409 return 0;
410}
411
412static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
413{
414 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
415 int dcdc = rdev_get_id(rdev);
416 u16 val;
417
418 switch (dcdc) {
419 case WM8350_DCDC_1:
420 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
421 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
422 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
423 val | WM8350_DCDC_HIB_MODE_DIS);
424 break;
425 case WM8350_DCDC_3:
426 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
427 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
428 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
429 val | WM8350_DCDC_HIB_MODE_DIS);
430 break;
431 case WM8350_DCDC_4:
432 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
433 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
434 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
435 val | WM8350_DCDC_HIB_MODE_DIS);
436 break;
437 case WM8350_DCDC_6:
438 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
439 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
440 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
441 val | WM8350_DCDC_HIB_MODE_DIS);
442 break;
443 case WM8350_DCDC_2:
444 case WM8350_DCDC_5:
445 default:
446 return -EINVAL;
447 }
448
449 return 0;
450}
451
452static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
453{
454 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
455 int dcdc = rdev_get_id(rdev);
456 u16 val;
457
458 switch (dcdc) {
459 case WM8350_DCDC_2:
460 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
461 & ~WM8350_DC2_HIB_MODE_MASK;
462 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
463 (WM8350_DC2_HIB_MODE_ACTIVE << WM8350_DC2_HIB_MODE_SHIFT));
464 break;
465 case WM8350_DCDC_5:
466 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
467 & ~WM8350_DC5_HIB_MODE_MASK;
468 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
469 (WM8350_DC5_HIB_MODE_ACTIVE << WM8350_DC5_HIB_MODE_SHIFT));
470 break;
471 default:
472 return -EINVAL;
473 }
474 return 0;
475}
476
477static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
478{
479 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
480 int dcdc = rdev_get_id(rdev);
481 u16 val;
482
483 switch (dcdc) {
484 case WM8350_DCDC_2:
485 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
486 & ~WM8350_DC2_HIB_MODE_MASK;
487 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
488 (WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT));
489 break;
490 case WM8350_DCDC_5:
491 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
492 & ~WM8350_DC5_HIB_MODE_MASK;
493 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
494 (WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT));
495 break;
496 default:
497 return -EINVAL;
498 }
499 return 0;
500}
501
502static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
503 unsigned int mode)
504{
505 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
506 int dcdc = rdev_get_id(rdev);
507 u16 *hib_mode;
508
509 switch (dcdc) {
510 case WM8350_DCDC_1:
511 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
512 break;
513 case WM8350_DCDC_3:
514 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
515 break;
516 case WM8350_DCDC_4:
517 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
518 break;
519 case WM8350_DCDC_6:
520 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
521 break;
522 case WM8350_DCDC_2:
523 case WM8350_DCDC_5:
524 default:
525 return -EINVAL;
526 }
527
528 switch (mode) {
529 case REGULATOR_MODE_NORMAL:
530 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
531 break;
532 case REGULATOR_MODE_IDLE:
533 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
534 break;
535 case REGULATOR_MODE_STANDBY:
536 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
537 break;
538 default:
539 return -EINVAL;
540 }
541
542 return 0;
543}
544
545static const struct regulator_linear_range wm8350_ldo_ranges[] = {
546 REGULATOR_LINEAR_RANGE(900000, 0, 15, 50000),
547 REGULATOR_LINEAR_RANGE(1800000, 16, 31, 100000),
548};
549
550static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
551{
552 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
553 int sel, volt_reg, ldo = rdev_get_id(rdev);
554 u16 val;
555
556 dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, uV / 1000);
557
558 switch (ldo) {
559 case WM8350_LDO_1:
560 volt_reg = WM8350_LDO1_LOW_POWER;
561 break;
562 case WM8350_LDO_2:
563 volt_reg = WM8350_LDO2_LOW_POWER;
564 break;
565 case WM8350_LDO_3:
566 volt_reg = WM8350_LDO3_LOW_POWER;
567 break;
568 case WM8350_LDO_4:
569 volt_reg = WM8350_LDO4_LOW_POWER;
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 sel = regulator_map_voltage_linear_range(rdev, uV, uV);
576 if (sel < 0)
577 return sel;
578
579
580 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
581 wm8350_reg_write(wm8350, volt_reg, val | sel);
582 return 0;
583}
584
585static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
586{
587 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
588 int volt_reg, ldo = rdev_get_id(rdev);
589 u16 val;
590
591 switch (ldo) {
592 case WM8350_LDO_1:
593 volt_reg = WM8350_LDO1_LOW_POWER;
594 break;
595 case WM8350_LDO_2:
596 volt_reg = WM8350_LDO2_LOW_POWER;
597 break;
598 case WM8350_LDO_3:
599 volt_reg = WM8350_LDO3_LOW_POWER;
600 break;
601 case WM8350_LDO_4:
602 volt_reg = WM8350_LDO4_LOW_POWER;
603 break;
604 default:
605 return -EINVAL;
606 }
607
608
609 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
610 wm8350_reg_write(wm8350, volt_reg, val);
611 return 0;
612}
613
614static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
615{
616 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
617 int volt_reg, ldo = rdev_get_id(rdev);
618 u16 val;
619
620 switch (ldo) {
621 case WM8350_LDO_1:
622 volt_reg = WM8350_LDO1_LOW_POWER;
623 break;
624 case WM8350_LDO_2:
625 volt_reg = WM8350_LDO2_LOW_POWER;
626 break;
627 case WM8350_LDO_3:
628 volt_reg = WM8350_LDO3_LOW_POWER;
629 break;
630 case WM8350_LDO_4:
631 volt_reg = WM8350_LDO4_LOW_POWER;
632 break;
633 default:
634 return -EINVAL;
635 }
636
637
638 val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
639 wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS);
640 return 0;
641}
642
643int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
644 u16 stop, u16 fault)
645{
646 int slot_reg;
647 u16 val;
648
649 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
650 __func__, dcdc, start, stop);
651
652
653 if (start > 15 || stop > 15)
654 return -EINVAL;
655
656 switch (dcdc) {
657 case WM8350_DCDC_1:
658 slot_reg = WM8350_DCDC1_TIMEOUTS;
659 break;
660 case WM8350_DCDC_2:
661 slot_reg = WM8350_DCDC2_TIMEOUTS;
662 break;
663 case WM8350_DCDC_3:
664 slot_reg = WM8350_DCDC3_TIMEOUTS;
665 break;
666 case WM8350_DCDC_4:
667 slot_reg = WM8350_DCDC4_TIMEOUTS;
668 break;
669 case WM8350_DCDC_5:
670 slot_reg = WM8350_DCDC5_TIMEOUTS;
671 break;
672 case WM8350_DCDC_6:
673 slot_reg = WM8350_DCDC6_TIMEOUTS;
674 break;
675 default:
676 return -EINVAL;
677 }
678
679 val = wm8350_reg_read(wm8350, slot_reg) &
680 ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
681 WM8350_DC1_ERRACT_MASK);
682 wm8350_reg_write(wm8350, slot_reg,
683 val | (start << WM8350_DC1_ENSLOT_SHIFT) |
684 (stop << WM8350_DC1_SDSLOT_SHIFT) |
685 (fault << WM8350_DC1_ERRACT_SHIFT));
686
687 return 0;
688}
689EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
690
691int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
692{
693 int slot_reg;
694 u16 val;
695
696 dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
697 __func__, ldo, start, stop);
698
699
700 if (start > 15 || stop > 15)
701 return -EINVAL;
702
703 switch (ldo) {
704 case WM8350_LDO_1:
705 slot_reg = WM8350_LDO1_TIMEOUTS;
706 break;
707 case WM8350_LDO_2:
708 slot_reg = WM8350_LDO2_TIMEOUTS;
709 break;
710 case WM8350_LDO_3:
711 slot_reg = WM8350_LDO3_TIMEOUTS;
712 break;
713 case WM8350_LDO_4:
714 slot_reg = WM8350_LDO4_TIMEOUTS;
715 break;
716 default:
717 return -EINVAL;
718 }
719
720 val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
721 wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
722 return 0;
723}
724EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
725
726int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
727 u16 ilim, u16 ramp, u16 feedback)
728{
729 u16 val;
730
731 dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
732 mode ? "normal" : "boost", ilim ? "low" : "normal");
733
734 switch (dcdc) {
735 case WM8350_DCDC_2:
736 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
737 & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
738 WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
739 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
740 (mode << WM8350_DC2_MODE_SHIFT) |
741 (ilim << WM8350_DC2_ILIM_SHIFT) |
742 (ramp << WM8350_DC2_RMP_SHIFT) |
743 (feedback << WM8350_DC2_FBSRC_SHIFT));
744 break;
745 case WM8350_DCDC_5:
746 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
747 & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
748 WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
749 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
750 (mode << WM8350_DC5_MODE_SHIFT) |
751 (ilim << WM8350_DC5_ILIM_SHIFT) |
752 (ramp << WM8350_DC5_RMP_SHIFT) |
753 (feedback << WM8350_DC5_FBSRC_SHIFT));
754 break;
755 default:
756 return -EINVAL;
757 }
758
759 return 0;
760}
761EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
762
763static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
764{
765 int reg = 0, ret;
766
767 switch (dcdc) {
768 case WM8350_DCDC_1:
769 reg = WM8350_DCDC1_FORCE_PWM;
770 break;
771 case WM8350_DCDC_3:
772 reg = WM8350_DCDC3_FORCE_PWM;
773 break;
774 case WM8350_DCDC_4:
775 reg = WM8350_DCDC4_FORCE_PWM;
776 break;
777 case WM8350_DCDC_6:
778 reg = WM8350_DCDC6_FORCE_PWM;
779 break;
780 default:
781 return -EINVAL;
782 }
783
784 if (enable)
785 ret = wm8350_set_bits(wm8350, reg,
786 WM8350_DCDC1_FORCE_PWM_ENA);
787 else
788 ret = wm8350_clear_bits(wm8350, reg,
789 WM8350_DCDC1_FORCE_PWM_ENA);
790 return ret;
791}
792
793static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
794{
795 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
796 int dcdc = rdev_get_id(rdev);
797 u16 val;
798
799 if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
800 return -EINVAL;
801
802 if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
803 return -EINVAL;
804
805 val = 1 << (dcdc - WM8350_DCDC_1);
806
807 switch (mode) {
808 case REGULATOR_MODE_FAST:
809
810 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
811 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
812 force_continuous_enable(wm8350, dcdc, 1);
813 break;
814 case REGULATOR_MODE_NORMAL:
815
816 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
817 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
818 force_continuous_enable(wm8350, dcdc, 0);
819 break;
820 case REGULATOR_MODE_IDLE:
821
822 force_continuous_enable(wm8350, dcdc, 0);
823 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
824 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
825 break;
826 case REGULATOR_MODE_STANDBY:
827
828 force_continuous_enable(wm8350, dcdc, 0);
829 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
830 break;
831 }
832
833 return 0;
834}
835
836static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
837{
838 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
839 int dcdc = rdev_get_id(rdev);
840 u16 mask, sleep, active, force;
841 int mode = REGULATOR_MODE_NORMAL;
842 int reg;
843
844 switch (dcdc) {
845 case WM8350_DCDC_1:
846 reg = WM8350_DCDC1_FORCE_PWM;
847 break;
848 case WM8350_DCDC_3:
849 reg = WM8350_DCDC3_FORCE_PWM;
850 break;
851 case WM8350_DCDC_4:
852 reg = WM8350_DCDC4_FORCE_PWM;
853 break;
854 case WM8350_DCDC_6:
855 reg = WM8350_DCDC6_FORCE_PWM;
856 break;
857 default:
858 return -EINVAL;
859 }
860
861 mask = 1 << (dcdc - WM8350_DCDC_1);
862 active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
863 force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA;
864 sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
865
866 dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
867 mask, active, sleep, force);
868
869 if (active && !sleep) {
870 if (force)
871 mode = REGULATOR_MODE_FAST;
872 else
873 mode = REGULATOR_MODE_NORMAL;
874 } else if (!active && !sleep)
875 mode = REGULATOR_MODE_IDLE;
876 else if (sleep)
877 mode = REGULATOR_MODE_STANDBY;
878
879 return mode;
880}
881
882static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
883{
884 return REGULATOR_MODE_NORMAL;
885}
886
887struct wm8350_dcdc_efficiency {
888 int uA_load_min;
889 int uA_load_max;
890 unsigned int mode;
891};
892
893static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
894 {0, 10000, REGULATOR_MODE_STANDBY},
895 {10000, 100000, REGULATOR_MODE_IDLE},
896 {100000, 1000000, REGULATOR_MODE_NORMAL},
897 {-1, -1, REGULATOR_MODE_NORMAL},
898};
899
900static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
901 {0, 10000, REGULATOR_MODE_STANDBY},
902 {10000, 100000, REGULATOR_MODE_IDLE},
903 {100000, 800000, REGULATOR_MODE_NORMAL},
904 {-1, -1, REGULATOR_MODE_NORMAL},
905};
906
907static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
908{
909 int i = 0;
910
911 while (eff[i].uA_load_min != -1) {
912 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
913 return eff[i].mode;
914 }
915 return REGULATOR_MODE_NORMAL;
916}
917
918
919
920
921
922static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
923 int input_uV, int output_uV,
924 int output_uA)
925{
926 int dcdc = rdev_get_id(rdev), mode;
927
928 switch (dcdc) {
929 case WM8350_DCDC_1:
930 case WM8350_DCDC_6:
931 mode = get_mode(output_uA, dcdc1_6_efficiency);
932 break;
933 case WM8350_DCDC_3:
934 case WM8350_DCDC_4:
935 mode = get_mode(output_uA, dcdc3_4_efficiency);
936 break;
937 default:
938 mode = REGULATOR_MODE_NORMAL;
939 break;
940 }
941 return mode;
942}
943
944static const struct regulator_ops wm8350_dcdc_ops = {
945 .set_voltage_sel = regulator_set_voltage_sel_regmap,
946 .get_voltage_sel = regulator_get_voltage_sel_regmap,
947 .list_voltage = regulator_list_voltage_linear,
948 .map_voltage = regulator_map_voltage_linear,
949 .enable = regulator_enable_regmap,
950 .disable = regulator_disable_regmap,
951 .is_enabled = regulator_is_enabled_regmap,
952 .get_mode = wm8350_dcdc_get_mode,
953 .set_mode = wm8350_dcdc_set_mode,
954 .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
955 .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
956 .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
957 .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
958 .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
959};
960
961static const struct regulator_ops wm8350_dcdc2_5_ops = {
962 .enable = regulator_enable_regmap,
963 .disable = regulator_disable_regmap,
964 .is_enabled = regulator_is_enabled_regmap,
965 .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
966 .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
967};
968
969static const struct regulator_ops wm8350_ldo_ops = {
970 .map_voltage = regulator_map_voltage_linear_range,
971 .set_voltage_sel = regulator_set_voltage_sel_regmap,
972 .get_voltage_sel = regulator_get_voltage_sel_regmap,
973 .list_voltage = regulator_list_voltage_linear_range,
974 .enable = regulator_enable_regmap,
975 .disable = regulator_disable_regmap,
976 .is_enabled = regulator_is_enabled_regmap,
977 .get_mode = wm8350_ldo_get_mode,
978 .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
979 .set_suspend_enable = wm8350_ldo_set_suspend_enable,
980 .set_suspend_disable = wm8350_ldo_set_suspend_disable,
981};
982
983static const struct regulator_ops wm8350_isink_ops = {
984 .set_current_limit = wm8350_isink_set_current,
985 .get_current_limit = wm8350_isink_get_current,
986 .enable = wm8350_isink_enable,
987 .disable = wm8350_isink_disable,
988 .is_enabled = wm8350_isink_is_enabled,
989 .enable_time = wm8350_isink_enable_time,
990};
991
992static const struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
993 {
994 .name = "DCDC1",
995 .id = WM8350_DCDC_1,
996 .ops = &wm8350_dcdc_ops,
997 .irq = WM8350_IRQ_UV_DC1,
998 .type = REGULATOR_VOLTAGE,
999 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1000 .min_uV = 850000,
1001 .uV_step = 25000,
1002 .vsel_reg = WM8350_DCDC1_CONTROL,
1003 .vsel_mask = WM8350_DC1_VSEL_MASK,
1004 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1005 .enable_mask = WM8350_DC1_ENA,
1006 .owner = THIS_MODULE,
1007 },
1008 {
1009 .name = "DCDC2",
1010 .id = WM8350_DCDC_2,
1011 .ops = &wm8350_dcdc2_5_ops,
1012 .irq = WM8350_IRQ_UV_DC2,
1013 .type = REGULATOR_VOLTAGE,
1014 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1015 .enable_mask = WM8350_DC2_ENA,
1016 .owner = THIS_MODULE,
1017 },
1018 {
1019 .name = "DCDC3",
1020 .id = WM8350_DCDC_3,
1021 .ops = &wm8350_dcdc_ops,
1022 .irq = WM8350_IRQ_UV_DC3,
1023 .type = REGULATOR_VOLTAGE,
1024 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1025 .min_uV = 850000,
1026 .uV_step = 25000,
1027 .vsel_reg = WM8350_DCDC3_CONTROL,
1028 .vsel_mask = WM8350_DC3_VSEL_MASK,
1029 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1030 .enable_mask = WM8350_DC3_ENA,
1031 .owner = THIS_MODULE,
1032 },
1033 {
1034 .name = "DCDC4",
1035 .id = WM8350_DCDC_4,
1036 .ops = &wm8350_dcdc_ops,
1037 .irq = WM8350_IRQ_UV_DC4,
1038 .type = REGULATOR_VOLTAGE,
1039 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1040 .min_uV = 850000,
1041 .uV_step = 25000,
1042 .vsel_reg = WM8350_DCDC4_CONTROL,
1043 .vsel_mask = WM8350_DC4_VSEL_MASK,
1044 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1045 .enable_mask = WM8350_DC4_ENA,
1046 .owner = THIS_MODULE,
1047 },
1048 {
1049 .name = "DCDC5",
1050 .id = WM8350_DCDC_5,
1051 .ops = &wm8350_dcdc2_5_ops,
1052 .irq = WM8350_IRQ_UV_DC5,
1053 .type = REGULATOR_VOLTAGE,
1054 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1055 .enable_mask = WM8350_DC5_ENA,
1056 .owner = THIS_MODULE,
1057 },
1058 {
1059 .name = "DCDC6",
1060 .id = WM8350_DCDC_6,
1061 .ops = &wm8350_dcdc_ops,
1062 .irq = WM8350_IRQ_UV_DC6,
1063 .type = REGULATOR_VOLTAGE,
1064 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1065 .min_uV = 850000,
1066 .uV_step = 25000,
1067 .vsel_reg = WM8350_DCDC6_CONTROL,
1068 .vsel_mask = WM8350_DC6_VSEL_MASK,
1069 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1070 .enable_mask = WM8350_DC6_ENA,
1071 .owner = THIS_MODULE,
1072 },
1073 {
1074 .name = "LDO1",
1075 .id = WM8350_LDO_1,
1076 .ops = &wm8350_ldo_ops,
1077 .irq = WM8350_IRQ_UV_LDO1,
1078 .type = REGULATOR_VOLTAGE,
1079 .n_voltages = WM8350_LDO1_VSEL_MASK + 1,
1080 .linear_ranges = wm8350_ldo_ranges,
1081 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1082 .vsel_reg = WM8350_LDO1_CONTROL,
1083 .vsel_mask = WM8350_LDO1_VSEL_MASK,
1084 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1085 .enable_mask = WM8350_LDO1_ENA,
1086 .owner = THIS_MODULE,
1087 },
1088 {
1089 .name = "LDO2",
1090 .id = WM8350_LDO_2,
1091 .ops = &wm8350_ldo_ops,
1092 .irq = WM8350_IRQ_UV_LDO2,
1093 .type = REGULATOR_VOLTAGE,
1094 .n_voltages = WM8350_LDO2_VSEL_MASK + 1,
1095 .linear_ranges = wm8350_ldo_ranges,
1096 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1097 .vsel_reg = WM8350_LDO2_CONTROL,
1098 .vsel_mask = WM8350_LDO2_VSEL_MASK,
1099 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1100 .enable_mask = WM8350_LDO2_ENA,
1101 .owner = THIS_MODULE,
1102 },
1103 {
1104 .name = "LDO3",
1105 .id = WM8350_LDO_3,
1106 .ops = &wm8350_ldo_ops,
1107 .irq = WM8350_IRQ_UV_LDO3,
1108 .type = REGULATOR_VOLTAGE,
1109 .n_voltages = WM8350_LDO3_VSEL_MASK + 1,
1110 .linear_ranges = wm8350_ldo_ranges,
1111 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1112 .vsel_reg = WM8350_LDO3_CONTROL,
1113 .vsel_mask = WM8350_LDO3_VSEL_MASK,
1114 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1115 .enable_mask = WM8350_LDO3_ENA,
1116 .owner = THIS_MODULE,
1117 },
1118 {
1119 .name = "LDO4",
1120 .id = WM8350_LDO_4,
1121 .ops = &wm8350_ldo_ops,
1122 .irq = WM8350_IRQ_UV_LDO4,
1123 .type = REGULATOR_VOLTAGE,
1124 .n_voltages = WM8350_LDO4_VSEL_MASK + 1,
1125 .linear_ranges = wm8350_ldo_ranges,
1126 .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1127 .vsel_reg = WM8350_LDO4_CONTROL,
1128 .vsel_mask = WM8350_LDO4_VSEL_MASK,
1129 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1130 .enable_mask = WM8350_LDO4_ENA,
1131 .owner = THIS_MODULE,
1132 },
1133 {
1134 .name = "ISINKA",
1135 .id = WM8350_ISINK_A,
1136 .ops = &wm8350_isink_ops,
1137 .irq = WM8350_IRQ_CS1,
1138 .type = REGULATOR_CURRENT,
1139 .owner = THIS_MODULE,
1140 },
1141 {
1142 .name = "ISINKB",
1143 .id = WM8350_ISINK_B,
1144 .ops = &wm8350_isink_ops,
1145 .irq = WM8350_IRQ_CS2,
1146 .type = REGULATOR_CURRENT,
1147 .owner = THIS_MODULE,
1148 },
1149};
1150
1151static irqreturn_t pmic_uv_handler(int irq, void *data)
1152{
1153 struct regulator_dev *rdev = (struct regulator_dev *)data;
1154
1155 mutex_lock(&rdev->mutex);
1156 if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1157 regulator_notifier_call_chain(rdev,
1158 REGULATOR_EVENT_REGULATION_OUT,
1159 NULL);
1160 else
1161 regulator_notifier_call_chain(rdev,
1162 REGULATOR_EVENT_UNDER_VOLTAGE,
1163 NULL);
1164 mutex_unlock(&rdev->mutex);
1165
1166 return IRQ_HANDLED;
1167}
1168
1169static int wm8350_regulator_probe(struct platform_device *pdev)
1170{
1171 struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1172 struct regulator_config config = { };
1173 struct regulator_dev *rdev;
1174 int ret;
1175 u16 val;
1176
1177 if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1178 return -ENODEV;
1179
1180
1181 switch (pdev->id) {
1182 case WM8350_DCDC_1:
1183 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1184 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1185 break;
1186 case WM8350_DCDC_3:
1187 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1188 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1189 break;
1190 case WM8350_DCDC_4:
1191 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1192 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1193 break;
1194 case WM8350_DCDC_6:
1195 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1196 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1197 break;
1198 }
1199
1200 config.dev = &pdev->dev;
1201 config.init_data = dev_get_platdata(&pdev->dev);
1202 config.driver_data = dev_get_drvdata(&pdev->dev);
1203 config.regmap = wm8350->regmap;
1204
1205
1206 rdev = devm_regulator_register(&pdev->dev, &wm8350_reg[pdev->id],
1207 &config);
1208 if (IS_ERR(rdev)) {
1209 dev_err(&pdev->dev, "failed to register %s\n",
1210 wm8350_reg[pdev->id].name);
1211 return PTR_ERR(rdev);
1212 }
1213
1214
1215 ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1216 pmic_uv_handler, 0, "UV", rdev);
1217 if (ret < 0) {
1218 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1219 wm8350_reg[pdev->id].name);
1220 return ret;
1221 }
1222
1223 return 0;
1224}
1225
1226static int wm8350_regulator_remove(struct platform_device *pdev)
1227{
1228 struct regulator_dev *rdev = platform_get_drvdata(pdev);
1229 struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1230
1231 wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev);
1232
1233 return 0;
1234}
1235
1236int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1237 struct regulator_init_data *initdata)
1238{
1239 struct platform_device *pdev;
1240 int ret;
1241 if (reg < 0 || reg >= NUM_WM8350_REGULATORS)
1242 return -EINVAL;
1243
1244 if (wm8350->pmic.pdev[reg])
1245 return -EBUSY;
1246
1247 if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 &&
1248 reg > wm8350->pmic.max_dcdc)
1249 return -ENODEV;
1250 if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B &&
1251 reg > wm8350->pmic.max_isink)
1252 return -ENODEV;
1253
1254 pdev = platform_device_alloc("wm8350-regulator", reg);
1255 if (!pdev)
1256 return -ENOMEM;
1257
1258 wm8350->pmic.pdev[reg] = pdev;
1259
1260 initdata->driver_data = wm8350;
1261
1262 pdev->dev.platform_data = initdata;
1263 pdev->dev.parent = wm8350->dev;
1264 platform_set_drvdata(pdev, wm8350);
1265
1266 ret = platform_device_add(pdev);
1267
1268 if (ret != 0) {
1269 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1270 reg, ret);
1271 platform_device_put(pdev);
1272 wm8350->pmic.pdev[reg] = NULL;
1273 }
1274
1275 return ret;
1276}
1277EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
1296 struct wm8350_led_platform_data *pdata)
1297{
1298 struct wm8350_led *led;
1299 struct platform_device *pdev;
1300 int ret;
1301
1302 if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) {
1303 dev_err(wm8350->dev, "Invalid LED index %d\n", lednum);
1304 return -ENODEV;
1305 }
1306
1307 led = &wm8350->pmic.led[lednum];
1308
1309 if (led->pdev) {
1310 dev_err(wm8350->dev, "LED %d already allocated\n", lednum);
1311 return -EINVAL;
1312 }
1313
1314 pdev = platform_device_alloc("wm8350-led", lednum);
1315 if (pdev == NULL) {
1316 dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum);
1317 return -ENOMEM;
1318 }
1319
1320 led->isink_consumer.dev_name = dev_name(&pdev->dev);
1321 led->isink_consumer.supply = "led_isink";
1322 led->isink_init.num_consumer_supplies = 1;
1323 led->isink_init.consumer_supplies = &led->isink_consumer;
1324 led->isink_init.constraints.min_uA = 0;
1325 led->isink_init.constraints.max_uA = pdata->max_uA;
1326 led->isink_init.constraints.valid_ops_mask
1327 = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS;
1328 led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1329 ret = wm8350_register_regulator(wm8350, isink, &led->isink_init);
1330 if (ret != 0) {
1331 platform_device_put(pdev);
1332 return ret;
1333 }
1334
1335 led->dcdc_consumer.dev_name = dev_name(&pdev->dev);
1336 led->dcdc_consumer.supply = "led_vcc";
1337 led->dcdc_init.num_consumer_supplies = 1;
1338 led->dcdc_init.consumer_supplies = &led->dcdc_consumer;
1339 led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1340 led->dcdc_init.constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
1341 ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init);
1342 if (ret != 0) {
1343 platform_device_put(pdev);
1344 return ret;
1345 }
1346
1347 switch (isink) {
1348 case WM8350_ISINK_A:
1349 wm8350->pmic.isink_A_dcdc = dcdc;
1350 break;
1351 case WM8350_ISINK_B:
1352 wm8350->pmic.isink_B_dcdc = dcdc;
1353 break;
1354 }
1355
1356 pdev->dev.platform_data = pdata;
1357 pdev->dev.parent = wm8350->dev;
1358 ret = platform_device_add(pdev);
1359 if (ret != 0) {
1360 dev_err(wm8350->dev, "Failed to register LED %d: %d\n",
1361 lednum, ret);
1362 platform_device_put(pdev);
1363 return ret;
1364 }
1365
1366 led->pdev = pdev;
1367
1368 return 0;
1369}
1370EXPORT_SYMBOL_GPL(wm8350_register_led);
1371
1372static struct platform_driver wm8350_regulator_driver = {
1373 .probe = wm8350_regulator_probe,
1374 .remove = wm8350_regulator_remove,
1375 .driver = {
1376 .name = "wm8350-regulator",
1377 },
1378};
1379
1380static int __init wm8350_regulator_init(void)
1381{
1382 return platform_driver_register(&wm8350_regulator_driver);
1383}
1384subsys_initcall(wm8350_regulator_init);
1385
1386static void __exit wm8350_regulator_exit(void)
1387{
1388 platform_driver_unregister(&wm8350_regulator_driver);
1389}
1390module_exit(wm8350_regulator_exit);
1391
1392
1393MODULE_AUTHOR("Liam Girdwood");
1394MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1395MODULE_LICENSE("GPL");
1396MODULE_ALIAS("platform:wm8350-regulator");
1397
