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12#include "hisi_sas.h"
13#define DRV_NAME "hisi_sas_v1_hw"
14
15
16#define DLVRY_QUEUE_ENABLE 0x0
17#define IOST_BASE_ADDR_LO 0x8
18#define IOST_BASE_ADDR_HI 0xc
19#define ITCT_BASE_ADDR_LO 0x10
20#define ITCT_BASE_ADDR_HI 0x14
21#define BROKEN_MSG_ADDR_LO 0x18
22#define BROKEN_MSG_ADDR_HI 0x1c
23#define PHY_CONTEXT 0x20
24#define PHY_STATE 0x24
25#define PHY_PORT_NUM_MA 0x28
26#define PORT_STATE 0x2c
27#define PHY_CONN_RATE 0x30
28#define HGC_TRANS_TASK_CNT_LIMIT 0x38
29#define AXI_AHB_CLK_CFG 0x3c
30#define HGC_SAS_TXFAIL_RETRY_CTRL 0x84
31#define HGC_GET_ITV_TIME 0x90
32#define DEVICE_MSG_WORK_MODE 0x94
33#define I_T_NEXUS_LOSS_TIME 0xa0
34#define BUS_INACTIVE_LIMIT_TIME 0xa8
35#define REJECT_TO_OPEN_LIMIT_TIME 0xac
36#define CFG_AGING_TIME 0xbc
37#define CFG_AGING_TIME_ITCT_REL_OFF 0
38#define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF)
39#define HGC_DFX_CFG2 0xc0
40#define FIS_LIST_BADDR_L 0xc4
41#define CFG_1US_TIMER_TRSH 0xcc
42#define CFG_SAS_CONFIG 0xd4
43#define HGC_IOST_ECC_ADDR 0x140
44#define HGC_IOST_ECC_ADDR_BAD_OFF 16
45#define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)
46#define HGC_DQ_ECC_ADDR 0x144
47#define HGC_DQ_ECC_ADDR_BAD_OFF 16
48#define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)
49#define HGC_INVLD_DQE_INFO 0x148
50#define HGC_INVLD_DQE_INFO_DQ_OFF 0
51#define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)
52#define HGC_INVLD_DQE_INFO_TYPE_OFF 16
53#define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)
54#define HGC_INVLD_DQE_INFO_FORCE_OFF 17
55#define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)
56#define HGC_INVLD_DQE_INFO_PHY_OFF 18
57#define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)
58#define HGC_INVLD_DQE_INFO_ABORT_OFF 19
59#define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)
60#define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20
61#define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)
62#define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21
63#define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)
64#define HGC_INVLD_DQE_INFO_OFL_OFF 22
65#define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)
66#define HGC_ITCT_ECC_ADDR 0x150
67#define HGC_ITCT_ECC_ADDR_BAD_OFF 16
68#define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)
69#define HGC_AXI_FIFO_ERR_INFO 0x154
70#define INT_COAL_EN 0x1bc
71#define OQ_INT_COAL_TIME 0x1c0
72#define OQ_INT_COAL_CNT 0x1c4
73#define ENT_INT_COAL_TIME 0x1c8
74#define ENT_INT_COAL_CNT 0x1cc
75#define OQ_INT_SRC 0x1d0
76#define OQ_INT_SRC_MSK 0x1d4
77#define ENT_INT_SRC1 0x1d8
78#define ENT_INT_SRC2 0x1dc
79#define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25
80#define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)
81#define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27
82#define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)
83#define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28
84#define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)
85#define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29
86#define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)
87#define ENT_INT_SRC_MSK1 0x1e0
88#define ENT_INT_SRC_MSK2 0x1e4
89#define SAS_ECC_INTR 0x1e8
90#define SAS_ECC_INTR_DQ_ECC1B_OFF 0
91#define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)
92#define SAS_ECC_INTR_DQ_ECCBAD_OFF 1
93#define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)
94#define SAS_ECC_INTR_IOST_ECC1B_OFF 2
95#define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)
96#define SAS_ECC_INTR_IOST_ECCBAD_OFF 3
97#define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)
98#define SAS_ECC_INTR_ITCT_ECC1B_OFF 4
99#define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)
100#define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5
101#define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)
102#define SAS_ECC_INTR_MSK 0x1ec
103#define HGC_ERR_STAT_EN 0x238
104#define DLVRY_Q_0_BASE_ADDR_LO 0x260
105#define DLVRY_Q_0_BASE_ADDR_HI 0x264
106#define DLVRY_Q_0_DEPTH 0x268
107#define DLVRY_Q_0_WR_PTR 0x26c
108#define DLVRY_Q_0_RD_PTR 0x270
109#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
110#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
111#define COMPL_Q_0_DEPTH 0x4e8
112#define COMPL_Q_0_WR_PTR 0x4ec
113#define COMPL_Q_0_RD_PTR 0x4f0
114#define HGC_ECC_ERR 0x7d0
115
116
117#define PORT_BASE (0x800)
118
119#define PHY_CFG (PORT_BASE + 0x0)
120#define PHY_CFG_ENA_OFF 0
121#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
122#define PHY_CFG_DC_OPT_OFF 2
123#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
124#define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)
125#define PROG_PHY_LINK_RATE_MAX_OFF 0
126#define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF)
127#define PROG_PHY_LINK_RATE_MIN_OFF 4
128#define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF)
129#define PROG_PHY_LINK_RATE_OOB_OFF 8
130#define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF)
131#define PHY_CTRL (PORT_BASE + 0x14)
132#define PHY_CTRL_RESET_OFF 0
133#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
134#define PHY_RATE_NEGO (PORT_BASE + 0x30)
135#define PHY_PCN (PORT_BASE + 0x44)
136#define SL_TOUT_CFG (PORT_BASE + 0x8c)
137#define SL_CONTROL (PORT_BASE + 0x94)
138#define SL_CONTROL_NOTIFY_EN_OFF 0
139#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
140#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
141#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
142#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
143#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
144#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
145#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
146#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
147#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
148#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
149#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
150#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
151#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
152#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
153#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
154#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
155#define DONE_RECEIVED_TIME (PORT_BASE + 0x12c)
156#define CON_CFG_DRIVER (PORT_BASE + 0x130)
157#define PHY_CONFIG2 (PORT_BASE + 0x1a8)
158#define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3
159#define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
160#define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24
161#define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)
162#define CHL_INT0 (PORT_BASE + 0x1b0)
163#define CHL_INT0_PHYCTRL_NOTRDY_OFF 0
164#define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)
165#define CHL_INT0_SN_FAIL_NGR_OFF 2
166#define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF)
167#define CHL_INT0_DWS_LOST_OFF 4
168#define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF)
169#define CHL_INT0_SL_IDAF_FAIL_OFF 10
170#define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)
171#define CHL_INT0_ID_TIMEOUT_OFF 11
172#define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF)
173#define CHL_INT0_SL_OPAF_FAIL_OFF 12
174#define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)
175#define CHL_INT0_SL_PS_FAIL_OFF 21
176#define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF)
177#define CHL_INT1 (PORT_BASE + 0x1b4)
178#define CHL_INT2 (PORT_BASE + 0x1b8)
179#define CHL_INT2_SL_RX_BC_ACK_OFF 2
180#define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)
181#define CHL_INT2_SL_PHY_ENA_OFF 6
182#define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF)
183#define CHL_INT0_MSK (PORT_BASE + 0x1bc)
184#define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0
185#define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)
186#define CHL_INT1_MSK (PORT_BASE + 0x1c0)
187#define CHL_INT2_MSK (PORT_BASE + 0x1c4)
188#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
189#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
190#define DMA_TX_STATUS_BUSY_OFF 0
191#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
192#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
193#define DMA_RX_STATUS_BUSY_OFF 0
194#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
195
196#define AXI_CFG 0x5100
197#define RESET_VALUE 0x7ffff
198
199
200
201
202#define CMD_HDR_RESP_REPORT_OFF 5
203#define CMD_HDR_RESP_REPORT_MSK 0x20
204#define CMD_HDR_TLR_CTRL_OFF 6
205#define CMD_HDR_TLR_CTRL_MSK 0xc0
206#define CMD_HDR_PORT_OFF 17
207#define CMD_HDR_PORT_MSK 0xe0000
208#define CMD_HDR_PRIORITY_OFF 27
209#define CMD_HDR_PRIORITY_MSK 0x8000000
210#define CMD_HDR_MODE_OFF 28
211#define CMD_HDR_MODE_MSK 0x10000000
212#define CMD_HDR_CMD_OFF 29
213#define CMD_HDR_CMD_MSK 0xe0000000
214
215#define CMD_HDR_VERIFY_DTL_OFF 10
216#define CMD_HDR_VERIFY_DTL_MSK 0x400
217#define CMD_HDR_SSP_FRAME_TYPE_OFF 13
218#define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000
219#define CMD_HDR_DEVICE_ID_OFF 16
220#define CMD_HDR_DEVICE_ID_MSK 0xffff0000
221
222#define CMD_HDR_CFL_OFF 0
223#define CMD_HDR_CFL_MSK 0x1ff
224#define CMD_HDR_MRFL_OFF 15
225#define CMD_HDR_MRFL_MSK 0xff8000
226#define CMD_HDR_FIRST_BURST_OFF 25
227#define CMD_HDR_FIRST_BURST_MSK 0x2000000
228
229#define CMD_HDR_IPTT_OFF 0
230#define CMD_HDR_IPTT_MSK 0xffff
231
232#define CMD_HDR_DATA_SGL_LEN_OFF 16
233#define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000
234
235
236#define CMPLT_HDR_IPTT_OFF 0
237#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
238#define CMPLT_HDR_CMD_CMPLT_OFF 17
239#define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF)
240#define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18
241#define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)
242#define CMPLT_HDR_RSPNS_XFRD_OFF 19
243#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
244#define CMPLT_HDR_IO_CFG_ERR_OFF 27
245#define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)
246
247
248
249#define ITCT_HDR_DEV_TYPE_OFF 0
250#define ITCT_HDR_DEV_TYPE_MSK (0x3ULL << ITCT_HDR_DEV_TYPE_OFF)
251#define ITCT_HDR_VALID_OFF 2
252#define ITCT_HDR_VALID_MSK (0x1ULL << ITCT_HDR_VALID_OFF)
253#define ITCT_HDR_AWT_CONTROL_OFF 4
254#define ITCT_HDR_AWT_CONTROL_MSK (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF)
255#define ITCT_HDR_MAX_CONN_RATE_OFF 5
256#define ITCT_HDR_MAX_CONN_RATE_MSK (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF)
257#define ITCT_HDR_VALID_LINK_NUM_OFF 9
258#define ITCT_HDR_VALID_LINK_NUM_MSK (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF)
259#define ITCT_HDR_PORT_ID_OFF 13
260#define ITCT_HDR_PORT_ID_MSK (0x7ULL << ITCT_HDR_PORT_ID_OFF)
261#define ITCT_HDR_SMP_TIMEOUT_OFF 16
262#define ITCT_HDR_SMP_TIMEOUT_MSK (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF)
263
264#define ITCT_HDR_MAX_SAS_ADDR_OFF 0
265#define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \
266 ITCT_HDR_MAX_SAS_ADDR_OFF)
267
268#define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0
269#define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffffULL << \
270 ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)
271#define ITCT_HDR_BUS_INACTIVE_TL_OFF 16
272#define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffffULL << \
273 ITCT_HDR_BUS_INACTIVE_TL_OFF)
274#define ITCT_HDR_MAX_CONN_TL_OFF 32
275#define ITCT_HDR_MAX_CONN_TL_MSK (0xffffULL << \
276 ITCT_HDR_MAX_CONN_TL_OFF)
277#define ITCT_HDR_REJ_OPEN_TL_OFF 48
278#define ITCT_HDR_REJ_OPEN_TL_MSK (0xffffULL << \
279 ITCT_HDR_REJ_OPEN_TL_OFF)
280
281
282#define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0
283#define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)
284#define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16
285#define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)
286
287struct hisi_sas_complete_v1_hdr {
288 __le32 data;
289};
290
291struct hisi_sas_err_record_v1 {
292
293 __le32 dma_err_type;
294
295
296 __le32 trans_tx_fail_type;
297
298
299 __le32 trans_rx_fail_type;
300
301
302 u32 rsvd;
303};
304
305enum {
306 HISI_SAS_PHY_BCAST_ACK = 0,
307 HISI_SAS_PHY_SL_PHY_ENABLED,
308 HISI_SAS_PHY_INT_ABNORMAL,
309 HISI_SAS_PHY_INT_NR
310};
311
312enum {
313 DMA_TX_ERR_BASE = 0x0,
314 DMA_RX_ERR_BASE = 0x100,
315 TRANS_TX_FAIL_BASE = 0x200,
316 TRANS_RX_FAIL_BASE = 0x300,
317
318
319 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE,
320 DMA_TX_DIF_APP_ERR,
321 DMA_TX_DIF_RPP_ERR,
322 DMA_TX_AXI_BUS_ERR,
323 DMA_TX_DATA_SGL_OVERFLOW_ERR,
324 DMA_TX_DIF_SGL_OVERFLOW_ERR,
325 DMA_TX_UNEXP_XFER_RDY_ERR,
326 DMA_TX_XFER_RDY_OFFSET_ERR,
327 DMA_TX_DATA_UNDERFLOW_ERR,
328 DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR,
329
330
331 DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE,
332 DMA_RX_DIF_CRC_ERR,
333 DMA_RX_DIF_APP_ERR,
334 DMA_RX_DIF_RPP_ERR,
335 DMA_RX_RESP_BUFFER_OVERFLOW_ERR,
336 DMA_RX_AXI_BUS_ERR,
337 DMA_RX_DATA_SGL_OVERFLOW_ERR,
338 DMA_RX_DIF_SGL_OVERFLOW_ERR,
339 DMA_RX_DATA_OFFSET_ERR,
340 DMA_RX_UNEXP_RX_DATA_ERR,
341 DMA_RX_DATA_OVERFLOW_ERR,
342 DMA_RX_DATA_UNDERFLOW_ERR,
343 DMA_RX_UNEXP_RETRANS_RESP_ERR,
344
345
346 TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE,
347 TRANS_TX_PHY_NOT_ENABLE_ERR,
348 TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR,
349 TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR,
350 TRANS_TX_OPEN_REJCT_BY_OTHER_ERR,
351 TRANS_TX_RSVD1_ERR,
352 TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR,
353 TRANS_TX_OPEN_REJCT_STP_BUSY_ERR,
354 TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR,
355 TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR,
356 TRANS_TX_OPEN_REJCT_BAD_DEST_ERR,
357 TRANS_TX_OPEN_BREAK_RECEIVE_ERR,
358 TRANS_TX_LOW_PHY_POWER_ERR,
359 TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR,
360 TRANS_TX_OPEN_TIMEOUT_ERR,
361 TRANS_TX_OPEN_REJCT_NO_DEST_ERR,
362 TRANS_TX_OPEN_RETRY_ERR,
363 TRANS_TX_RSVD2_ERR,
364 TRANS_TX_BREAK_TIMEOUT_ERR,
365 TRANS_TX_BREAK_REQUEST_ERR,
366 TRANS_TX_BREAK_RECEIVE_ERR,
367 TRANS_TX_CLOSE_TIMEOUT_ERR,
368 TRANS_TX_CLOSE_NORMAL_ERR,
369 TRANS_TX_CLOSE_PHYRESET_ERR,
370 TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR,
371 TRANS_TX_WITH_CLOSE_COMINIT_ERR,
372 TRANS_TX_NAK_RECEIVE_ERR,
373 TRANS_TX_ACK_NAK_TIMEOUT_ERR,
374 TRANS_TX_CREDIT_TIMEOUT_ERR,
375 TRANS_TX_IPTT_CONFLICT_ERR,
376 TRANS_TX_TXFRM_TYPE_ERR,
377 TRANS_TX_TXSMP_LENGTH_ERR,
378
379
380 TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE,
381 TRANS_RX_FRAME_DONE_ERR,
382 TRANS_RX_FRAME_ERRPRM_ERR,
383 TRANS_RX_FRAME_NO_CREDIT_ERR,
384 TRANS_RX_RSVD0_ERR,
385 TRANS_RX_FRAME_OVERRUN_ERR,
386 TRANS_RX_FRAME_NO_EOF_ERR,
387 TRANS_RX_LINK_BUF_OVERRUN_ERR,
388 TRANS_RX_BREAK_TIMEOUT_ERR,
389 TRANS_RX_BREAK_REQUEST_ERR,
390 TRANS_RX_BREAK_RECEIVE_ERR,
391 TRANS_RX_CLOSE_TIMEOUT_ERR,
392 TRANS_RX_CLOSE_NORMAL_ERR,
393 TRANS_RX_CLOSE_PHYRESET_ERR,
394 TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR,
395 TRANS_RX_WITH_CLOSE_COMINIT_ERR,
396 TRANS_RX_DATA_LENGTH0_ERR,
397 TRANS_RX_BAD_HASH_ERR,
398 TRANS_RX_XRDY_ZERO_ERR,
399 TRANS_RX_SSP_FRAME_LEN_ERR,
400 TRANS_RX_TRANS_RX_RSVD1_ERR,
401 TRANS_RX_NO_BALANCE_ERR,
402 TRANS_RX_TRANS_RX_RSVD2_ERR,
403 TRANS_RX_TRANS_RX_RSVD3_ERR,
404 TRANS_RX_BAD_FRAME_TYPE_ERR,
405 TRANS_RX_SMP_FRAME_LEN_ERR,
406 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
407};
408
409#define HISI_SAS_COMMAND_ENTRIES_V1_HW 8192
410
411#define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
412#define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
413#define HISI_SAS_FATAL_INT_NR (2)
414
415#define HISI_SAS_MAX_INT_NR \
416 (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
417 HISI_SAS_FATAL_INT_NR)
418
419static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
420{
421 void __iomem *regs = hisi_hba->regs + off;
422
423 return readl(regs);
424}
425
426static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
427{
428 void __iomem *regs = hisi_hba->regs + off;
429
430 return readl_relaxed(regs);
431}
432
433static void hisi_sas_write32(struct hisi_hba *hisi_hba,
434 u32 off, u32 val)
435{
436 void __iomem *regs = hisi_hba->regs + off;
437
438 writel(val, regs);
439}
440
441static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba,
442 int phy_no, u32 off, u32 val)
443{
444 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
445
446 writel(val, regs);
447}
448
449static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
450 int phy_no, u32 off)
451{
452 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
453
454 return readl(regs);
455}
456
457static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
458{
459 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
460
461 cfg &= ~PHY_CFG_DC_OPT_MSK;
462 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
463 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
464}
465
466static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
467{
468 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2);
469
470 cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
471 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg);
472}
473
474static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
475{
476 struct sas_identify_frame identify_frame;
477 u32 *identify_buffer;
478
479 memset(&identify_frame, 0, sizeof(identify_frame));
480 identify_frame.dev_type = SAS_END_DEVICE;
481 identify_frame.frame_type = 0;
482 identify_frame._un1 = 1;
483 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
484 identify_frame.target_bits = SAS_PROTOCOL_NONE;
485 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
486 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
487 identify_frame.phy_id = phy_no;
488 identify_buffer = (u32 *)(&identify_frame);
489
490 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
491 __swab32(identify_buffer[0]));
492 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
493 __swab32(identify_buffer[1]));
494 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
495 __swab32(identify_buffer[2]));
496 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
497 __swab32(identify_buffer[3]));
498 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
499 __swab32(identify_buffer[4]));
500 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
501 __swab32(identify_buffer[5]));
502}
503
504static void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
505 struct hisi_sas_device *sas_dev)
506{
507 struct domain_device *device = sas_dev->sas_device;
508 struct device *dev = &hisi_hba->pdev->dev;
509 u64 qw0, device_id = sas_dev->device_id;
510 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
511 struct asd_sas_port *sas_port = device->port;
512 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
513
514 memset(itct, 0, sizeof(*itct));
515
516
517 qw0 = 0;
518 switch (sas_dev->dev_type) {
519 case SAS_END_DEVICE:
520 case SAS_EDGE_EXPANDER_DEVICE:
521 case SAS_FANOUT_EXPANDER_DEVICE:
522 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
523 break;
524 default:
525 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
526 sas_dev->dev_type);
527 }
528
529 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
530 (1 << ITCT_HDR_AWT_CONTROL_OFF) |
531 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) |
532 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) |
533 (port->id << ITCT_HDR_PORT_ID_OFF));
534 itct->qw0 = cpu_to_le64(qw0);
535
536
537 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
538 itct->sas_addr = __swab64(itct->sas_addr);
539
540
541 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
542 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) |
543 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) |
544 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF));
545}
546
547static void free_device_v1_hw(struct hisi_hba *hisi_hba,
548 struct hisi_sas_device *sas_dev)
549{
550 u64 dev_id = sas_dev->device_id;
551 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
552 u64 qw0;
553 u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
554
555 reg_val |= CFG_AGING_TIME_ITCT_REL_MSK;
556 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
557
558
559 udelay(1);
560 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
561 reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
562 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
563
564 qw0 = cpu_to_le64(itct->qw0);
565 qw0 &= ~ITCT_HDR_VALID_MSK;
566 itct->qw0 = cpu_to_le64(qw0);
567}
568
569static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
570{
571 int i;
572 unsigned long end_time;
573 u32 val;
574 struct device *dev = &hisi_hba->pdev->dev;
575
576 for (i = 0; i < hisi_hba->n_phy; i++) {
577 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
578
579 phy_ctrl |= PHY_CTRL_RESET_MSK;
580 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
581 }
582 msleep(1);
583
584
585 for (i = 0; i < hisi_hba->n_phy; i++) {
586 u32 dma_tx_status, dma_rx_status;
587
588 end_time = jiffies + msecs_to_jiffies(1000);
589
590 while (1) {
591 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
592 DMA_TX_STATUS);
593 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
594 DMA_RX_STATUS);
595
596 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
597 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
598 break;
599
600 msleep(20);
601 if (time_after(jiffies, end_time))
602 return -EIO;
603 }
604 }
605
606
607 end_time = jiffies + msecs_to_jiffies(1000);
608 while (1) {
609 u32 axi_status =
610 hisi_sas_read32(hisi_hba, AXI_CFG);
611
612 if (axi_status == 0)
613 break;
614
615 msleep(20);
616 if (time_after(jiffies, end_time))
617 return -EIO;
618 }
619
620 if (ACPI_HANDLE(dev)) {
621 acpi_status s;
622
623 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
624 if (ACPI_FAILURE(s)) {
625 dev_err(dev, "Reset failed\n");
626 return -EIO;
627 }
628 } else if (hisi_hba->ctrl) {
629
630
631 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
632 RESET_VALUE);
633 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
634 RESET_VALUE);
635 msleep(1);
636 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
637 if (RESET_VALUE != (val & RESET_VALUE)) {
638 dev_err(dev, "Reset failed\n");
639 return -EIO;
640 }
641
642
643
644 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
645 RESET_VALUE);
646 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
647 RESET_VALUE);
648 msleep(1);
649 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
650 if (val & RESET_VALUE) {
651 dev_err(dev, "De-reset failed\n");
652 return -EIO;
653 }
654 } else
655 dev_warn(dev, "no reset method\n");
656
657 return 0;
658}
659
660static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
661{
662 int i;
663
664
665 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
666 (u32)((1ULL << hisi_hba->queue_count) - 1));
667 hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
668 hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1);
669 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
670 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401);
671 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64);
672 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
673 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64);
674 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710);
675 hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
676 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12);
677 hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40);
678 hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2);
679 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
680 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0);
681 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1);
682 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
683 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
684 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff);
685 hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0);
686 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
687 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0);
688 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
689 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0);
690 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0);
691 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2);
692 hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000);
693
694 for (i = 0; i < hisi_hba->n_phy; i++) {
695 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a);
696 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080);
697 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00);
698 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000);
699 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
700 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0);
701 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
702 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0);
703 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a);
704 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3);
705 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8);
706 }
707
708 for (i = 0; i < hisi_hba->queue_count; i++) {
709
710 hisi_sas_write32(hisi_hba,
711 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
712 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
713
714 hisi_sas_write32(hisi_hba,
715 DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
716 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
717
718 hisi_sas_write32(hisi_hba,
719 DLVRY_Q_0_DEPTH + (i * 0x14),
720 HISI_SAS_QUEUE_SLOTS);
721
722
723 hisi_sas_write32(hisi_hba,
724 COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
725 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
726
727 hisi_sas_write32(hisi_hba,
728 COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
729 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
730
731 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
732 HISI_SAS_QUEUE_SLOTS);
733 }
734
735
736 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
737 lower_32_bits(hisi_hba->itct_dma));
738
739 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
740 upper_32_bits(hisi_hba->itct_dma));
741
742
743 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
744 lower_32_bits(hisi_hba->iost_dma));
745
746 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
747 upper_32_bits(hisi_hba->iost_dma));
748
749
750 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO,
751 lower_32_bits(hisi_hba->breakpoint_dma));
752
753 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI,
754 upper_32_bits(hisi_hba->breakpoint_dma));
755}
756
757static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
758{
759 struct device *dev = &hisi_hba->pdev->dev;
760 int rc;
761
762 rc = reset_hw_v1_hw(hisi_hba);
763 if (rc) {
764 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
765 return rc;
766 }
767
768 msleep(100);
769 init_reg_v1_hw(hisi_hba);
770
771 return 0;
772}
773
774static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
775{
776 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
777
778 cfg |= PHY_CFG_ENA_MSK;
779 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
780}
781
782static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
783{
784 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
785
786 cfg &= ~PHY_CFG_ENA_MSK;
787 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
788}
789
790static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
791{
792 config_id_frame_v1_hw(hisi_hba, phy_no);
793 config_phy_opt_mode_v1_hw(hisi_hba, phy_no);
794 config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no);
795 enable_phy_v1_hw(hisi_hba, phy_no);
796}
797
798static void stop_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
799{
800 disable_phy_v1_hw(hisi_hba, phy_no);
801}
802
803static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
804{
805 stop_phy_v1_hw(hisi_hba, phy_no);
806 msleep(100);
807 start_phy_v1_hw(hisi_hba, phy_no);
808}
809
810static void start_phys_v1_hw(unsigned long data)
811{
812 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
813 int i;
814
815 for (i = 0; i < hisi_hba->n_phy; i++) {
816 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
817 start_phy_v1_hw(hisi_hba, i);
818 }
819}
820
821static void phys_init_v1_hw(struct hisi_hba *hisi_hba)
822{
823 int i;
824 struct timer_list *timer = &hisi_hba->timer;
825
826 for (i = 0; i < hisi_hba->n_phy; i++) {
827 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
828 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
829 }
830
831 setup_timer(timer, start_phys_v1_hw, (unsigned long)hisi_hba);
832 mod_timer(timer, jiffies + HZ);
833}
834
835static void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
836{
837 u32 sl_control;
838
839 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
840 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
841 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
842 msleep(1);
843 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
844 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
845 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
846}
847
848static enum sas_linkrate phy_get_max_linkrate_v1_hw(void)
849{
850 return SAS_LINK_RATE_6_0_GBPS;
851}
852
853static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no,
854 struct sas_phy_linkrates *r)
855{
856 u32 prog_phy_link_rate =
857 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
858 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
859 struct asd_sas_phy *sas_phy = &phy->sas_phy;
860 int i;
861 enum sas_linkrate min, max;
862 u32 rate_mask = 0;
863
864 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
865 max = sas_phy->phy->maximum_linkrate;
866 min = r->minimum_linkrate;
867 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
868 max = r->maximum_linkrate;
869 min = sas_phy->phy->minimum_linkrate;
870 } else
871 return;
872
873 sas_phy->phy->maximum_linkrate = max;
874 sas_phy->phy->minimum_linkrate = min;
875
876 min -= SAS_LINK_RATE_1_5_GBPS;
877 max -= SAS_LINK_RATE_1_5_GBPS;
878
879 for (i = 0; i <= max; i++)
880 rate_mask |= 1 << (i * 2);
881
882 prog_phy_link_rate &= ~0xff;
883 prog_phy_link_rate |= rate_mask;
884
885 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
886 prog_phy_link_rate);
887
888 phy_hard_reset_v1_hw(hisi_hba, phy_no);
889}
890
891static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
892{
893 int i, bitmap = 0;
894 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
895
896 for (i = 0; i < hisi_hba->n_phy; i++)
897 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
898 bitmap |= 1 << i;
899
900 return bitmap;
901}
902
903
904
905
906
907
908
909
910static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id,
911 int *q, int *s)
912{
913 struct device *dev = &hisi_hba->pdev->dev;
914 struct hisi_sas_dq *dq;
915 u32 r, w;
916 int queue = dev_id % hisi_hba->queue_count;
917
918 dq = &hisi_hba->dq[queue];
919 w = dq->wr_point;
920 r = hisi_sas_read32_relaxed(hisi_hba,
921 DLVRY_Q_0_RD_PTR + (queue * 0x14));
922 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
923 dev_warn(dev, "could not find free slot\n");
924 return -EAGAIN;
925 }
926
927 *q = queue;
928 *s = w;
929 return 0;
930}
931
932static void start_delivery_v1_hw(struct hisi_hba *hisi_hba)
933{
934 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
935 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
936 struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
937
938 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
939 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
940 dq->wr_point);
941}
942
943static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
944 struct hisi_sas_slot *slot,
945 struct hisi_sas_cmd_hdr *hdr,
946 struct scatterlist *scatter,
947 int n_elem)
948{
949 struct device *dev = &hisi_hba->pdev->dev;
950 struct scatterlist *sg;
951 int i;
952
953 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
954 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
955 n_elem);
956 return -EINVAL;
957 }
958
959 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
960 &slot->sge_page_dma);
961 if (!slot->sge_page)
962 return -ENOMEM;
963
964 for_each_sg(scatter, sg, n_elem, i) {
965 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
966
967 entry->addr = cpu_to_le64(sg_dma_address(sg));
968 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
969 entry->data_len = cpu_to_le32(sg_dma_len(sg));
970 entry->data_off = 0;
971 }
972
973 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
974
975 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
976
977 return 0;
978}
979
980static int prep_smp_v1_hw(struct hisi_hba *hisi_hba,
981 struct hisi_sas_slot *slot)
982{
983 struct sas_task *task = slot->task;
984 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
985 struct domain_device *device = task->dev;
986 struct device *dev = &hisi_hba->pdev->dev;
987 struct hisi_sas_port *port = slot->port;
988 struct scatterlist *sg_req, *sg_resp;
989 struct hisi_sas_device *sas_dev = device->lldd_dev;
990 dma_addr_t req_dma_addr;
991 unsigned int req_len, resp_len;
992 int elem, rc;
993
994
995
996
997
998 sg_req = &task->smp_task.smp_req;
999 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1000 if (!elem)
1001 return -ENOMEM;
1002 req_len = sg_dma_len(sg_req);
1003 req_dma_addr = sg_dma_address(sg_req);
1004
1005
1006 sg_resp = &task->smp_task.smp_resp;
1007 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1008 if (!elem) {
1009 rc = -ENOMEM;
1010 goto err_out_req;
1011 }
1012 resp_len = sg_dma_len(sg_resp);
1013 if ((req_len & 0x3) || (resp_len & 0x3)) {
1014 rc = -EINVAL;
1015 goto err_out_resp;
1016 }
1017
1018
1019
1020 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1021 (1 << CMD_HDR_PRIORITY_OFF) |
1022 (1 << CMD_HDR_MODE_OFF) |
1023 (2 << CMD_HDR_CMD_OFF));
1024
1025
1026 hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF);
1027
1028
1029 hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) |
1030 (HISI_SAS_MAX_SMP_RESP_SZ/4 <<
1031 CMD_HDR_MRFL_OFF));
1032
1033 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1034
1035 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1036 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1037
1038 return 0;
1039
1040err_out_resp:
1041 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1042 DMA_FROM_DEVICE);
1043err_out_req:
1044 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1045 DMA_TO_DEVICE);
1046 return rc;
1047}
1048
1049static int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
1050 struct hisi_sas_slot *slot, int is_tmf,
1051 struct hisi_sas_tmf_task *tmf)
1052{
1053 struct sas_task *task = slot->task;
1054 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1055 struct domain_device *device = task->dev;
1056 struct hisi_sas_device *sas_dev = device->lldd_dev;
1057 struct hisi_sas_port *port = slot->port;
1058 struct sas_ssp_task *ssp_task = &task->ssp_task;
1059 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1060 int has_data = 0, rc, priority = is_tmf;
1061 u8 *buf_cmd, fburst = 0;
1062 u32 dw1, dw2;
1063
1064
1065 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1066 (0x2 << CMD_HDR_TLR_CTRL_OFF) |
1067 (port->id << CMD_HDR_PORT_OFF) |
1068 (priority << CMD_HDR_PRIORITY_OFF) |
1069 (1 << CMD_HDR_MODE_OFF) |
1070 (1 << CMD_HDR_CMD_OFF));
1071
1072 dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
1073
1074 if (is_tmf) {
1075 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1076 } else {
1077 switch (scsi_cmnd->sc_data_direction) {
1078 case DMA_TO_DEVICE:
1079 dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1080 has_data = 1;
1081 break;
1082 case DMA_FROM_DEVICE:
1083 dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1084 has_data = 1;
1085 break;
1086 default:
1087 dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1088 }
1089 }
1090
1091
1092 dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF;
1093 hdr->dw1 = cpu_to_le32(dw1);
1094
1095 if (is_tmf) {
1096 dw2 = ((sizeof(struct ssp_tmf_iu) +
1097 sizeof(struct ssp_frame_hdr)+3)/4) <<
1098 CMD_HDR_CFL_OFF;
1099 } else {
1100 dw2 = ((sizeof(struct ssp_command_iu) +
1101 sizeof(struct ssp_frame_hdr)+3)/4) <<
1102 CMD_HDR_CFL_OFF;
1103 }
1104
1105 dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF;
1106
1107 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1108
1109 if (has_data) {
1110 rc = prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter,
1111 slot->n_elem);
1112 if (rc)
1113 return rc;
1114 }
1115
1116 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1117 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1118 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1119
1120 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
1121 if (task->ssp_task.enable_first_burst) {
1122 fburst = (1 << 7);
1123 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF;
1124 }
1125 hdr->dw2 = cpu_to_le32(dw2);
1126
1127 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1128 if (!is_tmf) {
1129 buf_cmd[9] = fburst | task->ssp_task.task_attr |
1130 (task->ssp_task.task_prio << 3);
1131 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1132 task->ssp_task.cmd->cmd_len);
1133 } else {
1134 buf_cmd[10] = tmf->tmf;
1135 switch (tmf->tmf) {
1136 case TMF_ABORT_TASK:
1137 case TMF_QUERY_TASK:
1138 buf_cmd[12] =
1139 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1140 buf_cmd[13] =
1141 tmf->tag_of_task_to_be_managed & 0xff;
1142 break;
1143 default:
1144 break;
1145 }
1146 }
1147
1148 return 0;
1149}
1150
1151
1152static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
1153 struct sas_task *task,
1154 struct hisi_sas_slot *slot)
1155{
1156 struct task_status_struct *ts = &task->task_status;
1157 struct hisi_sas_err_record_v1 *err_record = slot->status_buffer;
1158 struct device *dev = &hisi_hba->pdev->dev;
1159
1160 switch (task->task_proto) {
1161 case SAS_PROTOCOL_SSP:
1162 {
1163 int error = -1;
1164 u32 dma_err_type = cpu_to_le32(err_record->dma_err_type);
1165 u32 dma_tx_err_type = ((dma_err_type &
1166 ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
1167 ERR_HDR_DMA_TX_ERR_TYPE_OFF;
1168 u32 dma_rx_err_type = ((dma_err_type &
1169 ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
1170 ERR_HDR_DMA_RX_ERR_TYPE_OFF;
1171 u32 trans_tx_fail_type =
1172 cpu_to_le32(err_record->trans_tx_fail_type);
1173 u32 trans_rx_fail_type =
1174 cpu_to_le32(err_record->trans_rx_fail_type);
1175
1176 if (dma_tx_err_type) {
1177
1178 error = ffs(dma_tx_err_type)
1179 - 1 + DMA_TX_ERR_BASE;
1180 } else if (dma_rx_err_type) {
1181
1182 error = ffs(dma_rx_err_type)
1183 - 1 + DMA_RX_ERR_BASE;
1184 } else if (trans_tx_fail_type) {
1185
1186 error = ffs(trans_tx_fail_type)
1187 - 1 + TRANS_TX_FAIL_BASE;
1188 } else if (trans_rx_fail_type) {
1189
1190 error = ffs(trans_rx_fail_type)
1191 - 1 + TRANS_RX_FAIL_BASE;
1192 }
1193
1194 switch (error) {
1195 case DMA_TX_DATA_UNDERFLOW_ERR:
1196 case DMA_RX_DATA_UNDERFLOW_ERR:
1197 {
1198 ts->residual = 0;
1199 ts->stat = SAS_DATA_UNDERRUN;
1200 break;
1201 }
1202 case DMA_TX_DATA_SGL_OVERFLOW_ERR:
1203 case DMA_TX_DIF_SGL_OVERFLOW_ERR:
1204 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR:
1205 case DMA_RX_DATA_OVERFLOW_ERR:
1206 case TRANS_RX_FRAME_OVERRUN_ERR:
1207 case TRANS_RX_LINK_BUF_OVERRUN_ERR:
1208 {
1209 ts->stat = SAS_DATA_OVERRUN;
1210 ts->residual = 0;
1211 break;
1212 }
1213 case TRANS_TX_PHY_NOT_ENABLE_ERR:
1214 {
1215 ts->stat = SAS_PHY_DOWN;
1216 break;
1217 }
1218 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR:
1219 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR:
1220 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR:
1221 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR:
1222 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR:
1223 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR:
1224 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR:
1225 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR:
1226 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR:
1227 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR:
1228 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR:
1229 case TRANS_TX_OPEN_RETRY_ERR:
1230 {
1231 ts->stat = SAS_OPEN_REJECT;
1232 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1233 break;
1234 }
1235 case TRANS_TX_OPEN_TIMEOUT_ERR:
1236 {
1237 ts->stat = SAS_OPEN_TO;
1238 break;
1239 }
1240 case TRANS_TX_NAK_RECEIVE_ERR:
1241 case TRANS_TX_ACK_NAK_TIMEOUT_ERR:
1242 {
1243 ts->stat = SAS_NAK_R_ERR;
1244 break;
1245 }
1246 case TRANS_TX_CREDIT_TIMEOUT_ERR:
1247 case TRANS_TX_CLOSE_NORMAL_ERR:
1248 {
1249
1250 ts->stat = SAS_QUEUE_FULL;
1251 slot->abort = 1;
1252 break;
1253 }
1254 default:
1255 {
1256 ts->stat = SAM_STAT_CHECK_CONDITION;
1257 break;
1258 }
1259 }
1260 }
1261 break;
1262 case SAS_PROTOCOL_SMP:
1263 ts->stat = SAM_STAT_CHECK_CONDITION;
1264 break;
1265
1266 case SAS_PROTOCOL_SATA:
1267 case SAS_PROTOCOL_STP:
1268 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1269 {
1270 dev_err(dev, "slot err: SATA/STP not supported");
1271 }
1272 break;
1273 default:
1274 break;
1275 }
1276
1277}
1278
1279static int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
1280 struct hisi_sas_slot *slot)
1281{
1282 struct sas_task *task = slot->task;
1283 struct hisi_sas_device *sas_dev;
1284 struct device *dev = &hisi_hba->pdev->dev;
1285 struct task_status_struct *ts;
1286 struct domain_device *device;
1287 enum exec_status sts;
1288 struct hisi_sas_complete_v1_hdr *complete_queue =
1289 hisi_hba->complete_hdr[slot->cmplt_queue];
1290 struct hisi_sas_complete_v1_hdr *complete_hdr;
1291 unsigned long flags;
1292 u32 cmplt_hdr_data;
1293
1294 complete_hdr = &complete_queue[slot->cmplt_queue_slot];
1295 cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
1296
1297 if (unlikely(!task || !task->lldd_task || !task->dev))
1298 return -EINVAL;
1299
1300 ts = &task->task_status;
1301 device = task->dev;
1302 sas_dev = device->lldd_dev;
1303
1304 spin_lock_irqsave(&task->task_state_lock, flags);
1305 task->task_state_flags &=
1306 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1307 task->task_state_flags |= SAS_TASK_STATE_DONE;
1308 spin_unlock_irqrestore(&task->task_state_lock, flags);
1309
1310 memset(ts, 0, sizeof(*ts));
1311 ts->resp = SAS_TASK_COMPLETE;
1312
1313 if (unlikely(!sas_dev)) {
1314 dev_dbg(dev, "slot complete: port has no device\n");
1315 ts->stat = SAS_PHY_DOWN;
1316 goto out;
1317 }
1318
1319 if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) {
1320 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO);
1321
1322 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK)
1323 dev_err(dev, "slot complete: [%d:%d] has dq IPTT err",
1324 slot->cmplt_queue, slot->cmplt_queue_slot);
1325
1326 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK)
1327 dev_err(dev, "slot complete: [%d:%d] has dq type err",
1328 slot->cmplt_queue, slot->cmplt_queue_slot);
1329
1330 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK)
1331 dev_err(dev, "slot complete: [%d:%d] has dq force phy err",
1332 slot->cmplt_queue, slot->cmplt_queue_slot);
1333
1334 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK)
1335 dev_err(dev, "slot complete: [%d:%d] has dq phy id err",
1336 slot->cmplt_queue, slot->cmplt_queue_slot);
1337
1338 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK)
1339 dev_err(dev, "slot complete: [%d:%d] has dq abort flag err",
1340 slot->cmplt_queue, slot->cmplt_queue_slot);
1341
1342 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK)
1343 dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err",
1344 slot->cmplt_queue, slot->cmplt_queue_slot);
1345
1346 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK)
1347 dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err",
1348 slot->cmplt_queue, slot->cmplt_queue_slot);
1349
1350 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK)
1351 dev_err(dev, "slot complete: [%d:%d] has dq order frame len err",
1352 slot->cmplt_queue, slot->cmplt_queue_slot);
1353
1354 ts->stat = SAS_OPEN_REJECT;
1355 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1356 goto out;
1357 }
1358
1359 if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK &&
1360 !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
1361
1362 slot_err_v1_hw(hisi_hba, task, slot);
1363 if (unlikely(slot->abort)) {
1364 queue_work(hisi_hba->wq, &slot->abort_slot);
1365
1366 return ts->stat;
1367 }
1368 goto out;
1369 }
1370
1371 switch (task->task_proto) {
1372 case SAS_PROTOCOL_SSP:
1373 {
1374 struct ssp_response_iu *iu = slot->status_buffer +
1375 sizeof(struct hisi_sas_err_record);
1376 sas_ssp_task_response(dev, task, iu);
1377 break;
1378 }
1379 case SAS_PROTOCOL_SMP:
1380 {
1381 void *to;
1382 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1383
1384 ts->stat = SAM_STAT_GOOD;
1385 to = kmap_atomic(sg_page(sg_resp));
1386
1387 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1388 DMA_FROM_DEVICE);
1389 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1390 DMA_TO_DEVICE);
1391 memcpy(to + sg_resp->offset,
1392 slot->status_buffer +
1393 sizeof(struct hisi_sas_err_record),
1394 sg_dma_len(sg_resp));
1395 kunmap_atomic(to);
1396 break;
1397 }
1398 case SAS_PROTOCOL_SATA:
1399 case SAS_PROTOCOL_STP:
1400 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1401 dev_err(dev, "slot complete: SATA/STP not supported");
1402 break;
1403
1404 default:
1405 ts->stat = SAM_STAT_CHECK_CONDITION;
1406 break;
1407 }
1408
1409 if (!slot->port->port_attached) {
1410 dev_err(dev, "slot complete: port %d has removed\n",
1411 slot->port->sas_port.id);
1412 ts->stat = SAS_PHY_DOWN;
1413 }
1414
1415out:
1416 if (sas_dev)
1417 atomic64_dec(&sas_dev->running_req);
1418
1419 hisi_sas_slot_task_free(hisi_hba, task, slot);
1420 sts = ts->stat;
1421
1422 if (task->task_done)
1423 task->task_done(task);
1424
1425 return sts;
1426}
1427
1428
1429static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
1430{
1431 struct hisi_sas_phy *phy = p;
1432 struct hisi_hba *hisi_hba = phy->hisi_hba;
1433 struct device *dev = &hisi_hba->pdev->dev;
1434 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1435 int i, phy_no = sas_phy->id;
1436 u32 irq_value, context, port_id, link_rate;
1437 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1438 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1439 irqreturn_t res = IRQ_HANDLED;
1440
1441 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1442 if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) {
1443 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n",
1444 irq_value);
1445 res = IRQ_NONE;
1446 goto end;
1447 }
1448
1449 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1450 if (context & 1 << phy_no) {
1451 dev_err(dev, "phyup: phy%d SATA attached equipment\n",
1452 phy_no);
1453 goto end;
1454 }
1455
1456 port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no))
1457 & 0xf;
1458 if (port_id == 0xf) {
1459 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1460 res = IRQ_NONE;
1461 goto end;
1462 }
1463
1464 for (i = 0; i < 6; i++) {
1465 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1466 RX_IDAF_DWORD0 + (i * 4));
1467 frame_rcvd[i] = __swab32(idaf);
1468 }
1469
1470
1471 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1472 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1473 sas_phy->linkrate = link_rate;
1474 sas_phy->oob_mode = SAS_OOB_MODE;
1475 memcpy(sas_phy->attached_sas_addr,
1476 &id->sas_addr, SAS_ADDR_SIZE);
1477 dev_info(dev, "phyup: phy%d link_rate=%d\n",
1478 phy_no, link_rate);
1479 phy->port_id = port_id;
1480 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1481 phy->phy_type |= PORT_TYPE_SAS;
1482 phy->phy_attached = 1;
1483 phy->identify.device_type = id->dev_type;
1484 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1485 if (phy->identify.device_type == SAS_END_DEVICE)
1486 phy->identify.target_port_protocols =
1487 SAS_PROTOCOL_SSP;
1488 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1489 phy->identify.target_port_protocols =
1490 SAS_PROTOCOL_SMP;
1491 queue_work(hisi_hba->wq, &phy->phyup_ws);
1492
1493end:
1494 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1495 CHL_INT2_SL_PHY_ENA_MSK);
1496
1497 if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) {
1498 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1499
1500 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK;
1501 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0);
1502 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee);
1503 }
1504
1505 return res;
1506}
1507
1508static irqreturn_t int_bcast_v1_hw(int irq, void *p)
1509{
1510 struct hisi_sas_phy *phy = p;
1511 struct hisi_hba *hisi_hba = phy->hisi_hba;
1512 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1513 struct sas_ha_struct *sha = &hisi_hba->sha;
1514 struct device *dev = &hisi_hba->pdev->dev;
1515 int phy_no = sas_phy->id;
1516 u32 irq_value;
1517 irqreturn_t res = IRQ_HANDLED;
1518
1519 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1520
1521 if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
1522 dev_err(dev, "bcast: irq_value = %x not set enable bit",
1523 irq_value);
1524 res = IRQ_NONE;
1525 goto end;
1526 }
1527
1528 sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1529
1530end:
1531 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1532 CHL_INT2_SL_RX_BC_ACK_MSK);
1533
1534 return res;
1535}
1536
1537static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
1538{
1539 struct hisi_sas_phy *phy = p;
1540 struct hisi_hba *hisi_hba = phy->hisi_hba;
1541 struct device *dev = &hisi_hba->pdev->dev;
1542 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1543 u32 irq_value, irq_mask_old;
1544 int phy_no = sas_phy->id;
1545
1546
1547 irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK);
1548 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff);
1549
1550
1551 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1552
1553 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) {
1554 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1555
1556 hisi_sas_phy_down(hisi_hba, phy_no,
1557 (phy_state & 1 << phy_no) ? 1 : 0);
1558 }
1559
1560 if (irq_value & CHL_INT0_ID_TIMEOUT_MSK)
1561 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n",
1562 phy_no);
1563
1564 if (irq_value & CHL_INT0_DWS_LOST_MSK)
1565 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no);
1566
1567 if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK)
1568 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n",
1569 phy_no);
1570
1571 if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK ||
1572 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK)
1573 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n",
1574 phy_no);
1575
1576 if (irq_value & CHL_INT0_SL_PS_FAIL_OFF)
1577 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no);
1578
1579
1580 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value);
1581
1582 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK)
1583 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1584 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1585 else
1586 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1587 irq_mask_old);
1588
1589 return IRQ_HANDLED;
1590}
1591
1592static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
1593{
1594 struct hisi_sas_cq *cq = p;
1595 struct hisi_hba *hisi_hba = cq->hisi_hba;
1596 struct hisi_sas_slot *slot;
1597 int queue = cq->id;
1598 struct hisi_sas_complete_v1_hdr *complete_queue =
1599 (struct hisi_sas_complete_v1_hdr *)
1600 hisi_hba->complete_hdr[queue];
1601 u32 irq_value, rd_point = cq->rd_point, wr_point;
1602
1603 spin_lock(&hisi_hba->lock);
1604 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1605
1606 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1607 wr_point = hisi_sas_read32(hisi_hba,
1608 COMPL_Q_0_WR_PTR + (0x14 * queue));
1609
1610 while (rd_point != wr_point) {
1611 struct hisi_sas_complete_v1_hdr *complete_hdr;
1612 int idx;
1613 u32 cmplt_hdr_data;
1614
1615 complete_hdr = &complete_queue[rd_point];
1616 cmplt_hdr_data = cpu_to_le32(complete_hdr->data);
1617 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
1618 CMPLT_HDR_IPTT_OFF;
1619 slot = &hisi_hba->slot_info[idx];
1620
1621
1622
1623
1624
1625 slot->cmplt_queue_slot = rd_point;
1626 slot->cmplt_queue = queue;
1627 slot_complete_v1_hw(hisi_hba, slot);
1628
1629 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1630 rd_point = 0;
1631 }
1632
1633
1634 cq->rd_point = rd_point;
1635 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1636 spin_unlock(&hisi_hba->lock);
1637
1638 return IRQ_HANDLED;
1639}
1640
1641static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
1642{
1643 struct hisi_hba *hisi_hba = p;
1644 struct device *dev = &hisi_hba->pdev->dev;
1645 u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1646
1647 if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
1648 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1649
1650 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n",
1651 dev_name(dev), ecc_err);
1652 }
1653
1654 if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) {
1655 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) &
1656 HGC_DQ_ECC_ADDR_BAD_MSK) >>
1657 HGC_DQ_ECC_ADDR_BAD_OFF;
1658
1659 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n",
1660 dev_name(dev), addr);
1661 }
1662
1663 if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) {
1664 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1665
1666 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n",
1667 dev_name(dev), ecc_err);
1668 }
1669
1670 if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) {
1671 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) &
1672 HGC_IOST_ECC_ADDR_BAD_MSK) >>
1673 HGC_IOST_ECC_ADDR_BAD_OFF;
1674
1675 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n",
1676 dev_name(dev), addr);
1677 }
1678
1679 if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) {
1680 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) &
1681 HGC_ITCT_ECC_ADDR_BAD_MSK) >>
1682 HGC_ITCT_ECC_ADDR_BAD_OFF;
1683
1684 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n",
1685 dev_name(dev), addr);
1686 }
1687
1688 if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) {
1689 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1690
1691 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n",
1692 dev_name(dev), ecc_err);
1693 }
1694
1695 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f);
1696
1697 return IRQ_HANDLED;
1698}
1699
1700static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
1701{
1702 struct hisi_hba *hisi_hba = p;
1703 struct device *dev = &hisi_hba->pdev->dev;
1704 u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
1705 u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
1706
1707 if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK)
1708 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n",
1709 dev_name(dev), axi_info);
1710
1711 if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK)
1712 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n",
1713 dev_name(dev), axi_info);
1714
1715 if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK)
1716 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n",
1717 dev_name(dev), axi_info);
1718
1719 if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK)
1720 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n",
1721 dev_name(dev), axi_info);
1722
1723 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000);
1724
1725 return IRQ_HANDLED;
1726}
1727
1728static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1729 int_bcast_v1_hw,
1730 int_phyup_v1_hw,
1731 int_abnormal_v1_hw
1732};
1733
1734static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = {
1735 fatal_ecc_int_v1_hw,
1736 fatal_axi_int_v1_hw
1737};
1738
1739static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
1740{
1741 struct platform_device *pdev = hisi_hba->pdev;
1742 struct device *dev = &pdev->dev;
1743 int i, j, irq, rc, idx;
1744
1745 for (i = 0; i < hisi_hba->n_phy; i++) {
1746 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1747
1748 idx = i * HISI_SAS_PHY_INT_NR;
1749 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) {
1750 irq = platform_get_irq(pdev, idx);
1751 if (!irq) {
1752 dev_err(dev,
1753 "irq init: fail map phy interrupt %d\n",
1754 idx);
1755 return -ENOENT;
1756 }
1757
1758 rc = devm_request_irq(dev, irq, phy_interrupts[j], 0,
1759 DRV_NAME " phy", phy);
1760 if (rc) {
1761 dev_err(dev, "irq init: could not request "
1762 "phy interrupt %d, rc=%d\n",
1763 irq, rc);
1764 return -ENOENT;
1765 }
1766 }
1767 }
1768
1769 idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR;
1770 for (i = 0; i < hisi_hba->queue_count; i++, idx++) {
1771 irq = platform_get_irq(pdev, idx);
1772 if (!irq) {
1773 dev_err(dev, "irq init: could not map cq interrupt %d\n",
1774 idx);
1775 return -ENOENT;
1776 }
1777
1778 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0,
1779 DRV_NAME " cq", &hisi_hba->cq[i]);
1780 if (rc) {
1781 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
1782 irq, rc);
1783 return -ENOENT;
1784 }
1785 }
1786
1787 idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count;
1788 for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) {
1789 irq = platform_get_irq(pdev, idx);
1790 if (!irq) {
1791 dev_err(dev, "irq init: could not map fatal interrupt %d\n",
1792 idx);
1793 return -ENOENT;
1794 }
1795
1796 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
1797 DRV_NAME " fatal", hisi_hba);
1798 if (rc) {
1799 dev_err(dev,
1800 "irq init: could not request fatal interrupt %d, rc=%d\n",
1801 irq, rc);
1802 return -ENOENT;
1803 }
1804 }
1805
1806 return 0;
1807}
1808
1809static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba)
1810{
1811 int i;
1812 u32 val;
1813
1814 for (i = 0; i < hisi_hba->n_phy; i++) {
1815
1816 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0);
1817 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val);
1818 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1);
1819 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val);
1820 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2);
1821 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val);
1822
1823
1824 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee);
1825 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff);
1826 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a);
1827
1828
1829 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK,
1830 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1831 }
1832
1833 return 0;
1834}
1835
1836static int hisi_sas_v1_init(struct hisi_hba *hisi_hba)
1837{
1838 int rc;
1839
1840 rc = hw_init_v1_hw(hisi_hba);
1841 if (rc)
1842 return rc;
1843
1844 rc = interrupt_init_v1_hw(hisi_hba);
1845 if (rc)
1846 return rc;
1847
1848 rc = interrupt_openall_v1_hw(hisi_hba);
1849 if (rc)
1850 return rc;
1851
1852 return 0;
1853}
1854
1855static const struct hisi_sas_hw hisi_sas_v1_hw = {
1856 .hw_init = hisi_sas_v1_init,
1857 .setup_itct = setup_itct_v1_hw,
1858 .sl_notify = sl_notify_v1_hw,
1859 .free_device = free_device_v1_hw,
1860 .prep_smp = prep_smp_v1_hw,
1861 .prep_ssp = prep_ssp_v1_hw,
1862 .get_free_slot = get_free_slot_v1_hw,
1863 .start_delivery = start_delivery_v1_hw,
1864 .slot_complete = slot_complete_v1_hw,
1865 .phys_init = phys_init_v1_hw,
1866 .phy_enable = enable_phy_v1_hw,
1867 .phy_disable = disable_phy_v1_hw,
1868 .phy_hard_reset = phy_hard_reset_v1_hw,
1869 .phy_set_linkrate = phy_set_linkrate_v1_hw,
1870 .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw,
1871 .get_wideport_bitmap = get_wideport_bitmap_v1_hw,
1872 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V1_HW,
1873 .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),
1874};
1875
1876static int hisi_sas_v1_probe(struct platform_device *pdev)
1877{
1878 return hisi_sas_probe(pdev, &hisi_sas_v1_hw);
1879}
1880
1881static int hisi_sas_v1_remove(struct platform_device *pdev)
1882{
1883 return hisi_sas_remove(pdev);
1884}
1885
1886static const struct of_device_id sas_v1_of_match[] = {
1887 { .compatible = "hisilicon,hip05-sas-v1",},
1888 {},
1889};
1890MODULE_DEVICE_TABLE(of, sas_v1_of_match);
1891
1892static const struct acpi_device_id sas_v1_acpi_match[] = {
1893 { "HISI0161", 0 },
1894 { }
1895};
1896
1897MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match);
1898
1899static struct platform_driver hisi_sas_v1_driver = {
1900 .probe = hisi_sas_v1_probe,
1901 .remove = hisi_sas_v1_remove,
1902 .driver = {
1903 .name = DRV_NAME,
1904 .of_match_table = sas_v1_of_match,
1905 .acpi_match_table = ACPI_PTR(sas_v1_acpi_match),
1906 },
1907};
1908
1909module_platform_driver(hisi_sas_v1_driver);
1910
1911MODULE_LICENSE("GPL");
1912MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1913MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver");
1914MODULE_ALIAS("platform:" DRV_NAME);
1915
