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16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/interrupt.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/serial.h>
22#include <linux/serial_reg.h>
23
24#include "dgnc_driver.h"
25#include "dgnc_neo.h"
26#include "dgnc_tty.h"
27
28static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
29static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
30static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
31static inline void neo_clear_break(struct channel_t *ch, int force);
32static inline void neo_set_cts_flow_control(struct channel_t *ch);
33static inline void neo_set_rts_flow_control(struct channel_t *ch);
34static inline void neo_set_ixon_flow_control(struct channel_t *ch);
35static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
36static inline void neo_set_no_output_flow_control(struct channel_t *ch);
37static inline void neo_set_no_input_flow_control(struct channel_t *ch);
38static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
39static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
40static void neo_tasklet(unsigned long data);
41static void neo_vpd(struct dgnc_board *brd);
42static void neo_uart_init(struct channel_t *ch);
43static void neo_uart_off(struct channel_t *ch);
44static int neo_drain(struct tty_struct *tty, uint seconds);
45static void neo_param(struct tty_struct *tty);
46static void neo_assert_modem_signals(struct channel_t *ch);
47static void neo_flush_uart_write(struct channel_t *ch);
48static void neo_flush_uart_read(struct channel_t *ch);
49static void neo_disable_receiver(struct channel_t *ch);
50static void neo_enable_receiver(struct channel_t *ch);
51static void neo_send_break(struct channel_t *ch, int msecs);
52static void neo_send_start_character(struct channel_t *ch);
53static void neo_send_stop_character(struct channel_t *ch);
54static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
55static uint neo_get_uart_bytes_left(struct channel_t *ch);
56static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
57static irqreturn_t neo_intr(int irq, void *voidbrd);
58
59struct board_ops dgnc_neo_ops = {
60 .tasklet = neo_tasklet,
61 .intr = neo_intr,
62 .uart_init = neo_uart_init,
63 .uart_off = neo_uart_off,
64 .drain = neo_drain,
65 .param = neo_param,
66 .vpd = neo_vpd,
67 .assert_modem_signals = neo_assert_modem_signals,
68 .flush_uart_write = neo_flush_uart_write,
69 .flush_uart_read = neo_flush_uart_read,
70 .disable_receiver = neo_disable_receiver,
71 .enable_receiver = neo_enable_receiver,
72 .send_break = neo_send_break,
73 .send_start_character = neo_send_start_character,
74 .send_stop_character = neo_send_stop_character,
75 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
76 .get_uart_bytes_left = neo_get_uart_bytes_left,
77 .send_immediate_char = neo_send_immediate_char
78};
79
80
81
82
83
84
85
86
87
88static inline void neo_pci_posting_flush(struct dgnc_board *bd)
89{
90 readb(bd->re_map_membase + 0x8D);
91}
92
93static inline void neo_set_cts_flow_control(struct channel_t *ch)
94{
95 unsigned char ier = readb(&ch->ch_neo_uart->ier);
96 unsigned char efr = readb(&ch->ch_neo_uart->efr);
97
98
99 ier |= UART_17158_IER_CTSDSR;
100 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
101
102
103 efr &= ~UART_17158_EFR_IXON;
104
105
106
107
108
109 writeb(0, &ch->ch_neo_uart->efr);
110
111
112 writeb(efr, &ch->ch_neo_uart->efr);
113
114
115 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
116 &ch->ch_neo_uart->fctr);
117
118
119 writeb(8, &ch->ch_neo_uart->tfifo);
120 ch->ch_t_tlevel = 8;
121
122 writeb(ier, &ch->ch_neo_uart->ier);
123
124 neo_pci_posting_flush(ch->ch_bd);
125}
126
127static inline void neo_set_rts_flow_control(struct channel_t *ch)
128{
129 unsigned char ier = readb(&ch->ch_neo_uart->ier);
130 unsigned char efr = readb(&ch->ch_neo_uart->efr);
131
132
133 ier |= UART_17158_IER_RTSDTR;
134 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
135
136
137 ier &= ~UART_17158_IER_XOFF;
138 efr &= ~UART_17158_EFR_IXOFF;
139
140
141
142
143
144 writeb(0, &ch->ch_neo_uart->efr);
145
146
147 writeb(efr, &ch->ch_neo_uart->efr);
148
149 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
150 &ch->ch_neo_uart->fctr);
151 ch->ch_r_watermark = 4;
152
153 writeb(32, &ch->ch_neo_uart->rfifo);
154 ch->ch_r_tlevel = 32;
155
156 writeb(ier, &ch->ch_neo_uart->ier);
157
158
159
160
161
162
163
164 ch->ch_mostat |= UART_MCR_RTS;
165
166 neo_pci_posting_flush(ch->ch_bd);
167}
168
169static inline void neo_set_ixon_flow_control(struct channel_t *ch)
170{
171 unsigned char ier = readb(&ch->ch_neo_uart->ier);
172 unsigned char efr = readb(&ch->ch_neo_uart->efr);
173
174
175 ier &= ~UART_17158_IER_CTSDSR;
176 efr &= ~UART_17158_EFR_CTSDSR;
177
178
179 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
180
181
182
183
184
185 writeb(0, &ch->ch_neo_uart->efr);
186
187
188 writeb(efr, &ch->ch_neo_uart->efr);
189
190 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
191 &ch->ch_neo_uart->fctr);
192 ch->ch_r_watermark = 4;
193
194 writeb(32, &ch->ch_neo_uart->rfifo);
195 ch->ch_r_tlevel = 32;
196
197
198 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
199 writeb(0, &ch->ch_neo_uart->xonchar2);
200
201 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
202 writeb(0, &ch->ch_neo_uart->xoffchar2);
203
204 writeb(ier, &ch->ch_neo_uart->ier);
205
206 neo_pci_posting_flush(ch->ch_bd);
207}
208
209static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
210{
211 unsigned char ier = readb(&ch->ch_neo_uart->ier);
212 unsigned char efr = readb(&ch->ch_neo_uart->efr);
213
214
215 ier &= ~UART_17158_IER_RTSDTR;
216 efr &= ~UART_17158_EFR_RTSDTR;
217
218
219 ier |= UART_17158_IER_XOFF;
220 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
221
222
223
224
225
226 writeb(0, &ch->ch_neo_uart->efr);
227
228
229 writeb(efr, &ch->ch_neo_uart->efr);
230
231
232 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
233 &ch->ch_neo_uart->fctr);
234
235 writeb(8, &ch->ch_neo_uart->tfifo);
236 ch->ch_t_tlevel = 8;
237
238
239 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
240 writeb(0, &ch->ch_neo_uart->xonchar2);
241
242 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
243 writeb(0, &ch->ch_neo_uart->xoffchar2);
244
245 writeb(ier, &ch->ch_neo_uart->ier);
246
247 neo_pci_posting_flush(ch->ch_bd);
248}
249
250static inline void neo_set_no_input_flow_control(struct channel_t *ch)
251{
252 unsigned char ier = readb(&ch->ch_neo_uart->ier);
253 unsigned char efr = readb(&ch->ch_neo_uart->efr);
254
255
256 ier &= ~UART_17158_IER_RTSDTR;
257 efr &= ~UART_17158_EFR_RTSDTR;
258
259
260 ier &= ~UART_17158_IER_XOFF;
261 if (ch->ch_c_iflag & IXON)
262 efr &= ~(UART_17158_EFR_IXOFF);
263 else
264 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
265
266
267
268
269
270 writeb(0, &ch->ch_neo_uart->efr);
271
272
273 writeb(efr, &ch->ch_neo_uart->efr);
274
275
276 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
277 &ch->ch_neo_uart->fctr);
278
279 ch->ch_r_watermark = 0;
280
281 writeb(16, &ch->ch_neo_uart->tfifo);
282 ch->ch_t_tlevel = 16;
283
284 writeb(16, &ch->ch_neo_uart->rfifo);
285 ch->ch_r_tlevel = 16;
286
287 writeb(ier, &ch->ch_neo_uart->ier);
288
289 neo_pci_posting_flush(ch->ch_bd);
290}
291
292static inline void neo_set_no_output_flow_control(struct channel_t *ch)
293{
294 unsigned char ier = readb(&ch->ch_neo_uart->ier);
295 unsigned char efr = readb(&ch->ch_neo_uart->efr);
296
297
298 ier &= ~UART_17158_IER_CTSDSR;
299 efr &= ~UART_17158_EFR_CTSDSR;
300
301
302 if (ch->ch_c_iflag & IXOFF)
303 efr &= ~UART_17158_EFR_IXON;
304 else
305 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
306
307
308
309
310
311 writeb(0, &ch->ch_neo_uart->efr);
312
313
314 writeb(efr, &ch->ch_neo_uart->efr);
315
316
317 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
318 &ch->ch_neo_uart->fctr);
319
320 ch->ch_r_watermark = 0;
321
322 writeb(16, &ch->ch_neo_uart->tfifo);
323 ch->ch_t_tlevel = 16;
324
325 writeb(16, &ch->ch_neo_uart->rfifo);
326 ch->ch_r_tlevel = 16;
327
328 writeb(ier, &ch->ch_neo_uart->ier);
329
330 neo_pci_posting_flush(ch->ch_bd);
331}
332
333
334static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
335{
336
337 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) ||
338 ch->ch_c_cflag & CRTSCTS)
339 return;
340
341
342 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
343 writeb(0, &ch->ch_neo_uart->xonchar2);
344
345 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
346 writeb(0, &ch->ch_neo_uart->xoffchar2);
347
348 neo_pci_posting_flush(ch->ch_bd);
349}
350
351
352static inline void neo_clear_break(struct channel_t *ch, int force)
353{
354 unsigned long flags;
355
356 spin_lock_irqsave(&ch->ch_lock, flags);
357
358 if (!ch->ch_stop_sending_break) {
359 spin_unlock_irqrestore(&ch->ch_lock, flags);
360 return;
361 }
362
363 if (ch->ch_flags & CH_BREAK_SENDING) {
364 if (force ||
365 time_after_eq(jiffies, ch->ch_stop_sending_break)) {
366 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
367
368 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
369 neo_pci_posting_flush(ch->ch_bd);
370 ch->ch_flags &= ~(CH_BREAK_SENDING);
371 ch->ch_stop_sending_break = 0;
372 }
373 }
374 spin_unlock_irqrestore(&ch->ch_lock, flags);
375}
376
377
378static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
379{
380 struct channel_t *ch;
381 unsigned char isr;
382 unsigned char cause;
383 unsigned long flags;
384
385 ch = brd->channels[port];
386 if (!ch)
387 return;
388
389
390 while (1) {
391 isr = readb(&ch->ch_neo_uart->isr_fcr);
392
393 if (isr & UART_IIR_NO_INT)
394 break;
395
396
397
398
399
400 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
401
402 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
403
404 neo_copy_data_from_uart_to_queue(ch);
405
406
407
408
409 spin_lock_irqsave(&ch->ch_lock, flags);
410 dgnc_check_queue_flow_control(ch);
411 spin_unlock_irqrestore(&ch->ch_lock, flags);
412 }
413
414 if (isr & UART_IIR_THRI) {
415 spin_lock_irqsave(&ch->ch_lock, flags);
416 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
417 spin_unlock_irqrestore(&ch->ch_lock, flags);
418 neo_copy_data_from_queue_to_uart(ch);
419 }
420
421 if (isr & UART_17158_IIR_XONXOFF) {
422 cause = readb(&ch->ch_neo_uart->xoffchar1);
423
424
425
426
427
428
429 if (cause == UART_17158_XON_DETECT) {
430
431 if (brd->channels[port]->ch_flags & CH_STOP) {
432 spin_lock_irqsave(&ch->ch_lock,
433 flags);
434 ch->ch_flags &= ~(CH_STOP);
435 spin_unlock_irqrestore(&ch->ch_lock,
436 flags);
437 }
438 } else if (cause == UART_17158_XOFF_DETECT) {
439 if (!(brd->channels[port]->ch_flags &
440 CH_STOP)) {
441 spin_lock_irqsave(&ch->ch_lock,
442 flags);
443 ch->ch_flags |= CH_STOP;
444 spin_unlock_irqrestore(&ch->ch_lock,
445 flags);
446 }
447 }
448 }
449
450 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
451
452
453
454
455
456 cause = readb(&ch->ch_neo_uart->mcr);
457
458 if ((cause & 0x4) == 0) {
459 if (cause & UART_MCR_RTS) {
460 spin_lock_irqsave(&ch->ch_lock,
461 flags);
462 ch->ch_mostat |= UART_MCR_RTS;
463 spin_unlock_irqrestore(&ch->ch_lock,
464 flags);
465 } else {
466 spin_lock_irqsave(&ch->ch_lock,
467 flags);
468 ch->ch_mostat &= ~(UART_MCR_RTS);
469 spin_unlock_irqrestore(&ch->ch_lock,
470 flags);
471 }
472 } else {
473 if (cause & UART_MCR_DTR) {
474 spin_lock_irqsave(&ch->ch_lock,
475 flags);
476 ch->ch_mostat |= UART_MCR_DTR;
477 spin_unlock_irqrestore(&ch->ch_lock,
478 flags);
479 } else {
480 spin_lock_irqsave(&ch->ch_lock,
481 flags);
482 ch->ch_mostat &= ~(UART_MCR_DTR);
483 spin_unlock_irqrestore(&ch->ch_lock,
484 flags);
485 }
486 }
487 }
488
489 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
490 }
491}
492
493static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
494{
495 struct channel_t *ch;
496 int linestatus;
497 unsigned long flags;
498
499 if (!brd)
500 return;
501
502 if (port >= brd->maxports)
503 return;
504
505 ch = brd->channels[port];
506 if (!ch)
507 return;
508
509 linestatus = readb(&ch->ch_neo_uart->lsr);
510
511 ch->ch_cached_lsr |= linestatus;
512
513 if (ch->ch_cached_lsr & UART_LSR_DR) {
514 neo_copy_data_from_uart_to_queue(ch);
515 spin_lock_irqsave(&ch->ch_lock, flags);
516 dgnc_check_queue_flow_control(ch);
517 spin_unlock_irqrestore(&ch->ch_lock, flags);
518 }
519
520
521
522
523
524
525 if (linestatus & UART_LSR_PE)
526 ch->ch_err_parity++;
527
528 if (linestatus & UART_LSR_FE)
529 ch->ch_err_frame++;
530
531 if (linestatus & UART_LSR_BI)
532 ch->ch_err_break++;
533
534 if (linestatus & UART_LSR_OE) {
535
536
537
538
539
540
541
542 ch->ch_err_overrun++;
543 }
544
545 if (linestatus & UART_LSR_THRE) {
546 spin_lock_irqsave(&ch->ch_lock, flags);
547 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
548 spin_unlock_irqrestore(&ch->ch_lock, flags);
549
550 neo_copy_data_from_queue_to_uart(ch);
551 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
552 spin_lock_irqsave(&ch->ch_lock, flags);
553 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
554 spin_unlock_irqrestore(&ch->ch_lock, flags);
555
556 neo_copy_data_from_queue_to_uart(ch);
557 }
558}
559
560
561static void neo_param(struct tty_struct *tty)
562{
563 unsigned char lcr = 0;
564 unsigned char uart_lcr = 0;
565 unsigned char ier = 0;
566 unsigned char uart_ier = 0;
567 uint baud = 9600;
568 int quot = 0;
569 struct dgnc_board *bd;
570 struct channel_t *ch;
571 struct un_t *un;
572
573 if (!tty)
574 return;
575
576 un = (struct un_t *)tty->driver_data;
577 if (!un)
578 return;
579
580 ch = un->un_ch;
581 if (!ch)
582 return;
583
584 bd = ch->ch_bd;
585 if (!bd)
586 return;
587
588
589 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
590 ch->ch_r_head = 0;
591 ch->ch_r_tail = 0;
592 ch->ch_e_head = 0;
593 ch->ch_e_tail = 0;
594 ch->ch_w_head = 0;
595 ch->ch_w_tail = 0;
596
597 neo_flush_uart_write(ch);
598 neo_flush_uart_read(ch);
599
600
601 ch->ch_flags |= (CH_BAUD0);
602 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
603 neo_assert_modem_signals(ch);
604 ch->ch_old_baud = 0;
605 return;
606
607 } else if (ch->ch_custom_speed) {
608 baud = ch->ch_custom_speed;
609
610 if (ch->ch_flags & CH_BAUD0) {
611 ch->ch_flags &= ~(CH_BAUD0);
612
613
614
615
616
617 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
618 ch->ch_mostat |= (UART_MCR_RTS);
619 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
620 ch->ch_mostat |= (UART_MCR_DTR);
621 }
622 } else {
623 int iindex = 0;
624 int jindex = 0;
625
626 ulong bauds[4][16] = {
627 {
628 0, 50, 75, 110,
629 134, 150, 200, 300,
630 600, 1200, 1800, 2400,
631 4800, 9600, 19200, 38400 },
632 {
633 0, 57600, 115200, 230400,
634 460800, 150, 200, 921600,
635 600, 1200, 1800, 2400,
636 4800, 9600, 19200, 38400 },
637 {
638 0, 57600, 76800, 115200,
639 131657, 153600, 230400, 460800,
640 921600, 1200, 1800, 2400,
641 4800, 9600, 19200, 38400 },
642 {
643 0, 57600, 115200, 230400,
644 460800, 150, 200, 921600,
645 600, 1200, 1800, 2400,
646 4800, 9600, 19200, 38400 }
647 };
648
649
650
651
652
653 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
654 (un->un_type == DGNC_PRINT))
655 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
656 else
657 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
658
659 if (ch->ch_c_cflag & CBAUDEX)
660 iindex = 1;
661
662 if (ch->ch_digi.digi_flags & DIGI_FAST)
663 iindex += 2;
664
665 jindex = baud;
666
667 if ((iindex >= 0) && (iindex < 4) &&
668 (jindex >= 0) && (jindex < 16))
669 baud = bauds[iindex][jindex];
670 else
671 baud = 0;
672
673 if (baud == 0)
674 baud = 9600;
675
676
677 if (ch->ch_flags & CH_BAUD0) {
678 ch->ch_flags &= ~(CH_BAUD0);
679
680
681
682
683
684 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
685 ch->ch_mostat |= (UART_MCR_RTS);
686 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
687 ch->ch_mostat |= (UART_MCR_DTR);
688 }
689 }
690
691 if (ch->ch_c_cflag & PARENB)
692 lcr |= UART_LCR_PARITY;
693
694 if (!(ch->ch_c_cflag & PARODD))
695 lcr |= UART_LCR_EPAR;
696
697#ifdef CMSPAR
698 if (ch->ch_c_cflag & CMSPAR)
699 lcr |= UART_LCR_SPAR;
700#endif
701
702 if (ch->ch_c_cflag & CSTOPB)
703 lcr |= UART_LCR_STOP;
704
705 switch (ch->ch_c_cflag & CSIZE) {
706 case CS5:
707 lcr |= UART_LCR_WLEN5;
708 break;
709 case CS6:
710 lcr |= UART_LCR_WLEN6;
711 break;
712 case CS7:
713 lcr |= UART_LCR_WLEN7;
714 break;
715 case CS8:
716 default:
717 lcr |= UART_LCR_WLEN8;
718 break;
719 }
720
721 uart_ier = readb(&ch->ch_neo_uart->ier);
722 ier = uart_ier;
723
724 uart_lcr = readb(&ch->ch_neo_uart->lcr);
725
726 if (baud == 0)
727 baud = 9600;
728
729 quot = ch->ch_bd->bd_dividend / baud;
730
731 if (quot != 0 && ch->ch_old_baud != baud) {
732 ch->ch_old_baud = baud;
733 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
734 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
735 writeb((quot >> 8), &ch->ch_neo_uart->ier);
736 writeb(lcr, &ch->ch_neo_uart->lcr);
737 }
738
739 if (uart_lcr != lcr)
740 writeb(lcr, &ch->ch_neo_uart->lcr);
741
742 if (ch->ch_c_cflag & CREAD)
743 ier |= (UART_IER_RDI | UART_IER_RLSI);
744 else
745 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
746
747
748
749
750
751 if ((ch->ch_digi.digi_flags & CTSPACE) ||
752 (ch->ch_digi.digi_flags & RTSPACE) ||
753 (ch->ch_c_cflag & CRTSCTS) ||
754 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
755 !(ch->ch_c_cflag & CLOCAL))
756 ier |= UART_IER_MSI;
757 else
758 ier &= ~UART_IER_MSI;
759
760 ier |= UART_IER_THRI;
761
762 if (ier != uart_ier)
763 writeb(ier, &ch->ch_neo_uart->ier);
764
765 neo_set_new_start_stop_chars(ch);
766
767 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
768 neo_set_cts_flow_control(ch);
769 } else if (ch->ch_c_iflag & IXON) {
770 if ((ch->ch_startc == _POSIX_VDISABLE) ||
771 (ch->ch_stopc == _POSIX_VDISABLE))
772 neo_set_no_output_flow_control(ch);
773 else
774 neo_set_ixon_flow_control(ch);
775 } else {
776 neo_set_no_output_flow_control(ch);
777 }
778
779 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
780 neo_set_rts_flow_control(ch);
781 } else if (ch->ch_c_iflag & IXOFF) {
782 if ((ch->ch_startc == _POSIX_VDISABLE) ||
783 (ch->ch_stopc == _POSIX_VDISABLE))
784 neo_set_no_input_flow_control(ch);
785 else
786 neo_set_ixoff_flow_control(ch);
787 } else {
788 neo_set_no_input_flow_control(ch);
789 }
790
791
792
793
794
795
796 if (baud < 9600) {
797 writeb(1, &ch->ch_neo_uart->rfifo);
798 ch->ch_r_tlevel = 1;
799 }
800
801 neo_assert_modem_signals(ch);
802
803 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
804}
805
806
807static void neo_tasklet(unsigned long data)
808{
809 struct dgnc_board *bd = (struct dgnc_board *)data;
810 struct channel_t *ch;
811 unsigned long flags;
812 int i;
813 int state = 0;
814 int ports = 0;
815
816 if (!bd)
817 return;
818
819 spin_lock_irqsave(&bd->bd_lock, flags);
820 state = bd->state;
821 ports = bd->nasync;
822 spin_unlock_irqrestore(&bd->bd_lock, flags);
823
824
825
826
827
828 spin_lock_irqsave(&bd->bd_intr_lock, flags);
829
830 if ((state == BOARD_READY) && (ports > 0)) {
831 for (i = 0; i < ports; i++) {
832 ch = bd->channels[i];
833 if (!ch)
834 continue;
835
836
837
838
839
840
841
842
843
844
845 dgnc_input(ch);
846
847
848
849
850
851
852 neo_copy_data_from_queue_to_uart(ch);
853 dgnc_wakeup_writes(ch);
854
855 dgnc_carrier(ch);
856
857
858
859
860
861 if (ch->ch_stop_sending_break)
862 neo_clear_break(ch, 0);
863 }
864 }
865
866 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
867}
868
869
870static irqreturn_t neo_intr(int irq, void *voidbrd)
871{
872 struct dgnc_board *brd = voidbrd;
873 struct channel_t *ch;
874 int port = 0;
875 int type;
876 u32 uart_poll;
877 unsigned long flags;
878 unsigned long flags2;
879
880 if (!brd)
881 return IRQ_NONE;
882
883
884 spin_lock_irqsave(&brd->bd_intr_lock, flags);
885
886
887
888
889
890
891 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
892
893
894
895
896
897
898 if (!uart_poll) {
899 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
900 return IRQ_NONE;
901 }
902
903 while ((uart_poll & 0xff) != 0) {
904 type = uart_poll >> (8 + (port * 3));
905 type &= 0x7;
906
907 uart_poll &= ~(0x01 << port);
908
909 switch (type) {
910 case UART_17158_RXRDY_TIMEOUT:
911
912
913
914
915
916 if (port >= brd->nasync)
917 break;
918
919 ch = brd->channels[port];
920 neo_copy_data_from_uart_to_queue(ch);
921
922
923
924
925
926 spin_lock_irqsave(&ch->ch_lock, flags2);
927 dgnc_check_queue_flow_control(ch);
928 spin_unlock_irqrestore(&ch->ch_lock, flags2);
929
930 break;
931
932 case UART_17158_RX_LINE_STATUS:
933
934
935
936 neo_parse_lsr(brd, port);
937 break;
938
939 case UART_17158_TXRDY:
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954 neo_parse_isr(brd, port);
955 break;
956
957 case UART_17158_MSR:
958
959 neo_parse_isr(brd, port);
960 break;
961
962 default:
963 break;
964 }
965
966 port++;
967 }
968
969 tasklet_schedule(&brd->helper_tasklet);
970
971 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
972
973 return IRQ_HANDLED;
974}
975
976
977
978
979
980
981static void neo_disable_receiver(struct channel_t *ch)
982{
983 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
984
985 tmp &= ~(UART_IER_RDI);
986 writeb(tmp, &ch->ch_neo_uart->ier);
987 neo_pci_posting_flush(ch->ch_bd);
988}
989
990
991
992
993
994
995static void neo_enable_receiver(struct channel_t *ch)
996{
997 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
998
999 tmp |= (UART_IER_RDI);
1000 writeb(tmp, &ch->ch_neo_uart->ier);
1001 neo_pci_posting_flush(ch->ch_bd);
1002}
1003
1004static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1005{
1006 int qleft = 0;
1007 unsigned char linestatus = 0;
1008 unsigned char error_mask = 0;
1009 int n = 0;
1010 int total = 0;
1011 ushort head;
1012 ushort tail;
1013 unsigned long flags;
1014
1015 if (!ch)
1016 return;
1017
1018 spin_lock_irqsave(&ch->ch_lock, flags);
1019
1020 head = ch->ch_r_head & RQUEUEMASK;
1021 tail = ch->ch_r_tail & RQUEUEMASK;
1022
1023 linestatus = ch->ch_cached_lsr;
1024 ch->ch_cached_lsr = 0;
1025
1026 qleft = tail - head - 1;
1027 if (qleft < 0)
1028 qleft += RQUEUEMASK + 1;
1029
1030 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1031
1032 total = 0;
1033 } else {
1034 total = readb(&ch->ch_neo_uart->rfifo);
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1045 total -= 1;
1046 else
1047 total -= 3;
1048 }
1049
1050 total = min(total, qleft);
1051
1052 while (total > 0) {
1053 linestatus = readb(&ch->ch_neo_uart->lsr);
1054
1055 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1056 break;
1057
1058
1059 n = min(((uint)total), (RQUEUESIZE - (uint)head));
1060
1061
1062
1063
1064
1065
1066
1067 n = min_t(uint, n, 12);
1068
1069
1070
1071
1072
1073
1074 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1075 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1076
1077 linestatus = 0;
1078
1079 memcpy_fromio(ch->ch_rqueue + head,
1080 &ch->ch_neo_uart->txrxburst, n);
1081
1082
1083
1084
1085
1086
1087 memset(ch->ch_equeue + head, 0, n);
1088
1089 head = (head + n) & RQUEUEMASK;
1090 total -= n;
1091 qleft -= n;
1092 ch->ch_rxcount += n;
1093 }
1094
1095
1096
1097
1098
1099 if (ch->ch_c_iflag & IGNBRK)
1100 error_mask |= UART_LSR_BI;
1101
1102
1103
1104
1105
1106 while (1) {
1107
1108
1109
1110
1111 linestatus |= readb(&ch->ch_neo_uart->lsr);
1112
1113
1114
1115
1116
1117
1118 if (!(linestatus & UART_LSR_DR)) {
1119 ch->ch_cached_lsr = linestatus;
1120 break;
1121 }
1122
1123
1124 linestatus &= ~UART_LSR_DR;
1125
1126
1127
1128
1129
1130
1131 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1132 linestatus &= ~(UART_LSR_THRE |
1133 UART_17158_TX_AND_FIFO_CLR);
1134 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1135 }
1136
1137 if (linestatus & error_mask) {
1138 unsigned char discard;
1139
1140 linestatus = 0;
1141 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1142 continue;
1143 }
1144
1145
1146
1147
1148
1149
1150
1151 while (qleft < 1) {
1152 tail = (tail + 1) & RQUEUEMASK;
1153 ch->ch_r_tail = tail;
1154 ch->ch_err_overrun++;
1155 qleft++;
1156 }
1157
1158 memcpy_fromio(ch->ch_rqueue + head,
1159 &ch->ch_neo_uart->txrxburst, 1);
1160 ch->ch_equeue[head] = (unsigned char)linestatus;
1161
1162 linestatus = 0;
1163
1164 head = (head + 1) & RQUEUEMASK;
1165
1166 qleft--;
1167 ch->ch_rxcount++;
1168 }
1169
1170 ch->ch_r_head = head & RQUEUEMASK;
1171 ch->ch_e_head = head & EQUEUEMASK;
1172
1173 spin_unlock_irqrestore(&ch->ch_lock, flags);
1174}
1175
1176
1177
1178
1179
1180static int neo_drain(struct tty_struct *tty, uint seconds)
1181{
1182 unsigned long flags;
1183 struct channel_t *ch;
1184 struct un_t *un;
1185 int rc = 0;
1186
1187 if (!tty)
1188 return -ENXIO;
1189
1190 un = (struct un_t *)tty->driver_data;
1191 if (!un)
1192 return -ENXIO;
1193
1194 ch = un->un_ch;
1195 if (!ch)
1196 return -ENXIO;
1197
1198 spin_lock_irqsave(&ch->ch_lock, flags);
1199 un->un_flags |= UN_EMPTY;
1200 spin_unlock_irqrestore(&ch->ch_lock, flags);
1201
1202 rc = wait_event_interruptible_timeout(un->un_flags_wait,
1203 ((un->un_flags & UN_EMPTY) == 0),
1204 msecs_to_jiffies(seconds * 1000));
1205
1206
1207 return rc;
1208}
1209
1210
1211
1212
1213
1214static void neo_flush_uart_write(struct channel_t *ch)
1215{
1216 unsigned char tmp = 0;
1217 int i = 0;
1218
1219 if (!ch)
1220 return;
1221
1222 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1223 &ch->ch_neo_uart->isr_fcr);
1224 neo_pci_posting_flush(ch->ch_bd);
1225
1226 for (i = 0; i < 10; i++) {
1227
1228
1229
1230
1231 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1232 if (tmp & 4)
1233 udelay(10);
1234 else
1235 break;
1236 }
1237
1238 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1239}
1240
1241
1242
1243
1244
1245static void neo_flush_uart_read(struct channel_t *ch)
1246{
1247 unsigned char tmp = 0;
1248 int i = 0;
1249
1250 if (!ch)
1251 return;
1252
1253 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1254 &ch->ch_neo_uart->isr_fcr);
1255 neo_pci_posting_flush(ch->ch_bd);
1256
1257 for (i = 0; i < 10; i++) {
1258
1259
1260
1261
1262 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1263 if (tmp & 2)
1264 udelay(10);
1265 else
1266 break;
1267 }
1268}
1269
1270static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1271{
1272 ushort head;
1273 ushort tail;
1274 int n;
1275 int s;
1276 int qlen;
1277 uint len_written = 0;
1278 unsigned long flags;
1279
1280 if (!ch)
1281 return;
1282
1283 spin_lock_irqsave(&ch->ch_lock, flags);
1284
1285 if (ch->ch_w_tail == ch->ch_w_head)
1286 goto exit_unlock;
1287
1288
1289 if ((ch->ch_flags & CH_FORCED_STOP) ||
1290 (ch->ch_flags & CH_BREAK_SENDING))
1291 goto exit_unlock;
1292
1293 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1294
1295 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
1296
1297 ch->ch_cached_lsr |= lsrbits;
1298 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1299 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1300
1301
1302
1303
1304
1305
1306 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1307 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1308 ch->ch_mostat |= (UART_MCR_RTS);
1309 neo_assert_modem_signals(ch);
1310 }
1311 ch->ch_tun.un_flags |= (UN_EMPTY);
1312 }
1313
1314
1315
1316
1317
1318 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1319 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1320 ch->ch_mostat |= (UART_MCR_DTR);
1321 neo_assert_modem_signals(ch);
1322 }
1323 ch->ch_tun.un_flags |= (UN_EMPTY);
1324 }
1325
1326 writeb(ch->ch_wqueue[ch->ch_w_tail],
1327 &ch->ch_neo_uart->txrx);
1328 ch->ch_w_tail++;
1329 ch->ch_w_tail &= WQUEUEMASK;
1330 ch->ch_txcount++;
1331 }
1332
1333 goto exit_unlock;
1334 }
1335
1336
1337
1338 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1339 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1340 goto exit_unlock;
1341
1342 len_written = 0;
1343
1344 n = readb(&ch->ch_neo_uart->tfifo);
1345
1346 if ((unsigned int)n > ch->ch_t_tlevel)
1347 goto exit_unlock;
1348
1349 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1350 } else {
1351 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1352 }
1353
1354 head = ch->ch_w_head & WQUEUEMASK;
1355 tail = ch->ch_w_tail & WQUEUEMASK;
1356 qlen = (head - tail) & WQUEUEMASK;
1357
1358 n = min(n, qlen);
1359
1360 while (n > 0) {
1361 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1362 s = min(s, n);
1363
1364 if (s <= 0)
1365 break;
1366
1367
1368
1369
1370
1371
1372 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1373 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1374 ch->ch_mostat |= (UART_MCR_RTS);
1375 neo_assert_modem_signals(ch);
1376 }
1377 ch->ch_tun.un_flags |= (UN_EMPTY);
1378 }
1379
1380
1381
1382
1383
1384
1385 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1386 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1387 ch->ch_mostat |= (UART_MCR_DTR);
1388 neo_assert_modem_signals(ch);
1389 }
1390 ch->ch_tun.un_flags |= (UN_EMPTY);
1391 }
1392
1393 memcpy_toio(&ch->ch_neo_uart->txrxburst,
1394 ch->ch_wqueue + tail, s);
1395
1396 tail = (tail + s) & WQUEUEMASK;
1397 n -= s;
1398 ch->ch_txcount += s;
1399 len_written += s;
1400 }
1401
1402 ch->ch_w_tail = tail & WQUEUEMASK;
1403
1404 if (len_written > 0) {
1405 neo_pci_posting_flush(ch->ch_bd);
1406 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1407 }
1408
1409exit_unlock:
1410 spin_unlock_irqrestore(&ch->ch_lock, flags);
1411}
1412
1413static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
1414{
1415 unsigned char msignals = signals;
1416
1417 if (!ch)
1418 return;
1419
1420
1421
1422
1423
1424 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1425 unsigned char mswap = msignals;
1426
1427 if (mswap & UART_MSR_DDCD) {
1428 msignals &= ~UART_MSR_DDCD;
1429 msignals |= UART_MSR_DDSR;
1430 }
1431 if (mswap & UART_MSR_DDSR) {
1432 msignals &= ~UART_MSR_DDSR;
1433 msignals |= UART_MSR_DDCD;
1434 }
1435 if (mswap & UART_MSR_DCD) {
1436 msignals &= ~UART_MSR_DCD;
1437 msignals |= UART_MSR_DSR;
1438 }
1439 if (mswap & UART_MSR_DSR) {
1440 msignals &= ~UART_MSR_DSR;
1441 msignals |= UART_MSR_DCD;
1442 }
1443 }
1444
1445
1446 msignals &= 0xf0;
1447
1448 if (msignals & UART_MSR_DCD)
1449 ch->ch_mistat |= UART_MSR_DCD;
1450 else
1451 ch->ch_mistat &= ~UART_MSR_DCD;
1452
1453 if (msignals & UART_MSR_DSR)
1454 ch->ch_mistat |= UART_MSR_DSR;
1455 else
1456 ch->ch_mistat &= ~UART_MSR_DSR;
1457
1458 if (msignals & UART_MSR_RI)
1459 ch->ch_mistat |= UART_MSR_RI;
1460 else
1461 ch->ch_mistat &= ~UART_MSR_RI;
1462
1463 if (msignals & UART_MSR_CTS)
1464 ch->ch_mistat |= UART_MSR_CTS;
1465 else
1466 ch->ch_mistat &= ~UART_MSR_CTS;
1467}
1468
1469
1470static void neo_assert_modem_signals(struct channel_t *ch)
1471{
1472 unsigned char out;
1473
1474 if (!ch)
1475 return;
1476
1477 out = ch->ch_mostat;
1478
1479 if (ch->ch_flags & CH_LOOPBACK)
1480 out |= UART_MCR_LOOP;
1481
1482 writeb(out, &ch->ch_neo_uart->mcr);
1483 neo_pci_posting_flush(ch->ch_bd);
1484
1485
1486 udelay(10);
1487}
1488
1489static void neo_send_start_character(struct channel_t *ch)
1490{
1491 if (!ch)
1492 return;
1493
1494 if (ch->ch_startc != _POSIX_VDISABLE) {
1495 ch->ch_xon_sends++;
1496 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1497 neo_pci_posting_flush(ch->ch_bd);
1498 udelay(10);
1499 }
1500}
1501
1502static void neo_send_stop_character(struct channel_t *ch)
1503{
1504 if (!ch)
1505 return;
1506
1507 if (ch->ch_stopc != _POSIX_VDISABLE) {
1508 ch->ch_xoff_sends++;
1509 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1510 neo_pci_posting_flush(ch->ch_bd);
1511 udelay(10);
1512 }
1513}
1514
1515
1516
1517static void neo_uart_init(struct channel_t *ch)
1518{
1519 writeb(0, &ch->ch_neo_uart->ier);
1520 writeb(0, &ch->ch_neo_uart->efr);
1521 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1522
1523
1524 readb(&ch->ch_neo_uart->txrx);
1525 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1526 &ch->ch_neo_uart->isr_fcr);
1527 readb(&ch->ch_neo_uart->lsr);
1528 readb(&ch->ch_neo_uart->msr);
1529
1530 ch->ch_flags |= CH_FIFO_ENABLED;
1531
1532
1533 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1534 neo_pci_posting_flush(ch->ch_bd);
1535}
1536
1537
1538static void neo_uart_off(struct channel_t *ch)
1539{
1540
1541 writeb(0, &ch->ch_neo_uart->efr);
1542
1543
1544 writeb(0, &ch->ch_neo_uart->ier);
1545 neo_pci_posting_flush(ch->ch_bd);
1546}
1547
1548static uint neo_get_uart_bytes_left(struct channel_t *ch)
1549{
1550 unsigned char left = 0;
1551 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
1552
1553
1554 ch->ch_cached_lsr |= lsr;
1555
1556
1557 if (!(lsr & UART_LSR_TEMT)) {
1558 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1559 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1560 left = 1;
1561 } else {
1562 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1563 left = 0;
1564 }
1565
1566 return left;
1567}
1568
1569
1570static void neo_send_break(struct channel_t *ch, int msecs)
1571{
1572
1573
1574 if (msecs == 0) {
1575 if (ch->ch_flags & CH_BREAK_SENDING) {
1576 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1577
1578 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1579 neo_pci_posting_flush(ch->ch_bd);
1580 ch->ch_flags &= ~(CH_BREAK_SENDING);
1581 ch->ch_stop_sending_break = 0;
1582 }
1583 return;
1584 }
1585
1586
1587
1588
1589
1590
1591 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1592
1593
1594 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1595 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1596
1597 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1598 neo_pci_posting_flush(ch->ch_bd);
1599 ch->ch_flags |= (CH_BREAK_SENDING);
1600 }
1601}
1602
1603
1604
1605
1606
1607
1608
1609static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1610{
1611 if (!ch)
1612 return;
1613
1614 writeb(c, &ch->ch_neo_uart->txrx);
1615 neo_pci_posting_flush(ch->ch_bd);
1616}
1617
1618static unsigned int neo_read_eeprom(unsigned char __iomem *base,
1619 unsigned int address)
1620{
1621 unsigned int enable;
1622 unsigned int bits;
1623 unsigned int databit;
1624 unsigned int val;
1625
1626
1627 writeb(NEO_EECS, base + NEO_EEREG);
1628
1629 enable = address | 0x180;
1630
1631 for (bits = 9; bits--; ) {
1632 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1633
1634 writeb(databit | NEO_EECS, base + NEO_EEREG);
1635 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1636 }
1637
1638 val = 0;
1639
1640 for (bits = 17; bits--; ) {
1641
1642 writeb(NEO_EECS, base + NEO_EEREG);
1643 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1644 val <<= 1;
1645
1646 if (readb(base + NEO_EEREG) & NEO_EEDO)
1647 val |= 1;
1648 }
1649
1650
1651 writeb(NEO_EECS, base + NEO_EEREG);
1652
1653
1654 writeb(0x00, base + NEO_EEREG);
1655
1656 return val;
1657}
1658
1659static void neo_vpd(struct dgnc_board *brd)
1660{
1661 unsigned int i = 0;
1662 unsigned int a;
1663
1664 if (!brd)
1665 return;
1666
1667 if (!brd->re_map_membase)
1668 return;
1669
1670
1671 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1672 a = neo_read_eeprom(brd->re_map_membase, i);
1673 brd->vpd[i * 2] = a & 0xff;
1674 brd->vpd[(i * 2) + 1] = (a >> 8) & 0xff;
1675 }
1676
1677
1678
1679
1680
1681
1682
1683 if (((brd->vpd[0x08] != 0x82) &&
1684 (brd->vpd[0x10] != 0x82)) ||
1685 (brd->vpd[0x7F] != 0x78)) {
1686 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1687 } else {
1688
1689 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1690 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1691 strncpy(brd->serial_num, &brd->vpd[i + 3], 9);
1692 }
1693}
1694