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22#ifndef _INTEL_IOMMU_H_
23#define _INTEL_IOMMU_H_
24
25#include <linux/types.h>
26#include <linux/iova.h>
27#include <linux/io.h>
28#include <linux/idr.h>
29#include <linux/dma_remapping.h>
30#include <linux/mmu_notifier.h>
31#include <linux/list.h>
32#include <linux/iommu.h>
33#include <linux/io-64-nonatomic-lo-hi.h>
34
35#include <asm/cacheflush.h>
36#include <asm/iommu.h>
37
38
39
40
41
42#define DMAR_VER_REG 0x0
43#define DMAR_CAP_REG 0x8
44#define DMAR_ECAP_REG 0x10
45#define DMAR_GCMD_REG 0x18
46#define DMAR_GSTS_REG 0x1c
47#define DMAR_RTADDR_REG 0x20
48#define DMAR_CCMD_REG 0x28
49#define DMAR_FSTS_REG 0x34
50#define DMAR_FECTL_REG 0x38
51#define DMAR_FEDATA_REG 0x3c
52#define DMAR_FEADDR_REG 0x40
53#define DMAR_FEUADDR_REG 0x44
54#define DMAR_AFLOG_REG 0x58
55#define DMAR_PMEN_REG 0x64
56#define DMAR_PLMBASE_REG 0x68
57#define DMAR_PLMLIMIT_REG 0x6c
58#define DMAR_PHMBASE_REG 0x70
59#define DMAR_PHMLIMIT_REG 0x78
60#define DMAR_IQH_REG 0x80
61#define DMAR_IQT_REG 0x88
62#define DMAR_IQ_SHIFT 4
63#define DMAR_IQA_REG 0x90
64#define DMAR_ICS_REG 0x9c
65#define DMAR_IRTA_REG 0xb8
66#define DMAR_PQH_REG 0xc0
67#define DMAR_PQT_REG 0xc8
68#define DMAR_PQA_REG 0xd0
69#define DMAR_PRS_REG 0xdc
70#define DMAR_PECTL_REG 0xe0
71#define DMAR_PEDATA_REG 0xe4
72#define DMAR_PEADDR_REG 0xe8
73#define DMAR_PEUADDR_REG 0xec
74
75#define OFFSET_STRIDE (9)
76
77#define dmar_readq(a) readq(a)
78#define dmar_writeq(a,v) writeq(v,a)
79
80#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
81#define DMAR_VER_MINOR(v) ((v) & 0x0f)
82
83
84
85
86#define cap_pi_support(c) (((c) >> 59) & 1)
87#define cap_read_drain(c) (((c) >> 55) & 1)
88#define cap_write_drain(c) (((c) >> 54) & 1)
89#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
90#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
91#define cap_pgsel_inv(c) (((c) >> 39) & 1)
92
93#define cap_super_page_val(c) (((c) >> 34) & 0xf)
94#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
95 * OFFSET_STRIDE) + 21)
96
97#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
98#define cap_max_fault_reg_offset(c) \
99 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
100
101#define cap_zlr(c) (((c) >> 22) & 1)
102#define cap_isoch(c) (((c) >> 23) & 1)
103#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
104#define cap_sagaw(c) (((c) >> 8) & 0x1f)
105#define cap_caching_mode(c) (((c) >> 7) & 1)
106#define cap_phmr(c) (((c) >> 6) & 1)
107#define cap_plmr(c) (((c) >> 5) & 1)
108#define cap_rwbf(c) (((c) >> 4) & 1)
109#define cap_afl(c) (((c) >> 3) & 1)
110#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
111
112
113
114
115#define ecap_pasid(e) ((e >> 40) & 0x1)
116#define ecap_pss(e) ((e >> 35) & 0x1f)
117#define ecap_eafs(e) ((e >> 34) & 0x1)
118#define ecap_nwfs(e) ((e >> 33) & 0x1)
119#define ecap_srs(e) ((e >> 31) & 0x1)
120#define ecap_ers(e) ((e >> 30) & 0x1)
121#define ecap_prs(e) ((e >> 29) & 0x1)
122#define ecap_broken_pasid(e) ((e >> 28) & 0x1)
123#define ecap_dis(e) ((e >> 27) & 0x1)
124#define ecap_nest(e) ((e >> 26) & 0x1)
125#define ecap_mts(e) ((e >> 25) & 0x1)
126#define ecap_ecs(e) ((e >> 24) & 0x1)
127#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
128#define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
129#define ecap_coherent(e) ((e) & 0x1)
130#define ecap_qis(e) ((e) & 0x2)
131#define ecap_pass_through(e) ((e >> 6) & 0x1)
132#define ecap_eim_support(e) ((e >> 4) & 0x1)
133#define ecap_ir_support(e) ((e >> 3) & 0x1)
134#define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
135#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
136#define ecap_sc_support(e) ((e >> 7) & 0x1)
137
138
139#define DMA_TLB_FLUSH_GRANU_OFFSET 60
140#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
141#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
142#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
143#define DMA_TLB_IIRG(type) ((type >> 60) & 3)
144#define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
145#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
146#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
147#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
148#define DMA_TLB_IVT (((u64)1) << 63)
149#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
150#define DMA_TLB_MAX_SIZE (0x3f)
151
152
153#define DMA_CCMD_INVL_GRANU_OFFSET 61
154#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
155#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
156#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
157#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
158#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
159#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
160#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
161#define DMA_ID_TLB_ADDR(addr) (addr)
162#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
163
164
165#define DMA_PMEN_EPM (((u32)1)<<31)
166#define DMA_PMEN_PRS (((u32)1)<<0)
167
168
169#define DMA_GCMD_TE (((u32)1) << 31)
170#define DMA_GCMD_SRTP (((u32)1) << 30)
171#define DMA_GCMD_SFL (((u32)1) << 29)
172#define DMA_GCMD_EAFL (((u32)1) << 28)
173#define DMA_GCMD_WBF (((u32)1) << 27)
174#define DMA_GCMD_QIE (((u32)1) << 26)
175#define DMA_GCMD_SIRTP (((u32)1) << 24)
176#define DMA_GCMD_IRE (((u32) 1) << 25)
177#define DMA_GCMD_CFI (((u32) 1) << 23)
178
179
180#define DMA_GSTS_TES (((u32)1) << 31)
181#define DMA_GSTS_RTPS (((u32)1) << 30)
182#define DMA_GSTS_FLS (((u32)1) << 29)
183#define DMA_GSTS_AFLS (((u32)1) << 28)
184#define DMA_GSTS_WBFS (((u32)1) << 27)
185#define DMA_GSTS_QIES (((u32)1) << 26)
186#define DMA_GSTS_IRTPS (((u32)1) << 24)
187#define DMA_GSTS_IRES (((u32)1) << 25)
188#define DMA_GSTS_CFIS (((u32)1) << 23)
189
190
191#define DMA_RTADDR_RTT (((u64)1) << 11)
192
193
194#define DMA_CCMD_ICC (((u64)1) << 63)
195#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
196#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
197#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
198#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
199#define DMA_CCMD_MASK_NOBIT 0
200#define DMA_CCMD_MASK_1BIT 1
201#define DMA_CCMD_MASK_2BIT 2
202#define DMA_CCMD_MASK_3BIT 3
203#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
204#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
205
206
207#define DMA_FECTL_IM (((u32)1) << 31)
208
209
210#define DMA_FSTS_PPF ((u32)2)
211#define DMA_FSTS_PFO ((u32)1)
212#define DMA_FSTS_IQE (1 << 4)
213#define DMA_FSTS_ICE (1 << 5)
214#define DMA_FSTS_ITE (1 << 6)
215#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
216
217
218#define DMA_FRCD_F (((u32)1) << 31)
219#define dma_frcd_type(d) ((d >> 30) & 1)
220#define dma_frcd_fault_reason(c) (c & 0xff)
221#define dma_frcd_source_id(c) (c & 0xffff)
222
223#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
224
225
226#define DMA_PRS_PPR ((u32)1)
227
228#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
229do { \
230 cycles_t start_time = get_cycles(); \
231 while (1) { \
232 sts = op(iommu->reg + offset); \
233 if (cond) \
234 break; \
235 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
236 panic("DMAR hardware is malfunctioning\n"); \
237 cpu_relax(); \
238 } \
239} while (0)
240
241#define QI_LENGTH 256
242
243enum {
244 QI_FREE,
245 QI_IN_USE,
246 QI_DONE,
247 QI_ABORT
248};
249
250#define QI_CC_TYPE 0x1
251#define QI_IOTLB_TYPE 0x2
252#define QI_DIOTLB_TYPE 0x3
253#define QI_IEC_TYPE 0x4
254#define QI_IWD_TYPE 0x5
255#define QI_EIOTLB_TYPE 0x6
256#define QI_PC_TYPE 0x7
257#define QI_DEIOTLB_TYPE 0x8
258#define QI_PGRP_RESP_TYPE 0x9
259#define QI_PSTRM_RESP_TYPE 0xa
260
261#define QI_IEC_SELECTIVE (((u64)1) << 4)
262#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
263#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
264
265#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
266#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
267
268#define QI_IOTLB_DID(did) (((u64)did) << 16)
269#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
270#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
271#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
272#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
273#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
274#define QI_IOTLB_AM(am) (((u8)am))
275
276#define QI_CC_FM(fm) (((u64)fm) << 48)
277#define QI_CC_SID(sid) (((u64)sid) << 32)
278#define QI_CC_DID(did) (((u64)did) << 16)
279#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
280
281#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
282#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
283#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
284#define QI_DEV_IOTLB_SIZE 1
285#define QI_DEV_IOTLB_MAX_INVS 32
286
287#define QI_PC_PASID(pasid) (((u64)pasid) << 32)
288#define QI_PC_DID(did) (((u64)did) << 16)
289#define QI_PC_GRAN(gran) (((u64)gran) << 4)
290
291#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
292#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
293
294#define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
295#define QI_EIOTLB_GL(gl) (((u64)gl) << 7)
296#define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
297#define QI_EIOTLB_AM(am) (((u64)am))
298#define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
299#define QI_EIOTLB_DID(did) (((u64)did) << 16)
300#define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
301
302#define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
303#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
304#define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
305#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
306#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
307#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
308#define QI_DEV_EIOTLB_MAX_INVS 32
309
310#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
311#define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
312#define QI_PGRP_RESP_CODE(res) ((u64)(res))
313#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
314#define QI_PGRP_DID(did) (((u64)(did)) << 16)
315#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
316
317#define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
318#define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
319#define QI_PSTRM_RESP_CODE(res) ((u64)(res))
320#define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
321#define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
322#define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
323#define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
324
325#define QI_RESP_SUCCESS 0x0
326#define QI_RESP_INVALID 0x1
327#define QI_RESP_FAILURE 0xf
328
329#define QI_GRAN_ALL_ALL 0
330#define QI_GRAN_NONG_ALL 1
331#define QI_GRAN_NONG_PASID 2
332#define QI_GRAN_PSI_PASID 3
333
334struct qi_desc {
335 u64 low, high;
336};
337
338struct q_inval {
339 raw_spinlock_t q_lock;
340 struct qi_desc *desc;
341 int *desc_status;
342 int free_head;
343 int free_tail;
344 int free_cnt;
345};
346
347#ifdef CONFIG_IRQ_REMAP
348
349#define INTR_REMAP_PAGE_ORDER 8
350#define INTR_REMAP_TABLE_REG_SIZE 0xf
351#define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
352
353#define INTR_REMAP_TABLE_ENTRIES 65536
354
355struct irq_domain;
356
357struct ir_table {
358 struct irte *base;
359 unsigned long *bitmap;
360};
361#endif
362
363struct iommu_flush {
364 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
365 u8 fm, u64 type);
366 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
367 unsigned int size_order, u64 type);
368};
369
370enum {
371 SR_DMAR_FECTL_REG,
372 SR_DMAR_FEDATA_REG,
373 SR_DMAR_FEADDR_REG,
374 SR_DMAR_FEUADDR_REG,
375 MAX_SR_DMAR_REGS
376};
377
378#define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
379#define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
380
381struct pasid_entry;
382struct pasid_state_entry;
383struct page_req_dsc;
384
385struct intel_iommu {
386 void __iomem *reg;
387 u64 reg_phys;
388 u64 reg_size;
389 u64 cap;
390 u64 ecap;
391 u32 gcmd;
392 raw_spinlock_t register_lock;
393 int seq_id;
394 int agaw;
395 int msagaw;
396 unsigned int irq, pr_irq;
397 u16 segment;
398 unsigned char name[13];
399
400#ifdef CONFIG_INTEL_IOMMU
401 unsigned long *domain_ids;
402 struct dmar_domain ***domains;
403 spinlock_t lock;
404 struct root_entry *root_entry;
405
406 struct iommu_flush flush;
407#endif
408#ifdef CONFIG_INTEL_IOMMU_SVM
409
410
411
412
413
414 struct pasid_entry *pasid_table;
415 struct pasid_state_entry *pasid_state_table;
416 struct page_req_dsc *prq;
417 unsigned char prq_name[16];
418 struct idr pasid_idr;
419 u32 pasid_max;
420#endif
421 struct q_inval *qi;
422 u32 *iommu_state;
423
424#ifdef CONFIG_IRQ_REMAP
425 struct ir_table *ir_table;
426 struct irq_domain *ir_domain;
427 struct irq_domain *ir_msi_domain;
428#endif
429 struct iommu_device iommu;
430 int node;
431 u32 flags;
432};
433
434static inline void __iommu_flush_cache(
435 struct intel_iommu *iommu, void *addr, int size)
436{
437 if (!ecap_coherent(iommu->ecap))
438 clflush_cache_range(addr, size);
439}
440
441extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
442extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
443
444extern int dmar_enable_qi(struct intel_iommu *iommu);
445extern void dmar_disable_qi(struct intel_iommu *iommu);
446extern int dmar_reenable_qi(struct intel_iommu *iommu);
447extern void qi_global_iec(struct intel_iommu *iommu);
448
449extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
450 u8 fm, u64 type);
451extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
452 unsigned int size_order, u64 type);
453extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
454 u64 addr, unsigned mask);
455
456extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
457
458extern int dmar_ir_support(void);
459
460#ifdef CONFIG_INTEL_IOMMU_SVM
461extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
462extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
463extern int intel_svm_enable_prq(struct intel_iommu *iommu);
464extern int intel_svm_finish_prq(struct intel_iommu *iommu);
465
466struct svm_dev_ops;
467
468struct intel_svm_dev {
469 struct list_head list;
470 struct rcu_head rcu;
471 struct device *dev;
472 struct svm_dev_ops *ops;
473 int users;
474 u16 did;
475 u16 dev_iotlb:1;
476 u16 sid, qdep;
477};
478
479struct intel_svm {
480 struct mmu_notifier notifier;
481 struct mm_struct *mm;
482 struct intel_iommu *iommu;
483 int flags;
484 int pasid;
485 struct list_head devs;
486};
487
488extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev);
489extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
490#endif
491
492extern const struct attribute_group *intel_iommu_groups[];
493
494#endif
495