LXR linux/include/linux/perf/arm

   1/*
   2 *  linux/arch/arm/include/asm/pmu.h
   3 *
   4 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 */
  11
  12#ifndef __ARM_PMU_H__
  13#define __ARM_PMU_H__
  14
  15#include <linux/interrupt.h>
  16#include <linux/perf_event.h>
  17#include <linux/sysfs.h>
  18#include <asm/cputype.h>
  19
  20/*
  21 * struct arm_pmu_platdata - ARM PMU platform data
  22 *
  23 * @handle_irq: an optional handler which will be called from the
  24 *      interrupt and passed the address of the low level handler,
  25 *      and can be used to implement any platform specific handling
  26 *      before or after calling it.
  27 */
  28struct arm_pmu_platdata {
  29        irqreturn_t (*handle_irq)(int irq, void *dev,
  30                                  irq_handler_t pmu_handler);
  31};
  32
  33#ifdef CONFIG_ARM_PMU
  34
  35/*
  36 * The ARMv7 CPU PMU supports up to 32 event counters.
  37 */
  38#define ARMPMU_MAX_HWEVENTS             32
  39
  40#define HW_OP_UNSUPPORTED               0xFFFF
  41#define C(_x)                           PERF_COUNT_HW_CACHE_##_x
  42#define CACHE_OP_UNSUPPORTED            0xFFFF
  43
  44#define PERF_MAP_ALL_UNSUPPORTED                                        \
  45        [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
  46
  47#define PERF_CACHE_MAP_ALL_UNSUPPORTED                                  \
  48[0 ... C(MAX) - 1] = {                                                  \
  49        [0 ... C(OP_MAX) - 1] = {                                       \
  50                [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,       \
  51        },                                                              \
  52}
  53
  54/* The events for a given PMU register set. */
  55struct pmu_hw_events {
  56        /*
  57         * The events that are active on the PMU for the given index.
  58         */
  59        struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
  60
  61        /*
  62         * A 1 bit for an index indicates that the counter is being used for
  63         * an event. A 0 means that the counter can be used.
  64         */
  65        DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
  66
  67        /*
  68         * Hardware lock to serialize accesses to PMU registers. Needed for the
  69         * read/modify/write sequences.
  70         */
  71        raw_spinlock_t          pmu_lock;
  72
  73        /*
  74         * When using percpu IRQs, we need a percpu dev_id. Place it here as we
  75         * already have to allocate this struct per cpu.
  76         */
  77        struct arm_pmu          *percpu_pmu;
  78
  79        int irq;
  80};
  81
  82enum armpmu_attr_groups {
  83        ARMPMU_ATTR_GROUP_COMMON,
  84        ARMPMU_ATTR_GROUP_EVENTS,
  85        ARMPMU_ATTR_GROUP_FORMATS,
  86        ARMPMU_NR_ATTR_GROUPS
  87};
  88
  89struct arm_pmu {
  90        struct pmu      pmu;
  91        cpumask_t       active_irqs;
  92        cpumask_t       supported_cpus;
  93        char            *name;
  94        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
  95        void            (*enable)(struct perf_event *event);
  96        void            (*disable)(struct perf_event *event);
  97        int             (*get_event_idx)(struct pmu_hw_events *hw_events,
  98                                         struct perf_event *event);
  99        void            (*clear_event_idx)(struct pmu_hw_events *hw_events,
 100                                         struct perf_event *event);
 101        int             (*set_event_filter)(struct hw_perf_event *evt,
 102                                            struct perf_event_attr *attr);
 103        u32             (*read_counter)(struct perf_event *event);
 104        void            (*write_counter)(struct perf_event *event, u32 val);
 105        void            (*start)(struct arm_pmu *);
 106        void            (*stop)(struct arm_pmu *);
 107        void            (*reset)(void *);
 108        int             (*map_event)(struct perf_event *event);
 109        int             num_events;
 110        u64             max_period;
 111        bool            secure_access; /* 32-bit ARM only */
 112#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
 113        DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
 114        struct platform_device  *plat_device;
 115        struct pmu_hw_events    __percpu *hw_events;
 116        struct hlist_node       node;
 117        struct notifier_block   cpu_pm_nb;
 118        /* the attr_groups array must be NULL-terminated */
 119        const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
 120
 121        /* Only to be used by ACPI probing code */
 122        unsigned long acpi_cpuid;
 123};
 124
 125#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 126
 127u64 armpmu_event_update(struct perf_event *event);
 128
 129int armpmu_event_set_period(struct perf_event *event);
 130
 131int armpmu_map_event(struct perf_event *event,
 132                     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 133                     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
 134                                                [PERF_COUNT_HW_CACHE_OP_MAX]
 135                                                [PERF_COUNT_HW_CACHE_RESULT_MAX],
 136                     u32 raw_event_mask);
 137
 138typedef int (*armpmu_init_fn)(struct arm_pmu *);
 139
 140struct pmu_probe_info {
 141        unsigned int cpuid;
 142        unsigned int mask;
 143        armpmu_init_fn init;
 144};
 145
 146#define PMU_PROBE(_cpuid, _mask, _fn)   \
 147{                                       \
 148        .cpuid = (_cpuid),              \
 149        .mask = (_mask),                \
 150        .init = (_fn),                  \
 151}
 152
 153#define ARM_PMU_PROBE(_cpuid, _fn) \
 154        PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
 155
 156#define ARM_PMU_XSCALE_MASK     ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
 157
 158#define XSCALE_PMU_PROBE(_version, _fn) \
 159        PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
 160
 161int arm_pmu_device_probe(struct platform_device *pdev,
 162                         const struct of_device_id *of_table,
 163                         const struct pmu_probe_info *probe_table);
 164
 165#ifdef CONFIG_ACPI
 166int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
 167#else
 168static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
 169#endif
 170
 171/* Internal functions only for core arm_pmu code */
 172struct arm_pmu *armpmu_alloc(void);
 173void armpmu_free(struct arm_pmu *pmu);
 174int armpmu_register(struct arm_pmu *pmu);
 175int armpmu_request_irqs(struct arm_pmu *armpmu);
 176void armpmu_free_irqs(struct arm_pmu *armpmu);
 177int armpmu_request_irq(struct arm_pmu *armpmu, int cpu);
 178void armpmu_free_irq(struct arm_pmu *armpmu, int cpu);
 179
 180#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
 181
 182#endif /* CONFIG_ARM_PMU */
 183
 184#endif /* __ARM_PMU_H__ */
 185