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79#include "au88x0.h"
80#include "au88x0_a3d.h"
81#include <linux/delay.h>
82
83
84
85
86static int mchannels[NR_MIXIN];
87static int rampchs[NR_MIXIN];
88
89static void vortex_mixer_en_sr(vortex_t * vortex, int channel)
90{
91 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
92 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel));
93}
94static void vortex_mixer_dis_sr(vortex_t * vortex, int channel)
95{
96 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
97 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel));
98}
99
100#if 0
101static void
102vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix,
103 unsigned char channel)
104{
105 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
106 0x80);
107 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
108 0x80);
109}
110
111static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix)
112{
113 int a;
114 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
115
116 return (a);
117}
118
119static int
120vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix,
121 int channel, int *vol)
122{
123 int a;
124 if (!(mchannels[mix] & (1 << channel)))
125 return 0;
126 a = hwread(vortex->mmio,
127 VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2));
128
129
130
131
132
133
134 *vol = a;
135 return (0);
136}
137
138static unsigned int vortex_mix_boost6db(unsigned char vol)
139{
140 return (vol + 8);
141}
142
143static void vortex_mix_rampvolume(vortex_t * vortex, int mix)
144{
145 int ch;
146 char a;
147
148 for (ch = 0; ch < 0x20; ch++) {
149 if (((1 << ch) & rampchs[mix]) == 0)
150 continue;
151 a = hwread(vortex->mmio,
152 VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2));
153 if (a > -126) {
154 a -= 2;
155 hwwrite(vortex->mmio,
156 VORTEX_MIX_INVOL_A +
157 (((mix << 5) + ch) << 2), a);
158 hwwrite(vortex->mmio,
159 VORTEX_MIX_INVOL_B +
160 (((mix << 5) + ch) << 2), a);
161 } else
162 vortex_mix_killinput(vortex, mix, ch);
163 }
164}
165
166static int
167vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin)
168{
169 int addr, temp;
170 if (mixin >= 0)
171 addr = mixin;
172 else
173 addr = mixin + 3;
174 addr = ((mix << 3) + (addr >> 2)) << 2;
175 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
176 return ((temp >> (mixin & 3)) & 1);
177}
178#endif
179static void
180vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
181 unsigned char vol)
182{
183 int temp;
184 hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol);
185 if (1) {
186 temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2));
187 if ((temp != 0x80) || (vol == 0x80))
188 return;
189 }
190 hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol);
191}
192
193static void
194vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix,
195 int mixin, unsigned char vol)
196{
197 int temp;
198
199 hwwrite(vortex->mmio,
200 VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol);
201 if (1) {
202 temp =
203 hwread(vortex->mmio,
204 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2));
205 if ((temp != 0x80) || (vol == 0x80))
206 return;
207 }
208 hwwrite(vortex->mmio,
209 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol);
210}
211
212static void
213vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en)
214{
215 int temp, addr;
216
217 if (mixin < 0)
218 addr = (mixin + 3);
219 else
220 addr = mixin;
221 addr = ((mix << 3) + (addr >> 2)) << 2;
222 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
223 if (en)
224 temp |= (1 << (mixin & 3));
225 else
226 temp &= ~(1 << (mixin & 3));
227
228 hwwrite(vortex->mmio,
229 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80);
230
231 hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0);
232 hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0);
233
234 hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp);
235}
236
237static void
238vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin)
239{
240 rampchs[mix] &= ~(1 << mixin);
241 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);
242 mchannels[mix] &= ~(1 << mixin);
243 vortex_mix_setenablebit(vortex, mix, mixin, 0);
244}
245
246static void
247vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin)
248{
249 vortex_mix_killinput(vortex, mix, mixin);
250 if ((mchannels[mix] & (1 << mixin)) == 0) {
251 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);
252 mchannels[mix] |= (1 << mixin);
253 }
254 vortex_mix_setenablebit(vortex, mix, mixin, 1);
255}
256
257static void
258vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel,
259 int ramp)
260{
261 if (ramp) {
262 rampchs[mix] |= (1 << channel);
263
264
265 vortex_mix_killinput(vortex, mix, channel);
266 } else
267 vortex_mix_killinput(vortex, mix, channel);
268}
269
270static int
271vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
272{
273 int temp, lifeboat = 0, prev;
274
275 temp = hwread(vortex->mmio, VORTEX_MIXER_SR);
276 if ((temp & (1 << ch)) == 0) {
277 hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix);
278 vortex_mixer_en_sr(vortex, ch);
279 return 1;
280 }
281 prev = VORTEX_MIXER_CHNBASE + (ch << 2);
282 temp = hwread(vortex->mmio, prev);
283 while (temp & 0x10) {
284 prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2);
285 temp = hwread(vortex->mmio, prev);
286
287 if ((++lifeboat) > 0xf) {
288 dev_err(vortex->card->dev,
289 "vortex_mixer_addWTD: lifeboat overflow\n");
290 return 0;
291 }
292 }
293 hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix);
294 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
295 return 1;
296}
297
298static int
299vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
300{
301 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
302
303
304 eax = hwread(vortex->mmio, VORTEX_MIXER_SR);
305 if (((1 << ch) & eax) == 0) {
306 dev_err(vortex->card->dev, "mix ALARM %x\n", eax);
307 return 0;
308 }
309 ebp = VORTEX_MIXER_CHNBASE + (ch << 2);
310 esp18 = hwread(vortex->mmio, ebp);
311 if (esp18 & 0x10) {
312 ebx = (esp18 & 0xf);
313 if (mix == ebx) {
314 ebx = VORTEX_MIXER_RTBASE + (mix << 2);
315 edx = hwread(vortex->mmio, ebx);
316
317 hwwrite(vortex->mmio, ebp, edx);
318 hwwrite(vortex->mmio, ebx, 0);
319 } else {
320
321 edx =
322 hwread(vortex->mmio,
323 VORTEX_MIXER_RTBASE + (ebx << 2));
324
325 while ((edx & 0xf) != mix) {
326 if ((esi) > 0xf) {
327 dev_err(vortex->card->dev,
328 "mixdelWTD: error lifeboat overflow\n");
329 return 0;
330 }
331 esp14 = ebx;
332 ebx = edx & 0xf;
333 ebp = ebx << 2;
334 edx =
335 hwread(vortex->mmio,
336 VORTEX_MIXER_RTBASE + ebp);
337
338 esi++;
339 }
340
341 ebp = ebx << 2;
342 if (edx & 0x10) {
343 ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2);
344 edx = hwread(vortex->mmio, ebx);
345
346 hwwrite(vortex->mmio,
347 VORTEX_MIXER_RTBASE + ebp, edx);
348 hwwrite(vortex->mmio, ebx, 0);
349
350 } else {
351
352 if (esp14 == -1)
353 hwwrite(vortex->mmio,
354 VORTEX_MIXER_CHNBASE +
355 (ch << 2), esp18 & 0xef);
356 else {
357 ebx = (0xffffffe0 & edx) | (0xf & ebx);
358 hwwrite(vortex->mmio,
359 VORTEX_MIXER_RTBASE +
360 (esp14 << 2), ebx);
361
362 }
363 hwwrite(vortex->mmio,
364 VORTEX_MIXER_RTBASE + ebp, 0);
365 return 1;
366 }
367 }
368 } else {
369
370
371 vortex_mixer_dis_sr(vortex, ch);
372 hwwrite(vortex->mmio, ebp, 0);
373 }
374 return 1;
375}
376
377static void vortex_mixer_init(vortex_t * vortex)
378{
379 u32 addr;
380 int x;
381
382
383 memset(mchannels, 0, NR_MIXOUT * sizeof(int));
384 memset(rampchs, 0, NR_MIXOUT * sizeof(int));
385
386 addr = VORTEX_MIX_SMP + 0x17c;
387 for (x = 0x5f; x >= 0; x--) {
388 hwwrite(vortex->mmio, addr, 0);
389 addr -= 4;
390 }
391 addr = VORTEX_MIX_ENIN + 0x1fc;
392 for (x = 0x7f; x >= 0; x--) {
393 hwwrite(vortex->mmio, addr, 0);
394 addr -= 4;
395 }
396 addr = VORTEX_MIX_SMP + 0x17c;
397 for (x = 0x5f; x >= 0; x--) {
398 hwwrite(vortex->mmio, addr, 0);
399 addr -= 4;
400 }
401 addr = VORTEX_MIX_INVOL_A + 0x7fc;
402 for (x = 0x1ff; x >= 0; x--) {
403 hwwrite(vortex->mmio, addr, 0x80);
404 addr -= 4;
405 }
406 addr = VORTEX_MIX_VOL_A + 0x3c;
407 for (x = 0xf; x >= 0; x--) {
408 hwwrite(vortex->mmio, addr, 0x80);
409 addr -= 4;
410 }
411 addr = VORTEX_MIX_INVOL_B + 0x7fc;
412 for (x = 0x1ff; x >= 0; x--) {
413 hwwrite(vortex->mmio, addr, 0x80);
414 addr -= 4;
415 }
416 addr = VORTEX_MIX_VOL_B + 0x3c;
417 for (x = 0xf; x >= 0; x--) {
418 hwwrite(vortex->mmio, addr, 0x80);
419 addr -= 4;
420 }
421 addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4;
422 for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) {
423 hwwrite(vortex->mmio, addr, 0x0);
424 addr -= 4;
425 }
426 hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0);
427
428
429
430
431
432
433
434
435
436
437
438
439}
440
441
442
443static void vortex_src_en_sr(vortex_t * vortex, int channel)
444{
445 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
446 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel));
447}
448
449static void vortex_src_dis_sr(vortex_t * vortex, int channel)
450{
451 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
452 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel));
453}
454
455static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src)
456{
457 int i;
458
459 for (i = 0x1f; i >= 0; i--)
460 hwwrite(vortex->mmio,
461 VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0);
462 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0);
463 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0);
464}
465
466static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src)
467{
468 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
469 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0);
470 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
471}
472
473static void
474vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en)
475{
476 int temp;
477
478 temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE);
479 if (en)
480 temp |= 1 << src;
481 else
482 temp &= ~(1 << src);
483 hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp);
484}
485
486static int
487vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio)
488{
489 int temp, lifeboat = 0;
490
491 do {
492 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio);
493 temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
494 if ((++lifeboat) > 0x9) {
495 dev_err(vortex->card->dev, "Src cvr fail\n");
496 break;
497 }
498 }
499 while (temp != ratio);
500 return temp;
501}
502
503#if 0
504static void vortex_src_slowlock(vortex_t * vortex, unsigned char src)
505{
506 int temp;
507
508 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
509 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
510 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
511 if (temp & 0x200)
512 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
513 temp & ~0x200L);
514}
515
516static void
517vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio)
518{
519 int temp, a;
520
521 if ((ratio & 0x10000) && (ratio != 0x10000)) {
522 if (ratio & 0x3fff)
523 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1;
524 else
525 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2;
526 } else
527 a = 0xc;
528 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
529 if (((temp >> 4) & 0xf) != a)
530 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
531 (temp & 0xf) | ((a & 0xf) << 4));
532
533 vortex_src_persist_convratio(vortex, src, ratio);
534}
535
536static int
537vortex_src_checkratio(vortex_t * vortex, unsigned char src,
538 unsigned int desired_ratio)
539{
540 int hw_ratio, lifeboat = 0;
541
542 hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
543
544 while (hw_ratio != desired_ratio) {
545 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio);
546
547 if ((lifeboat++) > 15) {
548 pr_err( "Vortex: could not set src-%d from %d to %d\n",
549 src, hw_ratio, desired_ratio);
550 break;
551 }
552 }
553
554 return hw_ratio;
555}
556
557#endif
558
559
560
561
562
563
564
565
566
567
568
569
570
571static void vortex_src_setupchannel(vortex_t * card, unsigned char src,
572 unsigned int cr, unsigned int b, int sweep, int d,
573 int dirplay, int sl, unsigned int tr, int thsource)
574{
575
576
577
578
579
580
581
582 int esi, ebp = 0, esp10;
583
584 vortex_src_flushbuffers(card, src);
585
586 if (sweep) {
587 if ((tr & 0x10000) && (tr != 0x10000)) {
588 tr = 0;
589 esi = 0x7;
590 } else {
591 if ((((short)tr) < 0) && (tr != 0x8000)) {
592 tr = 0;
593 esi = 0x8;
594 } else {
595 tr = 1;
596 esi = 0xc;
597 }
598 }
599 } else {
600 if ((cr & 0x10000) && (cr != 0x10000)) {
601 tr = 0;
602 esi = 0x11 - ((cr >> 0xe) & 7);
603 if (cr & 0x3fff)
604 esi -= 1;
605 else
606 esi -= 2;
607 } else {
608 tr = 1;
609 esi = 0xc;
610 }
611 }
612 vortex_src_cleardrift(card, src);
613 vortex_src_set_throttlesource(card, src, thsource);
614
615 if ((dirplay == 0) && (sweep == 0)) {
616 if (tr)
617 esp10 = 0xf;
618 else
619 esp10 = 0xc;
620 ebp = 0;
621 } else {
622 if (tr)
623 ebp = 0xf;
624 else
625 ebp = 0xc;
626 esp10 = 0;
627 }
628 hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2),
629 (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d);
630
631 vortex_src_persist_convratio(card, src, cr);
632 hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff);
633
634 hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2),
635 (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10);
636
637
638}
639
640static void vortex_srcblock_init(vortex_t * vortex)
641{
642 u32 addr;
643 int x;
644 hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff);
645
646
647
648
649
650
651
652 addr = VORTEX_SRC_RTBASE + 0x3c;
653 for (x = 0xf; x >= 0; x--) {
654 hwwrite(vortex->mmio, addr, 0);
655 addr -= 4;
656 }
657
658
659 addr = VORTEX_SRC_CHNBASE + 0x54;
660 for (x = 0x15; x >= 0; x--) {
661 hwwrite(vortex->mmio, addr, 0);
662 addr -= 4;
663 }
664}
665
666static int
667vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
668{
669 int temp, lifeboat = 0, prev;
670
671
672 temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
673 if ((temp & (1 << ch)) == 0) {
674 hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src);
675 vortex_src_en_sr(vortex, ch);
676 return 1;
677 }
678 prev = VORTEX_SRC_CHNBASE + (ch << 2);
679 temp = hwread(vortex->mmio, prev);
680
681 while (temp & 0x10) {
682 prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2);
683
684 temp = hwread(vortex->mmio, prev);
685
686 if ((++lifeboat) > 0xf) {
687 dev_err(vortex->card->dev,
688 "vortex_src_addWTD: lifeboat overflow\n");
689 return 0;
690 }
691 }
692 hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src);
693
694 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
695 return 1;
696}
697
698static int
699vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
700{
701 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
702
703
704 eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
705 if (((1 << ch) & eax) == 0) {
706 dev_err(vortex->card->dev, "src alarm\n");
707 return 0;
708 }
709 ebp = VORTEX_SRC_CHNBASE + (ch << 2);
710 esp18 = hwread(vortex->mmio, ebp);
711 if (esp18 & 0x10) {
712 ebx = (esp18 & 0xf);
713 if (src == ebx) {
714 ebx = VORTEX_SRC_RTBASE + (src << 2);
715 edx = hwread(vortex->mmio, ebx);
716
717 hwwrite(vortex->mmio, ebp, edx);
718 hwwrite(vortex->mmio, ebx, 0);
719 } else {
720
721 edx =
722 hwread(vortex->mmio,
723 VORTEX_SRC_RTBASE + (ebx << 2));
724
725 while ((edx & 0xf) != src) {
726 if ((esi) > 0xf) {
727 dev_warn(vortex->card->dev,
728 "srcdelWTD: error, lifeboat overflow\n");
729 return 0;
730 }
731 esp14 = ebx;
732 ebx = edx & 0xf;
733 ebp = ebx << 2;
734 edx =
735 hwread(vortex->mmio,
736 VORTEX_SRC_RTBASE + ebp);
737
738 esi++;
739 }
740
741 ebp = ebx << 2;
742 if (edx & 0x10) {
743 ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2);
744 edx = hwread(vortex->mmio, ebx);
745
746 hwwrite(vortex->mmio,
747 VORTEX_SRC_RTBASE + ebp, edx);
748 hwwrite(vortex->mmio, ebx, 0);
749
750 } else {
751
752 if (esp14 == -1)
753 hwwrite(vortex->mmio,
754 VORTEX_SRC_CHNBASE +
755 (ch << 2), esp18 & 0xef);
756 else {
757 ebx = (0xffffffe0 & edx) | (0xf & ebx);
758 hwwrite(vortex->mmio,
759 VORTEX_SRC_RTBASE +
760 (esp14 << 2), ebx);
761
762 }
763 hwwrite(vortex->mmio,
764 VORTEX_SRC_RTBASE + ebp, 0);
765 return 1;
766 }
767 }
768 } else {
769
770 vortex_src_dis_sr(vortex, ch);
771 hwwrite(vortex->mmio, ebp, 0);
772 }
773 return 1;
774}
775
776
777
778static void
779vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x)
780{
781 for (x--; x >= 0; x--)
782 hwwrite(vortex->mmio,
783 VORTEX_FIFO_ADBDATA +
784 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
785}
786
787#if 0
788static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j)
789{
790 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
791#ifdef CHIP_AU8820
792 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
793 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
794#else
795 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
796 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
797#endif
798}
799#endif
800static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en)
801{
802 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
803 (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) &
804 0xffffffef) | ((1 & en) << 4) | FIFO_U1);
805}
806
807static void
808vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int stereo, int priority,
809 int empty, int valid, int f)
810{
811 int temp, lifeboat = 0;
812
813 int this_4 = 0x2;
814
815
816
817
818
819 do {
820 temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
821 if (lifeboat++ > 0xbb8) {
822 dev_err(vortex->card->dev,
823 "vortex_fifo_setadbctrl fail\n");
824 break;
825 }
826 }
827 while (temp & FIFO_RDONLY);
828
829
830
831 if (valid) {
832 if ((temp & FIFO_VALID) == 0) {
833
834 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
835#ifdef CHIP_AU8820
836 temp = (this_4 & 0x1f) << 0xb;
837#else
838 temp = (this_4 & 0x3f) << 0xc;
839#endif
840 temp = (temp & 0xfffffffd) | ((stereo & 1) << 1);
841 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
842 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
843 temp |= FIFO_U1;
844 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
845#ifdef CHIP_AU8820
846 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
847#endif
848#ifdef CHIP_AU8830
849 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
850 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
851#endif
852#ifdef CHIP_AU8810
853 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
854 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
855#endif
856 }
857 } else {
858 if (temp & FIFO_VALID) {
859#ifdef CHIP_AU8820
860 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
861#endif
862#ifdef CHIP_AU8830
863 temp =
864 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
865#endif
866#ifdef CHIP_AU8810
867 temp =
868 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
869#endif
870 } else
871
872 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
873 }
874 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp);
875 hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
876}
877
878#ifndef CHIP_AU8810
879static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x)
880{
881 if (x < 1)
882 return;
883 for (x--; x >= 0; x--)
884 hwwrite(vortex->mmio,
885 VORTEX_FIFO_WTDATA +
886 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
887}
888
889static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j)
890{
891 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
892#ifdef CHIP_AU8820
893 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
894 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
895#else
896 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
897 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
898#endif
899}
900
901static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en)
902{
903 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
904 (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) &
905 0xffffffef) | ((en & 1) << 4) | FIFO_U1);
906}
907
908static void
909vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority,
910 int empty, int valid, int f)
911{
912 int temp = 0, lifeboat = 0;
913 int this_4 = 2;
914
915 do {
916 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
917 if (lifeboat++ > 0xbb8) {
918 dev_err(vortex->card->dev,
919 "vortex_fifo_setwtctrl fail\n");
920 break;
921 }
922 }
923 while (temp & FIFO_RDONLY);
924
925 if (valid) {
926 if ((temp & FIFO_VALID) == 0) {
927 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
928#ifdef CHIP_AU8820
929 temp = (this_4 & 0x1f) << 0xb;
930#else
931 temp = (this_4 & 0x3f) << 0xc;
932#endif
933 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
934 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
935 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
936 temp |= FIFO_U1;
937 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
938#ifdef CHIP_AU8820
939 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
940#endif
941#ifdef CHIP_AU8830
942 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
943 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
944#endif
945#ifdef CHIP_AU8810
946 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
947 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
948#endif
949 }
950 } else {
951 if (temp & FIFO_VALID) {
952#ifdef CHIP_AU8820
953 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
954#endif
955#ifdef CHIP_AU8830
956 temp =
957 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
958#endif
959#ifdef CHIP_AU8810
960 temp =
961 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
962#endif
963 } else
964
965 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
966 }
967 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
968 hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
969
970
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1033}
1034
1035#endif
1036static void vortex_fifo_init(vortex_t * vortex)
1037{
1038 int x;
1039 u32 addr;
1040
1041
1042 addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4);
1043 for (x = NR_ADB - 1; x >= 0; x--) {
1044 hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1));
1045 if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1))
1046 dev_err(vortex->card->dev, "bad adb fifo reset!\n");
1047 vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE);
1048 addr -= 4;
1049 }
1050
1051#ifndef CHIP_AU8810
1052
1053 addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4);
1054 for (x = NR_WT - 1; x >= 0; x--) {
1055 hwwrite(vortex->mmio, addr, FIFO_U0);
1056 if (hwread(vortex->mmio, addr) != FIFO_U0)
1057 dev_err(vortex->card->dev,
1058 "bad wt fifo reset (0x%08x, 0x%08x)!\n",
1059 addr, hwread(vortex->mmio, addr));
1060 vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE);
1061 addr -= 4;
1062 }
1063#endif
1064
1065#ifdef CHIP_AU8820
1066 hwwrite(vortex->mmio, 0xf8c0, 0xd03);
1067#else
1068#ifdef CHIP_AU8830
1069 hwwrite(vortex->mmio, 0x17000, 0x61);
1070 hwwrite(vortex->mmio, 0x17004, 0x61);
1071#endif
1072 hwwrite(vortex->mmio, 0x17008, 0x61);
1073#endif
1074}
1075
1076
1077
1078static void vortex_adbdma_init(vortex_t * vortex)
1079{
1080}
1081
1082static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma)
1083{
1084 stream_t *dma = &vortex->dma_adb[adbdma];
1085
1086 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1087 dma->dma_ctrl);
1088}
1089
1090static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb)
1091{
1092 stream_t *dma = &vortex->dma_adb[adbdma];
1093
1094 hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2),
1095 sb << ((0xf - (adbdma & 0xf)) * 2));
1096 dma->period_real = dma->period_virt = sb;
1097}
1098
1099static void
1100vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
1101 int psize, int count)
1102{
1103 stream_t *dma = &vortex->dma_adb[adbdma];
1104
1105 dma->period_bytes = psize;
1106 dma->nr_periods = count;
1107
1108 dma->cfg0 = 0;
1109 dma->cfg1 = 0;
1110 switch (count) {
1111
1112 default:
1113 case 4:
1114 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1);
1115 hwwrite(vortex->mmio,
1116 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc,
1117 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3));
1118
1119 case 3:
1120 dma->cfg0 |= 0x12000000;
1121 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1122 hwwrite(vortex->mmio,
1123 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8,
1124 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2));
1125
1126 case 2:
1127 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1);
1128 hwwrite(vortex->mmio,
1129 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4,
1130 snd_pcm_sgbuf_get_addr(dma->substream, psize));
1131
1132 case 1:
1133 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1134 hwwrite(vortex->mmio,
1135 VORTEX_ADBDMA_BUFBASE + (adbdma << 4),
1136 snd_pcm_sgbuf_get_addr(dma->substream, 0));
1137 break;
1138 }
1139
1140
1141
1142
1143 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0);
1144 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1);
1145
1146 vortex_adbdma_setfirstbuffer(vortex, adbdma);
1147 vortex_adbdma_setstartbuffer(vortex, adbdma, 0);
1148}
1149
1150static void
1151vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir,
1152 int fmt, int stereo, u32 offset)
1153{
1154 stream_t *dma = &vortex->dma_adb[adbdma];
1155
1156 dma->dma_unknown = stereo;
1157 dma->dma_ctrl =
1158 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1159
1160 dma->dma_ctrl =
1161 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1162
1163 dma->dma_ctrl =
1164 (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
1165 dma->dma_ctrl =
1166 (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1167
1168 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1169 dma->dma_ctrl);
1170 hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2));
1171}
1172
1173static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma)
1174{
1175 stream_t *dma = &vortex->dma_adb[adbdma];
1176 int page, p, pp, delta, i;
1177
1178 page =
1179 (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) &
1180 ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1181 if (dma->nr_periods >= 4)
1182 delta = (page - dma->period_real) & 3;
1183 else {
1184 delta = (page - dma->period_real);
1185 if (delta < 0)
1186 delta += dma->nr_periods;
1187 }
1188 if (delta == 0)
1189 return 0;
1190
1191
1192 if (dma->nr_periods > 4) {
1193 for (i = 0; i < delta; i++) {
1194
1195 p = dma->period_virt + i + 4;
1196 if (p >= dma->nr_periods)
1197 p -= dma->nr_periods;
1198
1199 pp = dma->period_real + i;
1200 if (pp >= 4)
1201 pp -= 4;
1202
1203 hwwrite(vortex->mmio,
1204 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1205 snd_pcm_sgbuf_get_addr(dma->substream,
1206 dma->period_bytes * p));
1207
1208 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE +
1209 (((adbdma << 2) + pp) << 2));
1210 }
1211 }
1212 dma->period_virt += delta;
1213 dma->period_real = page;
1214 if (dma->period_virt >= dma->nr_periods)
1215 dma->period_virt -= dma->nr_periods;
1216 if (delta != 1)
1217 dev_info(vortex->card->dev,
1218 "%d virt=%d, real=%d, delta=%d\n",
1219 adbdma, dma->period_virt, dma->period_real, delta);
1220
1221 return delta;
1222}
1223
1224
1225static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma) {
1226 stream_t *dma = &vortex->dma_adb[adbdma];
1227 int p, pp, i;
1228
1229
1230 for (i=0 ; i < 4 && i < dma->nr_periods; i++) {
1231
1232 p = dma->period_virt + i;
1233 if (p >= dma->nr_periods)
1234 p -= dma->nr_periods;
1235
1236 pp = dma->period_real + i;
1237 if (dma->nr_periods < 4) {
1238 if (pp >= dma->nr_periods)
1239 pp -= dma->nr_periods;
1240 }
1241 else {
1242 if (pp >= 4)
1243 pp -= 4;
1244 }
1245 hwwrite(vortex->mmio,
1246 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1247 snd_pcm_sgbuf_get_addr(dma->substream,
1248 dma->period_bytes * p));
1249
1250 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2)+pp) << 2));
1251 }
1252}
1253
1254static inline int vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
1255{
1256 stream_t *dma = &vortex->dma_adb[adbdma];
1257 int temp, page, delta;
1258
1259 temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
1260 page = (temp & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1261 if (dma->nr_periods >= 4)
1262 delta = (page - dma->period_real) & 3;
1263 else {
1264 delta = (page - dma->period_real);
1265 if (delta < 0)
1266 delta += dma->nr_periods;
1267 }
1268 return (dma->period_virt + delta) * dma->period_bytes
1269 + (temp & (dma->period_bytes - 1));
1270}
1271
1272static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
1273{
1274 int this_8 = 0 , this_4 = 0 ;
1275 stream_t *dma = &vortex->dma_adb[adbdma];
1276
1277 switch (dma->fifo_status) {
1278 case FIFO_START:
1279 vortex_fifo_setadbvalid(vortex, adbdma,
1280 dma->fifo_enabled ? 1 : 0);
1281 break;
1282 case FIFO_STOP:
1283 this_8 = 1;
1284 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1285 dma->dma_ctrl);
1286 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1287 this_4, this_8,
1288 dma->fifo_enabled ? 1 : 0, 0);
1289 break;
1290 case FIFO_PAUSE:
1291 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1292 this_4, this_8,
1293 dma->fifo_enabled ? 1 : 0, 0);
1294 break;
1295 }
1296 dma->fifo_status = FIFO_START;
1297}
1298
1299static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma)
1300{
1301 stream_t *dma = &vortex->dma_adb[adbdma];
1302
1303 int this_8 = 1, this_4 = 0;
1304 switch (dma->fifo_status) {
1305 case FIFO_STOP:
1306 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1307 dma->dma_ctrl);
1308 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1309 this_4, this_8,
1310 dma->fifo_enabled ? 1 : 0, 0);
1311 break;
1312 case FIFO_PAUSE:
1313 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1314 this_4, this_8,
1315 dma->fifo_enabled ? 1 : 0, 0);
1316 break;
1317 }
1318 dma->fifo_status = FIFO_START;
1319}
1320
1321static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma)
1322{
1323 stream_t *dma = &vortex->dma_adb[adbdma];
1324
1325 int this_8 = 0, this_4 = 0;
1326 switch (dma->fifo_status) {
1327 case FIFO_START:
1328 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1329 this_4, this_8, 0, 0);
1330 break;
1331 case FIFO_STOP:
1332 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1333 dma->dma_ctrl);
1334 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1335 this_4, this_8, 0, 0);
1336 break;
1337 }
1338 dma->fifo_status = FIFO_PAUSE;
1339}
1340
1341static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma)
1342{
1343 stream_t *dma = &vortex->dma_adb[adbdma];
1344
1345 int this_4 = 0, this_8 = 0;
1346 if (dma->fifo_status == FIFO_START)
1347 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1348 this_4, this_8, 0, 0);
1349 else if (dma->fifo_status == FIFO_STOP)
1350 return;
1351 dma->fifo_status = FIFO_STOP;
1352 dma->fifo_enabled = 0;
1353}
1354
1355
1356
1357#ifndef CHIP_AU8810
1358static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma)
1359{
1360
1361 stream_t *dma = &vortex->dma_wt[wtdma];
1362
1363 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1364}
1365
1366static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb)
1367{
1368 stream_t *dma = &vortex->dma_wt[wtdma];
1369
1370 hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2),
1371 sb << ((0xf - (wtdma & 0xf)) * 2));
1372 dma->period_real = dma->period_virt = sb;
1373}
1374
1375static void
1376vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
1377 int psize, int count)
1378{
1379 stream_t *dma = &vortex->dma_wt[wtdma];
1380
1381 dma->period_bytes = psize;
1382 dma->nr_periods = count;
1383
1384 dma->cfg0 = 0;
1385 dma->cfg1 = 0;
1386 switch (count) {
1387
1388 default:
1389 case 4:
1390 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1);
1391 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0xc,
1392 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3));
1393
1394 case 3:
1395 dma->cfg0 |= 0x12000000;
1396 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1397 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x8,
1398 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2));
1399
1400 case 2:
1401 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1);
1402 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x4,
1403 snd_pcm_sgbuf_get_addr(dma->substream, psize));
1404
1405 case 1:
1406 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1407 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1408 snd_pcm_sgbuf_get_addr(dma->substream, 0));
1409 break;
1410 }
1411 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0);
1412 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1);
1413
1414 vortex_wtdma_setfirstbuffer(vortex, wtdma);
1415 vortex_wtdma_setstartbuffer(vortex, wtdma, 0);
1416}
1417
1418static void
1419vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d,
1420 u32 offset)
1421{
1422 stream_t *dma = &vortex->dma_wt[wtdma];
1423
1424
1425 dma->dma_unknown = d;
1426 dma->dma_ctrl = 0;
1427 dma->dma_ctrl =
1428 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1429
1430 dma->dma_ctrl =
1431 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1432
1433 dma->dma_ctrl |= (1 << DIR_SHIFT);
1434
1435 dma->dma_ctrl =
1436 (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1437
1438 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1439}
1440
1441static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma)
1442{
1443 stream_t *dma = &vortex->dma_wt[wtdma];
1444 int page, p, pp, delta, i;
1445
1446 page =
1447 (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2))
1448 >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1449 if (dma->nr_periods >= 4)
1450 delta = (page - dma->period_real) & 3;
1451 else {
1452 delta = (page - dma->period_real);
1453 if (delta < 0)
1454 delta += dma->nr_periods;
1455 }
1456 if (delta == 0)
1457 return 0;
1458
1459
1460 if (dma->nr_periods > 4) {
1461 for (i = 0; i < delta; i++) {
1462
1463 p = dma->period_virt + i + 4;
1464 if (p >= dma->nr_periods)
1465 p -= dma->nr_periods;
1466
1467 pp = dma->period_real + i;
1468 if (pp >= 4)
1469 pp -= 4;
1470 hwwrite(vortex->mmio,
1471 VORTEX_WTDMA_BUFBASE +
1472 (((wtdma << 2) + pp) << 2),
1473 snd_pcm_sgbuf_get_addr(dma->substream,
1474 dma->period_bytes * p));
1475
1476 hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE +
1477 (((wtdma << 2) + pp) << 2));
1478 }
1479 }
1480 dma->period_virt += delta;
1481 if (dma->period_virt >= dma->nr_periods)
1482 dma->period_virt -= dma->nr_periods;
1483 dma->period_real = page;
1484
1485 if (delta != 1)
1486 dev_warn(vortex->card->dev, "wt virt = %d, delta = %d\n",
1487 dma->period_virt, delta);
1488
1489 return delta;
1490}
1491
1492#if 0
1493static void
1494vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos)
1495{
1496 int temp;
1497 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1498 *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1499 *pos = temp & POS_MASK;
1500}
1501
1502static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma)
1503{
1504 return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >>
1505 POS_SHIFT) & POS_MASK);
1506}
1507#endif
1508static inline int vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma)
1509{
1510 stream_t *dma = &vortex->dma_wt[wtdma];
1511 int temp;
1512
1513 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1514 temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1));
1515 return temp;
1516}
1517
1518static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma)
1519{
1520 stream_t *dma = &vortex->dma_wt[wtdma];
1521 int this_8 = 0, this_4 = 0;
1522
1523 switch (dma->fifo_status) {
1524 case FIFO_START:
1525 vortex_fifo_setwtvalid(vortex, wtdma,
1526 dma->fifo_enabled ? 1 : 0);
1527 break;
1528 case FIFO_STOP:
1529 this_8 = 1;
1530 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1531 dma->dma_ctrl);
1532 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1533 this_4, this_8,
1534 dma->fifo_enabled ? 1 : 0, 0);
1535 break;
1536 case FIFO_PAUSE:
1537 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1538 this_4, this_8,
1539 dma->fifo_enabled ? 1 : 0, 0);
1540 break;
1541 }
1542 dma->fifo_status = FIFO_START;
1543}
1544
1545static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma)
1546{
1547 stream_t *dma = &vortex->dma_wt[wtdma];
1548
1549 int this_8 = 0, this_4 = 0;
1550 switch (dma->fifo_status) {
1551 case FIFO_STOP:
1552 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1553 dma->dma_ctrl);
1554 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1555 this_4, this_8,
1556 dma->fifo_enabled ? 1 : 0, 0);
1557 break;
1558 case FIFO_PAUSE:
1559 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1560 this_4, this_8,
1561 dma->fifo_enabled ? 1 : 0, 0);
1562 break;
1563 }
1564 dma->fifo_status = FIFO_START;
1565}
1566
1567static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma)
1568{
1569 stream_t *dma = &vortex->dma_wt[wtdma];
1570
1571 int this_8 = 0, this_4 = 0;
1572 switch (dma->fifo_status) {
1573 case FIFO_START:
1574 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1575 this_4, this_8, 0, 0);
1576 break;
1577 case FIFO_STOP:
1578 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1579 dma->dma_ctrl);
1580 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1581 this_4, this_8, 0, 0);
1582 break;
1583 }
1584 dma->fifo_status = FIFO_PAUSE;
1585}
1586
1587static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma)
1588{
1589 stream_t *dma = &vortex->dma_wt[wtdma];
1590
1591 int this_4 = 0, this_8 = 0;
1592 if (dma->fifo_status == FIFO_START)
1593 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1594 this_4, this_8, 0, 0);
1595 else if (dma->fifo_status == FIFO_STOP)
1596 return;
1597 dma->fifo_status = FIFO_STOP;
1598 dma->fifo_enabled = 0;
1599}
1600
1601#endif
1602
1603
1604typedef int ADBRamLink;
1605static void vortex_adb_init(vortex_t * vortex)
1606{
1607 int i;
1608
1609
1610 hwwrite(vortex->mmio, VORTEX_ADB_SR, 0);
1611 for (i = 0; i < VORTEX_ADB_RTBASE_COUNT; i++)
1612 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2),
1613 hwread(vortex->mmio,
1614 VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK);
1615 for (i = 0; i < VORTEX_ADB_CHNBASE_COUNT; i++) {
1616 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2),
1617 hwread(vortex->mmio,
1618 VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK);
1619 }
1620}
1621
1622static void vortex_adb_en_sr(vortex_t * vortex, int channel)
1623{
1624 hwwrite(vortex->mmio, VORTEX_ADB_SR,
1625 hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel));
1626}
1627
1628static void vortex_adb_dis_sr(vortex_t * vortex, int channel)
1629{
1630 hwwrite(vortex->mmio, VORTEX_ADB_SR,
1631 hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel));
1632}
1633
1634static void
1635vortex_adb_addroutes(vortex_t * vortex, unsigned char channel,
1636 ADBRamLink * route, int rnum)
1637{
1638 int temp, prev, lifeboat = 0;
1639
1640 if ((rnum <= 0) || (route == NULL))
1641 return;
1642
1643 rnum--;
1644 hwwrite(vortex->mmio,
1645 VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2),
1646 ROUTE_MASK);
1647 while (rnum > 0) {
1648 hwwrite(vortex->mmio,
1649 VORTEX_ADB_RTBASE +
1650 ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]);
1651 rnum--;
1652 }
1653
1654 temp =
1655 hwread(vortex->mmio,
1656 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1657 if (temp == ADB_MASK) {
1658
1659 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1660 route[0]);
1661 vortex_adb_en_sr(vortex, channel);
1662 return;
1663 }
1664
1665 do {
1666 prev = temp;
1667 temp =
1668 hwread(vortex->mmio,
1669 VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK;
1670 if ((lifeboat++) > ADB_MASK) {
1671 dev_err(vortex->card->dev,
1672 "vortex_adb_addroutes: unending route! 0x%x\n",
1673 *route);
1674 return;
1675 }
1676 }
1677 while (temp != ADB_MASK);
1678 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]);
1679}
1680
1681static void
1682vortex_adb_delroutes(vortex_t * vortex, unsigned char channel,
1683 ADBRamLink route0, ADBRamLink route1)
1684{
1685 int temp, lifeboat = 0, prev;
1686
1687
1688 temp =
1689 hwread(vortex->mmio,
1690 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1691 if (temp == (route0 & ADB_MASK)) {
1692 temp =
1693 hwread(vortex->mmio,
1694 VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2));
1695 if ((temp & ADB_MASK) == ADB_MASK)
1696 vortex_adb_dis_sr(vortex, channel);
1697 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1698 temp);
1699 return;
1700 }
1701 do {
1702 prev = temp;
1703 temp =
1704 hwread(vortex->mmio,
1705 VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK;
1706 if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) {
1707 dev_err(vortex->card->dev,
1708 "vortex_adb_delroutes: route not found! 0x%x\n",
1709 route0);
1710 return;
1711 }
1712 }
1713 while (temp != (route0 & ADB_MASK));
1714 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1715 if ((temp & ADB_MASK) == route1)
1716 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1717
1718 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp);
1719}
1720
1721static void
1722vortex_route(vortex_t * vortex, int en, unsigned char channel,
1723 unsigned char source, unsigned char dest)
1724{
1725 ADBRamLink route;
1726
1727 route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1728 if (en) {
1729 vortex_adb_addroutes(vortex, channel, &route, 1);
1730 if ((source < (OFFSET_SRCOUT + NR_SRC))
1731 && (source >= OFFSET_SRCOUT))
1732 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1733 channel);
1734 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1735 && (source >= OFFSET_MIXOUT))
1736 vortex_mixer_addWTD(vortex,
1737 (source - OFFSET_MIXOUT), channel);
1738 } else {
1739 vortex_adb_delroutes(vortex, channel, route, route);
1740 if ((source < (OFFSET_SRCOUT + NR_SRC))
1741 && (source >= OFFSET_SRCOUT))
1742 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1743 channel);
1744 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1745 && (source >= OFFSET_MIXOUT))
1746 vortex_mixer_delWTD(vortex,
1747 (source - OFFSET_MIXOUT), channel);
1748 }
1749}
1750
1751#if 0
1752static void
1753vortex_routes(vortex_t * vortex, int en, unsigned char channel,
1754 unsigned char source, unsigned char dest0, unsigned char dest1)
1755{
1756 ADBRamLink route[2];
1757
1758 route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK);
1759 route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK);
1760
1761 if (en) {
1762 vortex_adb_addroutes(vortex, channel, route, 2);
1763 if ((source < (OFFSET_SRCOUT + NR_SRC))
1764 && (source >= (OFFSET_SRCOUT)))
1765 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1766 channel);
1767 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1768 && (source >= (OFFSET_MIXOUT)))
1769 vortex_mixer_addWTD(vortex,
1770 (source - OFFSET_MIXOUT), channel);
1771 } else {
1772 vortex_adb_delroutes(vortex, channel, route[0], route[1]);
1773 if ((source < (OFFSET_SRCOUT + NR_SRC))
1774 && (source >= (OFFSET_SRCOUT)))
1775 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1776 channel);
1777 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1778 && (source >= (OFFSET_MIXOUT)))
1779 vortex_mixer_delWTD(vortex,
1780 (source - OFFSET_MIXOUT), channel);
1781 }
1782}
1783
1784#endif
1785
1786static void
1787vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch,
1788 unsigned char source0, unsigned char source1,
1789 unsigned char dest)
1790{
1791 ADBRamLink route[2];
1792
1793 route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1794 route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1795
1796 if (dest < 0x10)
1797 route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20);
1798
1799 if (en) {
1800 vortex_adb_addroutes(vortex, ch, route, 2);
1801 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1802 && (source0 >= OFFSET_SRCOUT)) {
1803 vortex_src_addWTD(vortex,
1804 (source0 - OFFSET_SRCOUT), ch);
1805 vortex_src_addWTD(vortex,
1806 (source1 - OFFSET_SRCOUT), ch);
1807 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1808 && (source0 >= OFFSET_MIXOUT)) {
1809 vortex_mixer_addWTD(vortex,
1810 (source0 - OFFSET_MIXOUT), ch);
1811 vortex_mixer_addWTD(vortex,
1812 (source1 - OFFSET_MIXOUT), ch);
1813 }
1814 } else {
1815 vortex_adb_delroutes(vortex, ch, route[0], route[1]);
1816 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1817 && (source0 >= OFFSET_SRCOUT)) {
1818 vortex_src_delWTD(vortex,
1819 (source0 - OFFSET_SRCOUT), ch);
1820 vortex_src_delWTD(vortex,
1821 (source1 - OFFSET_SRCOUT), ch);
1822 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1823 && (source0 >= OFFSET_MIXOUT)) {
1824 vortex_mixer_delWTD(vortex,
1825 (source0 - OFFSET_MIXOUT), ch);
1826 vortex_mixer_delWTD(vortex,
1827 (source1 - OFFSET_MIXOUT), ch);
1828 }
1829 }
1830}
1831
1832
1833
1834
1835static void
1836vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch,
1837 unsigned char adbdma, unsigned char src)
1838{
1839 vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src));
1840}
1841
1842
1843static void
1844vortex_connection_src_mixin(vortex_t * vortex, int en,
1845 unsigned char channel, unsigned char src,
1846 unsigned char mixin)
1847{
1848 vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin));
1849}
1850
1851
1852static void
1853vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin,
1854 unsigned char mix, int a)
1855{
1856 if (en) {
1857 vortex_mix_enableinput(vortex, mix, mixin);
1858 vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN);
1859 } else
1860 vortex_mix_disableinput(vortex, mix, mixin, a);
1861}
1862
1863
1864static void
1865vortex_connection_adb_mixin(vortex_t * vortex, int en,
1866 unsigned char channel, unsigned char source,
1867 unsigned char mixin)
1868{
1869 vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin));
1870}
1871
1872static void
1873vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch,
1874 unsigned char src, unsigned char adbdma)
1875{
1876 vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma));
1877}
1878
1879static void
1880vortex_connection_src_src_adbdma(vortex_t * vortex, int en,
1881 unsigned char ch, unsigned char src0,
1882 unsigned char src1, unsigned char adbdma)
1883{
1884
1885 vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1),
1886 ADB_DMA(adbdma));
1887}
1888
1889
1890static void
1891vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch,
1892 unsigned char mix, unsigned char dest)
1893{
1894 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest);
1895 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN);
1896}
1897
1898
1899static void
1900vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch,
1901 unsigned char mix, unsigned char src)
1902{
1903 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src));
1904 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN);
1905}
1906
1907#if 0
1908static void
1909vortex_connection_adbdma_src_src(vortex_t * vortex, int en,
1910 unsigned char channel,
1911 unsigned char adbdma, unsigned char src0,
1912 unsigned char src1)
1913{
1914 vortex_routes(vortex, en, channel, ADB_DMA(adbdma),
1915 ADB_SRCIN(src0), ADB_SRCIN(src1));
1916}
1917
1918
1919static void
1920vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en,
1921 unsigned char ch, unsigned char mix0,
1922 unsigned char mix1, unsigned char adbdma)
1923{
1924
1925 ADBRamLink routes[2];
1926 routes[0] =
1927 (((mix0 +
1928 OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK);
1929 routes[1] =
1930 (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma +
1931 0x20) &
1932 ADB_MASK);
1933 if (en) {
1934 vortex_adb_addroutes(vortex, ch, routes, 0x2);
1935 vortex_mixer_addWTD(vortex, mix0, ch);
1936 vortex_mixer_addWTD(vortex, mix1, ch);
1937 } else {
1938 vortex_adb_delroutes(vortex, ch, routes[0], routes[1]);
1939 vortex_mixer_delWTD(vortex, mix0, ch);
1940 vortex_mixer_delWTD(vortex, mix1, ch);
1941 }
1942}
1943#endif
1944
1945
1946
1947static void
1948vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[])
1949{
1950#ifdef CHIP_AU8820
1951 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1952 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1953#else
1954#if 1
1955
1956 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0));
1957 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1));
1958
1959 vortex_mix_setvolumebyte(vortex, mixers[0], 0);
1960 vortex_mix_setvolumebyte(vortex, mixers[1], 0);
1961 vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0));
1962 vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1));
1963
1964
1965 if (VORTEX_IS_QUAD(vortex)) {
1966
1967 vortex_connection_mix_adb(vortex, en, 0x11, mixers[2],
1968 ADB_CODECOUT(0 + 4));
1969 vortex_connection_mix_adb(vortex, en, 0x11, mixers[3],
1970 ADB_CODECOUT(1 + 4));
1971
1972 }
1973#else
1974
1975 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1976 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1977#endif
1978#endif
1979}
1980
1981static void
1982vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0,
1983 unsigned char mixin1)
1984{
1985
1986
1987
1988
1989
1990
1991 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0);
1992 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1);
1993}
1994
1995
1996
1997
1998static int resnum[VORTEX_RESOURCE_LAST] =
1999 { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D };
2000
2001
2002
2003
2004
2005
2006
2007static char
2008vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype)
2009{
2010 int i, qty = resnum[restype], resinuse = 0;
2011
2012 if (out) {
2013
2014 for (i = 0; i < NR_ADB; i++) {
2015 resinuse |= vortex->dma_adb[i].resources[restype];
2016 }
2017 resinuse |= vortex->fixed_res[restype];
2018
2019 for (i = 0; i < qty; i++) {
2020 if ((resinuse & (1 << i)) == 0) {
2021 if (resmap != NULL)
2022 resmap[restype] |= (1 << i);
2023 else
2024 vortex->dma_adb[i].resources[restype] |= (1 << i);
2025
2026
2027
2028
2029
2030 return i;
2031 }
2032 }
2033 } else {
2034 if (resmap == NULL)
2035 return -EINVAL;
2036
2037 for (i = 0; i < qty; i++) {
2038 if (resmap[restype] & (1 << i)) {
2039 resmap[restype] &= ~(1 << i);
2040
2041
2042
2043
2044
2045 return i;
2046 }
2047 }
2048 }
2049 dev_err(vortex->card->dev,
2050 "FATAL: ResManager: resource type %d exhausted.\n",
2051 restype);
2052 return -ENOMEM;
2053}
2054
2055
2056
2057static void vortex_connect_default(vortex_t * vortex, int en)
2058{
2059
2060 vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2061 VORTEX_RESOURCE_MIXOUT);
2062 vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2063 VORTEX_RESOURCE_MIXOUT);
2064 if (VORTEX_IS_QUAD(vortex)) {
2065 vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2066 VORTEX_RESOURCE_MIXOUT);
2067 vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2068 VORTEX_RESOURCE_MIXOUT);
2069 }
2070 vortex_connect_codecplay(vortex, en, vortex->mixplayb);
2071
2072 vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2073 VORTEX_RESOURCE_MIXIN);
2074 vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2075 VORTEX_RESOURCE_MIXIN);
2076 vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1));
2077
2078
2079#ifndef CHIP_AU8820
2080 vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2081 VORTEX_RESOURCE_MIXOUT);
2082 vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2083 VORTEX_RESOURCE_MIXOUT);
2084 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0],
2085 ADB_SPDIFOUT(0));
2086 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1],
2087 ADB_SPDIFOUT(1));
2088#endif
2089
2090#ifndef CHIP_AU8810
2091 vortex_wt_connect(vortex, en);
2092#endif
2093
2094#ifndef CHIP_AU8820
2095 vortex_Vort3D_connect(vortex, en);
2096#endif
2097
2098
2099
2100
2101
2102
2103}
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114static int
2115vortex_adb_allocroute(vortex_t *vortex, int dma, int nr_ch, int dir,
2116 int type, int subdev)
2117{
2118 stream_t *stream;
2119 int i, en;
2120 struct pcm_vol *p;
2121
2122 if (dma >= 0) {
2123 en = 0;
2124 vortex_adb_checkinout(vortex,
2125 vortex->dma_adb[dma].resources, en,
2126 VORTEX_RESOURCE_DMA);
2127 } else {
2128 en = 1;
2129 if ((dma =
2130 vortex_adb_checkinout(vortex, NULL, en,
2131 VORTEX_RESOURCE_DMA)) < 0)
2132 return -EBUSY;
2133 }
2134
2135 stream = &vortex->dma_adb[dma];
2136 stream->dma = dma;
2137 stream->dir = dir;
2138 stream->type = type;
2139
2140
2141 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
2142 int src[4], mix[4], ch_top;
2143#ifndef CHIP_AU8820
2144 int a3d = 0;
2145#endif
2146
2147 if (stream->type != VORTEX_PCM_SPDIF) {
2148 for (i = 0; i < nr_ch; i++) {
2149 if ((src[i] = vortex_adb_checkinout(vortex,
2150 stream->resources, en,
2151 VORTEX_RESOURCE_SRC)) < 0) {
2152 memset(stream->resources, 0,
2153 sizeof(stream->resources));
2154 return -EBUSY;
2155 }
2156 if (stream->type != VORTEX_PCM_A3D) {
2157 if ((mix[i] = vortex_adb_checkinout(vortex,
2158 stream->resources,
2159 en,
2160 VORTEX_RESOURCE_MIXIN)) < 0) {
2161 memset(stream->resources,
2162 0,
2163 sizeof(stream->resources));
2164 return -EBUSY;
2165 }
2166 }
2167 }
2168 }
2169#ifndef CHIP_AU8820
2170 if (stream->type == VORTEX_PCM_A3D) {
2171 if ((a3d =
2172 vortex_adb_checkinout(vortex,
2173 stream->resources, en,
2174 VORTEX_RESOURCE_A3D)) < 0) {
2175 memset(stream->resources, 0,
2176 sizeof(stream->resources));
2177 dev_err(vortex->card->dev,
2178 "out of A3D sources. Sorry\n");
2179 return -EBUSY;
2180 }
2181
2182 vortex_Vort3D_InitializeSource(&vortex->a3d[a3d], en,
2183 vortex);
2184 }
2185
2186 if ((stream->type == VORTEX_PCM_SPDIF) && (en)) {
2187 vortex_route(vortex, 0, 0x14,
2188 ADB_MIXOUT(vortex->mixspdif[0]),
2189 ADB_SPDIFOUT(0));
2190 vortex_route(vortex, 0, 0x14,
2191 ADB_MIXOUT(vortex->mixspdif[1]),
2192 ADB_SPDIFOUT(1));
2193 }
2194#endif
2195
2196 for (i = 0; i < nr_ch; i++) {
2197 if (stream->type == VORTEX_PCM_ADB) {
2198 vortex_connection_adbdma_src(vortex, en,
2199 src[nr_ch - 1],
2200 dma,
2201 src[i]);
2202 vortex_connection_src_mixin(vortex, en,
2203 0x11, src[i],
2204 mix[i]);
2205 vortex_connection_mixin_mix(vortex, en,
2206 mix[i],
2207 MIX_PLAYB(i), 0);
2208#ifndef CHIP_AU8820
2209 vortex_connection_mixin_mix(vortex, en,
2210 mix[i],
2211 MIX_SPDIF(i % 2), 0);
2212 vortex_mix_setinputvolumebyte(vortex,
2213 MIX_SPDIF(i % 2),
2214 mix[i],
2215 MIX_DEFIGAIN);
2216#endif
2217 }
2218#ifndef CHIP_AU8820
2219 if (stream->type == VORTEX_PCM_A3D) {
2220 vortex_connection_adbdma_src(vortex, en,
2221 src[nr_ch - 1],
2222 dma,
2223 src[i]);
2224 vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d));
2225
2226
2227
2228 }
2229 if (stream->type == VORTEX_PCM_SPDIF)
2230 vortex_route(vortex, en, 0x14,
2231 ADB_DMA(stream->dma),
2232 ADB_SPDIFOUT(i));
2233#endif
2234 }
2235 if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) {
2236 ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
2237 for (i = nr_ch; i < ch_top; i++) {
2238 vortex_connection_mixin_mix(vortex, en,
2239 mix[i % nr_ch],
2240 MIX_PLAYB(i), 0);
2241#ifndef CHIP_AU8820
2242 vortex_connection_mixin_mix(vortex, en,
2243 mix[i % nr_ch],
2244 MIX_SPDIF(i % 2),
2245 0);
2246 vortex_mix_setinputvolumebyte(vortex,
2247 MIX_SPDIF(i % 2),
2248 mix[i % nr_ch],
2249 MIX_DEFIGAIN);
2250#endif
2251 }
2252 if (stream->type == VORTEX_PCM_ADB && en) {
2253 p = &vortex->pcm_vol[subdev];
2254 p->dma = dma;
2255 for (i = 0; i < nr_ch; i++)
2256 p->mixin[i] = mix[i];
2257 for (i = 0; i < ch_top; i++)
2258 p->vol[i] = 0;
2259 }
2260 }
2261#ifndef CHIP_AU8820
2262 else {
2263 if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF)
2264 vortex_route(vortex, en, 0x14,
2265 ADB_DMA(stream->dma),
2266 ADB_SPDIFOUT(1));
2267 }
2268
2269 if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) {
2270 vortex_route(vortex, 1, 0x14,
2271 ADB_MIXOUT(vortex->mixspdif[0]),
2272 ADB_SPDIFOUT(0));
2273 vortex_route(vortex, 1, 0x14,
2274 ADB_MIXOUT(vortex->mixspdif[1]),
2275 ADB_SPDIFOUT(1));
2276 }
2277#endif
2278
2279 } else {
2280 int src[2], mix[2];
2281
2282 if (nr_ch < 1)
2283 return -EINVAL;
2284
2285
2286 for (i = 0; i < nr_ch; i++) {
2287 if ((mix[i] =
2288 vortex_adb_checkinout(vortex,
2289 stream->resources, en,
2290 VORTEX_RESOURCE_MIXOUT))
2291 < 0) {
2292 memset(stream->resources, 0,
2293 sizeof(stream->resources));
2294 return -EBUSY;
2295 }
2296 if ((src[i] =
2297 vortex_adb_checkinout(vortex,
2298 stream->resources, en,
2299 VORTEX_RESOURCE_SRC)) < 0) {
2300 memset(stream->resources, 0,
2301 sizeof(stream->resources));
2302 return -EBUSY;
2303 }
2304 }
2305
2306
2307 vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0);
2308 vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]);
2309 if (nr_ch == 1) {
2310 vortex_connection_mixin_mix(vortex, en,
2311 MIX_CAPT(1), mix[0], 0);
2312 vortex_connection_src_adbdma(vortex, en,
2313 src[0],
2314 src[0], dma);
2315 } else {
2316 vortex_connection_mixin_mix(vortex, en,
2317 MIX_CAPT(1), mix[1], 0);
2318 vortex_connection_mix_src(vortex, en, 0x11, mix[1],
2319 src[1]);
2320 vortex_connection_src_src_adbdma(vortex, en,
2321 src[1], src[0],
2322 src[1], dma);
2323 }
2324 }
2325 vortex->dma_adb[dma].nr_ch = nr_ch;
2326
2327#if 0
2328
2329 if (nr_ch < 4) {
2330
2331 snd_ac97_write_cache(vortex->codec,
2332 AC97_SIGMATEL_DAC2INVERT,
2333 snd_ac97_read(vortex->codec,
2334 AC97_SIGMATEL_DAC2INVERT)
2335 | 4);
2336 } else {
2337
2338 snd_ac97_write_cache(vortex->codec,
2339 AC97_SIGMATEL_DAC2INVERT,
2340 snd_ac97_read(vortex->codec,
2341 AC97_SIGMATEL_DAC2INVERT)
2342 & ~((u32)
2343 4));
2344 }
2345#endif
2346 return dma;
2347}
2348
2349
2350
2351
2352static void
2353vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir)
2354{
2355 stream_t *stream = &(vortex->dma_adb[adbdma]);
2356 int i, cvrt;
2357
2358
2359 if (dir)
2360 cvrt = SRC_RATIO(rate, 48000);
2361 else
2362 cvrt = SRC_RATIO(48000, rate);
2363
2364
2365 for (i = 0; i < NR_SRC; i++) {
2366 if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i))
2367 vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir);
2368 }
2369}
2370
2371
2372
2373static void vortex_settimer(vortex_t * vortex, int period)
2374{
2375
2376 hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period);
2377}
2378
2379#if 0
2380static void vortex_enable_timer_int(vortex_t * card)
2381{
2382 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2383 hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60);
2384}
2385
2386static void vortex_disable_timer_int(vortex_t * card)
2387{
2388 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2389 hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER);
2390}
2391
2392#endif
2393static void vortex_enable_int(vortex_t * card)
2394{
2395
2396 hwwrite(card->mmio, VORTEX_CTRL,
2397 hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE);
2398 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2399 (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24);
2400}
2401
2402static void vortex_disable_int(vortex_t * card)
2403{
2404 hwwrite(card->mmio, VORTEX_CTRL,
2405 hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE);
2406}
2407
2408static irqreturn_t vortex_interrupt(int irq, void *dev_id)
2409{
2410 vortex_t *vortex = dev_id;
2411 int i, handled;
2412 u32 source;
2413
2414
2415 if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1))
2416 return IRQ_NONE;
2417
2418
2419 if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE))
2420 return IRQ_NONE;
2421
2422 source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2423
2424 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source);
2425 hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2426
2427 if (source == 0) {
2428 dev_err(vortex->card->dev, "missing irq source\n");
2429 return IRQ_NONE;
2430 }
2431
2432 handled = 0;
2433
2434 if (unlikely(source & IRQ_ERR_MASK)) {
2435 if (source & IRQ_FATAL) {
2436 dev_err(vortex->card->dev, "IRQ fatal error\n");
2437 }
2438 if (source & IRQ_PARITY) {
2439 dev_err(vortex->card->dev, "IRQ parity error\n");
2440 }
2441 if (source & IRQ_REG) {
2442 dev_err(vortex->card->dev, "IRQ reg error\n");
2443 }
2444 if (source & IRQ_FIFO) {
2445 dev_err(vortex->card->dev, "IRQ fifo error\n");
2446 }
2447 if (source & IRQ_DMA) {
2448 dev_err(vortex->card->dev, "IRQ dma error\n");
2449 }
2450 handled = 1;
2451 }
2452 if (source & IRQ_PCMOUT) {
2453
2454 spin_lock(&vortex->lock);
2455 for (i = 0; i < NR_ADB; i++) {
2456 if (vortex->dma_adb[i].fifo_status == FIFO_START) {
2457 if (!vortex_adbdma_bufshift(vortex, i))
2458 continue;
2459 spin_unlock(&vortex->lock);
2460 snd_pcm_period_elapsed(vortex->dma_adb[i].
2461 substream);
2462 spin_lock(&vortex->lock);
2463 }
2464 }
2465#ifndef CHIP_AU8810
2466 for (i = 0; i < NR_WT; i++) {
2467 if (vortex->dma_wt[i].fifo_status == FIFO_START) {
2468
2469
2470
2471
2472
2473 vortex_wtdma_bufshift(vortex, i);
2474 spin_unlock(&vortex->lock);
2475 snd_pcm_period_elapsed(vortex->dma_wt[i].
2476 substream);
2477 spin_lock(&vortex->lock);
2478 }
2479 }
2480#endif
2481 spin_unlock(&vortex->lock);
2482 handled = 1;
2483 }
2484
2485 if (source & IRQ_TIMER) {
2486 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2487 handled = 1;
2488 }
2489 if ((source & IRQ_MIDI) && vortex->rmidi) {
2490 snd_mpu401_uart_interrupt(vortex->irq,
2491 vortex->rmidi->private_data);
2492 handled = 1;
2493 }
2494
2495 if (!handled) {
2496 dev_err(vortex->card->dev, "unknown irq source %x\n", source);
2497 }
2498 return IRQ_RETVAL(handled);
2499}
2500
2501
2502
2503#define POLL_COUNT 1000
2504static void vortex_codec_init(vortex_t * vortex)
2505{
2506 int i;
2507
2508 for (i = 0; i < 32; i++) {
2509
2510 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i);
2511 msleep(2);
2512 }
2513 if (0) {
2514 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068);
2515 msleep(1);
2516 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2517 msleep(1);
2518 } else {
2519 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2520 msleep(2);
2521 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2522 msleep(2);
2523 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8);
2524 msleep(2);
2525 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2526 msleep(2);
2527 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2528 msleep(2);
2529 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2530 }
2531 for (i = 0; i < 32; i++) {
2532 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i);
2533 msleep(5);
2534 }
2535 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8);
2536 msleep(1);
2537
2538 hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2539 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC);
2540}
2541
2542static void
2543vortex_codec_write(struct snd_ac97 * codec, unsigned short addr, unsigned short data)
2544{
2545
2546 vortex_t *card = (vortex_t *) codec->private_data;
2547 unsigned int lifeboat = 0;
2548
2549
2550 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2551 udelay(100);
2552 if (lifeboat++ > POLL_COUNT) {
2553 dev_err(card->card->dev, "ac97 codec stuck busy\n");
2554 return;
2555 }
2556 }
2557
2558 hwwrite(card->mmio, VORTEX_CODEC_IO,
2559 ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2560 ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) |
2561 VORTEX_CODEC_WRITE |
2562 (codec->num << VORTEX_CODEC_ID_SHIFT) );
2563
2564
2565 hwread(card->mmio, VORTEX_CODEC_IO);
2566}
2567
2568static unsigned short vortex_codec_read(struct snd_ac97 * codec, unsigned short addr)
2569{
2570
2571 vortex_t *card = (vortex_t *) codec->private_data;
2572 u32 read_addr, data;
2573 unsigned lifeboat = 0;
2574
2575
2576 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2577 udelay(100);
2578 if (lifeboat++ > POLL_COUNT) {
2579 dev_err(card->card->dev, "ac97 codec stuck busy\n");
2580 return 0xffff;
2581 }
2582 }
2583
2584 read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2585 (codec->num << VORTEX_CODEC_ID_SHIFT) ;
2586 hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr);
2587
2588
2589 do {
2590 udelay(100);
2591 data = hwread(card->mmio, VORTEX_CODEC_IO);
2592 if (lifeboat++ > POLL_COUNT) {
2593 dev_err(card->card->dev,
2594 "ac97 address never arrived\n");
2595 return 0xffff;
2596 }
2597 } while ((data & VORTEX_CODEC_ADDMASK) !=
2598 (addr << VORTEX_CODEC_ADDSHIFT));
2599
2600
2601 return (u16) (data & VORTEX_CODEC_DATMASK);
2602}
2603
2604
2605
2606static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode)
2607{
2608 int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0;
2609
2610
2611 hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS,
2612 hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd);
2613
2614 for (i = 0; i < 11; i++)
2615 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0);
2616
2617 hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2618 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF);
2619
2620
2621 if (this_04 && this_08) {
2622 int edi;
2623
2624 i = (((0x5DC00000 / spdif_sr) + 1) >> 1);
2625 if (i > 0x800) {
2626 if (i < 0x1ffff)
2627 edi = (i >> 1);
2628 else
2629 edi = 0x1ffff;
2630 } else {
2631 i = edi = 0x800;
2632 }
2633
2634 vortex_src_setupchannel(vortex, this_04, edi, 0, 1,
2635 this_0c, 1, 0, edi, 1);
2636 vortex_src_setupchannel(vortex, this_08, edi, 0, 1,
2637 this_0c, 1, 0, edi, 1);
2638 }
2639
2640 i = spdif_sr;
2641 spdif_sr |= 0x8c;
2642 switch (i) {
2643 case 32000:
2644 this_38 &= 0xFFFFFFFE;
2645 this_38 &= 0xFFFFFFFD;
2646 this_38 &= 0xF3FFFFFF;
2647 this_38 |= 0x03000000;
2648 this_38 &= 0xFFFFFF3F;
2649 spdif_sr &= 0xFFFFFFFD;
2650 spdif_sr |= 1;
2651 break;
2652 case 44100:
2653 this_38 &= 0xFFFFFFFE;
2654 this_38 &= 0xFFFFFFFD;
2655 this_38 &= 0xF0FFFFFF;
2656 this_38 |= 0x03000000;
2657 this_38 &= 0xFFFFFF3F;
2658 spdif_sr &= 0xFFFFFFFC;
2659 break;
2660 case 48000:
2661 if (spdif_mode == 1) {
2662 this_38 &= 0xFFFFFFFE;
2663 this_38 &= 0xFFFFFFFD;
2664 this_38 &= 0xF2FFFFFF;
2665 this_38 |= 0x02000000;
2666 this_38 &= 0xFFFFFF3F;
2667 } else {
2668
2669 this_38 |= 0x00000003;
2670 this_38 &= 0xFFFFFFBF;
2671 this_38 |= 0x80;
2672 }
2673 spdif_sr |= 2;
2674 spdif_sr &= 0xFFFFFFFE;
2675 break;
2676
2677 }
2678
2679
2680
2681 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff);
2682 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10);
2683 hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr);
2684}
2685
2686
2687
2688static int vortex_core_init(vortex_t *vortex)
2689{
2690
2691 dev_info(vortex->card->dev, "init started\n");
2692
2693 hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff);
2694 msleep(5);
2695 hwwrite(vortex->mmio, VORTEX_CTRL,
2696 hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff);
2697 msleep(5);
2698
2699 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff);
2700 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2701
2702 vortex_codec_init(vortex);
2703
2704#ifdef CHIP_AU8830
2705 hwwrite(vortex->mmio, VORTEX_CTRL,
2706 hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000);
2707#endif
2708
2709
2710 vortex_adbdma_init(vortex);
2711 hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0);
2712 vortex_adb_init(vortex);
2713
2714 vortex_fifo_init(vortex);
2715 vortex_mixer_init(vortex);
2716 vortex_srcblock_init(vortex);
2717#ifndef CHIP_AU8820
2718 vortex_eq_init(vortex);
2719 vortex_spdif_init(vortex, 48000, 1);
2720 vortex_Vort3D_enable(vortex);
2721#endif
2722#ifndef CHIP_AU8810
2723 vortex_wt_init(vortex);
2724#endif
2725
2726
2727
2728 vortex_settimer(vortex, 0x90);
2729
2730
2731
2732
2733
2734
2735
2736 dev_info(vortex->card->dev, "init.... done.\n");
2737 spin_lock_init(&vortex->lock);
2738
2739 return 0;
2740}
2741
2742static int vortex_core_shutdown(vortex_t * vortex)
2743{
2744
2745 dev_info(vortex->card->dev, "shutdown started\n");
2746#ifndef CHIP_AU8820
2747 vortex_eq_free(vortex);
2748 vortex_Vort3D_disable(vortex);
2749#endif
2750
2751 vortex_disable_int(vortex);
2752 vortex_connect_default(vortex, 0);
2753
2754 vortex_fifo_init(vortex);
2755
2756 vortex_adb_init(vortex);
2757
2758
2759
2760
2761
2762 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2763 hwwrite(vortex->mmio, VORTEX_CTRL, 0);
2764 msleep(5);
2765 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff);
2766
2767 dev_info(vortex->card->dev, "shutdown.... done.\n");
2768 return 0;
2769}
2770
2771
2772
2773static int vortex_alsafmt_aspfmt(int alsafmt, vortex_t *v)
2774{
2775 int fmt;
2776
2777 switch (alsafmt) {
2778 case SNDRV_PCM_FORMAT_U8:
2779 fmt = 0x1;
2780 break;
2781 case SNDRV_PCM_FORMAT_MU_LAW:
2782 fmt = 0x2;
2783 break;
2784 case SNDRV_PCM_FORMAT_A_LAW:
2785 fmt = 0x3;
2786 break;
2787 case SNDRV_PCM_FORMAT_SPECIAL:
2788 fmt = 0x4;
2789 break;
2790 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
2791 fmt = 0x5;
2792 break;
2793 case SNDRV_PCM_FORMAT_S16_LE:
2794 fmt = 0x8;
2795 break;
2796 case SNDRV_PCM_FORMAT_S16_BE:
2797 fmt = 0x9;
2798 break;
2799 default:
2800 fmt = 0x8;
2801 dev_err(v->card->dev,
2802 "format unsupported %d\n", alsafmt);
2803 break;
2804 }
2805 return fmt;
2806}
2807
2808
2809#if 0
2810typedef enum {
2811 ASPFMTLINEAR16 = 0,
2812 ASPFMTLINEAR8,
2813 ASPFMTULAW,
2814 ASPFMTALAW,
2815 ASPFMTSPORT,
2816 ASPFMTSPDIF,
2817} ASPENCODING;
2818
2819static int
2820vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod)
2821{
2822 int a, this_194;
2823
2824 if ((bits != 8) && (bits != 16))
2825 return -1;
2826
2827 switch (encod) {
2828 case 0:
2829 if (bits == 0x10)
2830 a = 8;
2831 break;
2832 case 1:
2833 if (bits == 8)
2834 a = 1;
2835 break;
2836 case 2:
2837 a = 2;
2838 break;
2839 case 3:
2840 a = 3;
2841 break;
2842 }
2843 switch (nch) {
2844 case 1:
2845 this_194 = 0;
2846 break;
2847 case 2:
2848 this_194 = 1;
2849 break;
2850 case 4:
2851 this_194 = 1;
2852 break;
2853 case 6:
2854 this_194 = 1;
2855 break;
2856 }
2857 return (a);
2858}
2859
2860static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch)
2861{
2862 short int d, this_148;
2863
2864 d = ((bits >> 3) * nch);
2865 this_148 = 0xbb80 / d;
2866}
2867#endif
2868